xref: /OK3568_Linux_fs/kernel/drivers/regulator/qcom_smd-regulator.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2015, Sony Mobile Communications AB.
4*4882a593Smuzhiyun  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/of.h>
9*4882a593Smuzhiyun #include <linux/of_device.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/regulator/driver.h>
12*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
13*4882a593Smuzhiyun #include <linux/soc/qcom/smd-rpm.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun struct qcom_rpm_reg {
16*4882a593Smuzhiyun 	struct device *dev;
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun 	struct qcom_smd_rpm *rpm;
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun 	u32 type;
21*4882a593Smuzhiyun 	u32 id;
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 	struct regulator_desc desc;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	int is_enabled;
26*4882a593Smuzhiyun 	int uV;
27*4882a593Smuzhiyun 	u32 load;
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	unsigned int enabled_updated:1;
30*4882a593Smuzhiyun 	unsigned int uv_updated:1;
31*4882a593Smuzhiyun 	unsigned int load_updated:1;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun struct rpm_regulator_req {
35*4882a593Smuzhiyun 	__le32 key;
36*4882a593Smuzhiyun 	__le32 nbytes;
37*4882a593Smuzhiyun 	__le32 value;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define RPM_KEY_SWEN	0x6e657773 /* "swen" */
41*4882a593Smuzhiyun #define RPM_KEY_UV	0x00007675 /* "uv" */
42*4882a593Smuzhiyun #define RPM_KEY_MA	0x0000616d /* "ma" */
43*4882a593Smuzhiyun 
rpm_reg_write_active(struct qcom_rpm_reg * vreg)44*4882a593Smuzhiyun static int rpm_reg_write_active(struct qcom_rpm_reg *vreg)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun 	struct rpm_regulator_req req[3];
47*4882a593Smuzhiyun 	int reqlen = 0;
48*4882a593Smuzhiyun 	int ret;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	if (vreg->enabled_updated) {
51*4882a593Smuzhiyun 		req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN);
52*4882a593Smuzhiyun 		req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
53*4882a593Smuzhiyun 		req[reqlen].value = cpu_to_le32(vreg->is_enabled);
54*4882a593Smuzhiyun 		reqlen++;
55*4882a593Smuzhiyun 	}
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	if (vreg->uv_updated && vreg->is_enabled) {
58*4882a593Smuzhiyun 		req[reqlen].key = cpu_to_le32(RPM_KEY_UV);
59*4882a593Smuzhiyun 		req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
60*4882a593Smuzhiyun 		req[reqlen].value = cpu_to_le32(vreg->uV);
61*4882a593Smuzhiyun 		reqlen++;
62*4882a593Smuzhiyun 	}
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	if (vreg->load_updated && vreg->is_enabled) {
65*4882a593Smuzhiyun 		req[reqlen].key = cpu_to_le32(RPM_KEY_MA);
66*4882a593Smuzhiyun 		req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
67*4882a593Smuzhiyun 		req[reqlen].value = cpu_to_le32(vreg->load / 1000);
68*4882a593Smuzhiyun 		reqlen++;
69*4882a593Smuzhiyun 	}
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	if (!reqlen)
72*4882a593Smuzhiyun 		return 0;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
75*4882a593Smuzhiyun 				 vreg->type, vreg->id,
76*4882a593Smuzhiyun 				 req, sizeof(req[0]) * reqlen);
77*4882a593Smuzhiyun 	if (!ret) {
78*4882a593Smuzhiyun 		vreg->enabled_updated = 0;
79*4882a593Smuzhiyun 		vreg->uv_updated = 0;
80*4882a593Smuzhiyun 		vreg->load_updated = 0;
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	return ret;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
rpm_reg_enable(struct regulator_dev * rdev)86*4882a593Smuzhiyun static int rpm_reg_enable(struct regulator_dev *rdev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
89*4882a593Smuzhiyun 	int ret;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	vreg->is_enabled = 1;
92*4882a593Smuzhiyun 	vreg->enabled_updated = 1;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	ret = rpm_reg_write_active(vreg);
95*4882a593Smuzhiyun 	if (ret)
96*4882a593Smuzhiyun 		vreg->is_enabled = 0;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	return ret;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
rpm_reg_is_enabled(struct regulator_dev * rdev)101*4882a593Smuzhiyun static int rpm_reg_is_enabled(struct regulator_dev *rdev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	return vreg->is_enabled;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun 
rpm_reg_disable(struct regulator_dev * rdev)108*4882a593Smuzhiyun static int rpm_reg_disable(struct regulator_dev *rdev)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
111*4882a593Smuzhiyun 	int ret;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	vreg->is_enabled = 0;
114*4882a593Smuzhiyun 	vreg->enabled_updated = 1;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	ret = rpm_reg_write_active(vreg);
117*4882a593Smuzhiyun 	if (ret)
118*4882a593Smuzhiyun 		vreg->is_enabled = 1;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	return ret;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
rpm_reg_get_voltage(struct regulator_dev * rdev)123*4882a593Smuzhiyun static int rpm_reg_get_voltage(struct regulator_dev *rdev)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	return vreg->uV;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun 
rpm_reg_set_voltage(struct regulator_dev * rdev,int min_uV,int max_uV,unsigned * selector)130*4882a593Smuzhiyun static int rpm_reg_set_voltage(struct regulator_dev *rdev,
131*4882a593Smuzhiyun 			       int min_uV,
132*4882a593Smuzhiyun 			       int max_uV,
133*4882a593Smuzhiyun 			       unsigned *selector)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
136*4882a593Smuzhiyun 	int ret;
137*4882a593Smuzhiyun 	int old_uV = vreg->uV;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	vreg->uV = min_uV;
140*4882a593Smuzhiyun 	vreg->uv_updated = 1;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	ret = rpm_reg_write_active(vreg);
143*4882a593Smuzhiyun 	if (ret)
144*4882a593Smuzhiyun 		vreg->uV = old_uV;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	return ret;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
rpm_reg_set_load(struct regulator_dev * rdev,int load_uA)149*4882a593Smuzhiyun static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
152*4882a593Smuzhiyun 	u32 old_load = vreg->load;
153*4882a593Smuzhiyun 	int ret;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	vreg->load = load_uA;
156*4882a593Smuzhiyun 	vreg->load_updated = 1;
157*4882a593Smuzhiyun 	ret = rpm_reg_write_active(vreg);
158*4882a593Smuzhiyun 	if (ret)
159*4882a593Smuzhiyun 		vreg->load = old_load;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	return ret;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun static const struct regulator_ops rpm_smps_ldo_ops = {
165*4882a593Smuzhiyun 	.enable = rpm_reg_enable,
166*4882a593Smuzhiyun 	.disable = rpm_reg_disable,
167*4882a593Smuzhiyun 	.is_enabled = rpm_reg_is_enabled,
168*4882a593Smuzhiyun 	.list_voltage = regulator_list_voltage_linear_range,
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	.get_voltage = rpm_reg_get_voltage,
171*4882a593Smuzhiyun 	.set_voltage = rpm_reg_set_voltage,
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	.set_load = rpm_reg_set_load,
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun static const struct regulator_ops rpm_smps_ldo_ops_fixed = {
177*4882a593Smuzhiyun 	.enable = rpm_reg_enable,
178*4882a593Smuzhiyun 	.disable = rpm_reg_disable,
179*4882a593Smuzhiyun 	.is_enabled = rpm_reg_is_enabled,
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	.get_voltage = rpm_reg_get_voltage,
182*4882a593Smuzhiyun 	.set_voltage = rpm_reg_set_voltage,
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	.set_load = rpm_reg_set_load,
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun static const struct regulator_ops rpm_switch_ops = {
188*4882a593Smuzhiyun 	.enable = rpm_reg_enable,
189*4882a593Smuzhiyun 	.disable = rpm_reg_disable,
190*4882a593Smuzhiyun 	.is_enabled = rpm_reg_is_enabled,
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun static const struct regulator_ops rpm_bob_ops = {
194*4882a593Smuzhiyun 	.enable = rpm_reg_enable,
195*4882a593Smuzhiyun 	.disable = rpm_reg_disable,
196*4882a593Smuzhiyun 	.is_enabled = rpm_reg_is_enabled,
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	.get_voltage = rpm_reg_get_voltage,
199*4882a593Smuzhiyun 	.set_voltage = rpm_reg_set_voltage,
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static const struct regulator_ops rpm_mp5496_ops = {
203*4882a593Smuzhiyun 	.enable = rpm_reg_enable,
204*4882a593Smuzhiyun 	.disable = rpm_reg_disable,
205*4882a593Smuzhiyun 	.is_enabled = rpm_reg_is_enabled,
206*4882a593Smuzhiyun 	.list_voltage = regulator_list_voltage_linear_range,
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	.set_voltage = rpm_reg_set_voltage,
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun static const struct regulator_desc pma8084_hfsmps = {
212*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
213*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(375000,  0,  95, 12500),
214*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
215*4882a593Smuzhiyun 	},
216*4882a593Smuzhiyun 	.n_linear_ranges = 2,
217*4882a593Smuzhiyun 	.n_voltages = 159,
218*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun static const struct regulator_desc pma8084_ftsmps = {
222*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
223*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(350000,  0, 184, 5000),
224*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
225*4882a593Smuzhiyun 	},
226*4882a593Smuzhiyun 	.n_linear_ranges = 2,
227*4882a593Smuzhiyun 	.n_voltages = 262,
228*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun static const struct regulator_desc pma8084_pldo = {
232*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
233*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE( 750000,  0,  63, 12500),
234*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
235*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
236*4882a593Smuzhiyun 	},
237*4882a593Smuzhiyun 	.n_linear_ranges = 3,
238*4882a593Smuzhiyun 	.n_voltages = 164,
239*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun static const struct regulator_desc pma8084_nldo = {
243*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
244*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
245*4882a593Smuzhiyun 	},
246*4882a593Smuzhiyun 	.n_linear_ranges = 1,
247*4882a593Smuzhiyun 	.n_voltages = 64,
248*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun static const struct regulator_desc pma8084_switch = {
252*4882a593Smuzhiyun 	.ops = &rpm_switch_ops,
253*4882a593Smuzhiyun };
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun static const struct regulator_desc pm8x41_hfsmps = {
256*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
257*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE( 375000,  0,  95, 12500),
258*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
259*4882a593Smuzhiyun 	},
260*4882a593Smuzhiyun 	.n_linear_ranges = 2,
261*4882a593Smuzhiyun 	.n_voltages = 159,
262*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun static const struct regulator_desc pm8841_ftsmps = {
266*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
267*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(350000,  0, 184, 5000),
268*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
269*4882a593Smuzhiyun 	},
270*4882a593Smuzhiyun 	.n_linear_ranges = 2,
271*4882a593Smuzhiyun 	.n_voltages = 262,
272*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun static const struct regulator_desc pm8941_boost = {
276*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
277*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000),
278*4882a593Smuzhiyun 	},
279*4882a593Smuzhiyun 	.n_linear_ranges = 1,
280*4882a593Smuzhiyun 	.n_voltages = 31,
281*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun static const struct regulator_desc pm8941_pldo = {
285*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
286*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE( 750000,  0,  63, 12500),
287*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
288*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
289*4882a593Smuzhiyun 	},
290*4882a593Smuzhiyun 	.n_linear_ranges = 3,
291*4882a593Smuzhiyun 	.n_voltages = 164,
292*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun static const struct regulator_desc pm8941_nldo = {
296*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
297*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
298*4882a593Smuzhiyun 	},
299*4882a593Smuzhiyun 	.n_linear_ranges = 1,
300*4882a593Smuzhiyun 	.n_voltages = 64,
301*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
302*4882a593Smuzhiyun };
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun static const struct regulator_desc pm8941_lnldo = {
305*4882a593Smuzhiyun 	.fixed_uV = 1740000,
306*4882a593Smuzhiyun 	.n_voltages = 1,
307*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops_fixed,
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun static const struct regulator_desc pm8941_switch = {
311*4882a593Smuzhiyun 	.ops = &rpm_switch_ops,
312*4882a593Smuzhiyun };
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun static const struct regulator_desc pm8916_pldo = {
315*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
316*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
317*4882a593Smuzhiyun 	},
318*4882a593Smuzhiyun 	.n_linear_ranges = 1,
319*4882a593Smuzhiyun 	.n_voltages = 128,
320*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun static const struct regulator_desc pm8916_nldo = {
324*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
325*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
326*4882a593Smuzhiyun 	},
327*4882a593Smuzhiyun 	.n_linear_ranges = 1,
328*4882a593Smuzhiyun 	.n_voltages = 94,
329*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun static const struct regulator_desc pm8916_buck_lvo_smps = {
333*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
334*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
335*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
336*4882a593Smuzhiyun 	},
337*4882a593Smuzhiyun 	.n_linear_ranges = 2,
338*4882a593Smuzhiyun 	.n_voltages = 128,
339*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
340*4882a593Smuzhiyun };
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun static const struct regulator_desc pm8916_buck_hvo_smps = {
343*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
344*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
345*4882a593Smuzhiyun 	},
346*4882a593Smuzhiyun 	.n_linear_ranges = 1,
347*4882a593Smuzhiyun 	.n_voltages = 32,
348*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun static const struct regulator_desc pm8950_hfsmps = {
352*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
353*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
354*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1550000, 96, 127, 25000),
355*4882a593Smuzhiyun 	},
356*4882a593Smuzhiyun 	.n_linear_ranges = 2,
357*4882a593Smuzhiyun 	.n_voltages = 128,
358*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
359*4882a593Smuzhiyun };
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun static const struct regulator_desc pm8950_ftsmps2p5 = {
362*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
363*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(80000, 0, 255, 5000),
364*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(160000, 256, 460, 10000),
365*4882a593Smuzhiyun 	},
366*4882a593Smuzhiyun 	.n_linear_ranges = 2,
367*4882a593Smuzhiyun 	.n_voltages = 461,
368*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
369*4882a593Smuzhiyun };
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun static const struct regulator_desc pm8950_ult_nldo = {
372*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
373*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(375000, 0, 202, 12500),
374*4882a593Smuzhiyun 	},
375*4882a593Smuzhiyun 	.n_linear_ranges = 1,
376*4882a593Smuzhiyun 	.n_voltages = 203,
377*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
378*4882a593Smuzhiyun };
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun static const struct regulator_desc pm8950_ult_pldo = {
381*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
382*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
383*4882a593Smuzhiyun 	},
384*4882a593Smuzhiyun 	.n_linear_ranges = 1,
385*4882a593Smuzhiyun 	.n_voltages = 128,
386*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
387*4882a593Smuzhiyun };
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun static const struct regulator_desc pm8950_pldo_lv = {
390*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
391*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1500000, 0, 16, 25000),
392*4882a593Smuzhiyun 	},
393*4882a593Smuzhiyun 	.n_linear_ranges = 1,
394*4882a593Smuzhiyun 	.n_voltages = 17,
395*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
396*4882a593Smuzhiyun };
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun static const struct regulator_desc pm8950_pldo = {
399*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
400*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(975000, 0, 164, 12500),
401*4882a593Smuzhiyun 	},
402*4882a593Smuzhiyun 	.n_linear_ranges = 1,
403*4882a593Smuzhiyun 	.n_voltages = 165,
404*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
405*4882a593Smuzhiyun };
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun static const struct regulator_desc pm8953_lnldo = {
408*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
409*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1380000, 8, 15, 120000),
410*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(690000, 0, 7, 60000),
411*4882a593Smuzhiyun 	},
412*4882a593Smuzhiyun 	.n_linear_ranges = 2,
413*4882a593Smuzhiyun 	.n_voltages = 16,
414*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
415*4882a593Smuzhiyun };
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun static const struct regulator_desc pm8953_ult_nldo = {
418*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
419*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
420*4882a593Smuzhiyun 	},
421*4882a593Smuzhiyun 	.n_linear_ranges = 1,
422*4882a593Smuzhiyun 	.n_voltages = 94,
423*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
424*4882a593Smuzhiyun };
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun static const struct regulator_desc pm8994_hfsmps = {
427*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
428*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE( 375000,  0,  95, 12500),
429*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
430*4882a593Smuzhiyun 	},
431*4882a593Smuzhiyun 	.n_linear_ranges = 2,
432*4882a593Smuzhiyun 	.n_voltages = 159,
433*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
434*4882a593Smuzhiyun };
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun static const struct regulator_desc pm8994_ftsmps = {
437*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
438*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(350000,  0, 199, 5000),
439*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
440*4882a593Smuzhiyun 	},
441*4882a593Smuzhiyun 	.n_linear_ranges = 2,
442*4882a593Smuzhiyun 	.n_voltages = 350,
443*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun static const struct regulator_desc pm8994_nldo = {
447*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
448*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
449*4882a593Smuzhiyun 	},
450*4882a593Smuzhiyun 	.n_linear_ranges = 1,
451*4882a593Smuzhiyun 	.n_voltages = 64,
452*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static const struct regulator_desc pm8994_pldo = {
456*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
457*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE( 750000,  0,  63, 12500),
458*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
459*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
460*4882a593Smuzhiyun 	},
461*4882a593Smuzhiyun 	.n_linear_ranges = 3,
462*4882a593Smuzhiyun 	.n_voltages = 164,
463*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
464*4882a593Smuzhiyun };
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun static const struct regulator_desc pm8994_switch = {
467*4882a593Smuzhiyun 	.ops = &rpm_switch_ops,
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun static const struct regulator_desc pm8994_lnldo = {
471*4882a593Smuzhiyun 	.fixed_uV = 1740000,
472*4882a593Smuzhiyun 	.n_voltages = 1,
473*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops_fixed,
474*4882a593Smuzhiyun };
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun static const struct regulator_desc pmi8994_ftsmps = {
477*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
478*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(350000,  0, 199, 5000),
479*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
480*4882a593Smuzhiyun 	},
481*4882a593Smuzhiyun 	.n_linear_ranges = 2,
482*4882a593Smuzhiyun 	.n_voltages = 350,
483*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
484*4882a593Smuzhiyun };
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun static const struct regulator_desc pmi8994_hfsmps = {
487*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
488*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(350000,  0,  80, 12500),
489*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(700000, 81, 141, 25000),
490*4882a593Smuzhiyun 	},
491*4882a593Smuzhiyun 	.n_linear_ranges = 2,
492*4882a593Smuzhiyun 	.n_voltages = 142,
493*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
494*4882a593Smuzhiyun };
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun static const struct regulator_desc pmi8994_bby = {
497*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
498*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(3000000, 0, 44, 50000),
499*4882a593Smuzhiyun 	},
500*4882a593Smuzhiyun 	.n_linear_ranges = 1,
501*4882a593Smuzhiyun 	.n_voltages = 45,
502*4882a593Smuzhiyun 	.ops = &rpm_bob_ops,
503*4882a593Smuzhiyun };
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun static const struct regulator_desc pm8998_ftsmps = {
506*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
507*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000),
508*4882a593Smuzhiyun 	},
509*4882a593Smuzhiyun 	.n_linear_ranges = 1,
510*4882a593Smuzhiyun 	.n_voltages = 259,
511*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
512*4882a593Smuzhiyun };
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun static const struct regulator_desc pm8998_hfsmps = {
515*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
516*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
517*4882a593Smuzhiyun 	},
518*4882a593Smuzhiyun 	.n_linear_ranges = 1,
519*4882a593Smuzhiyun 	.n_voltages = 216,
520*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
521*4882a593Smuzhiyun };
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun static const struct regulator_desc pm8998_nldo = {
524*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
525*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
526*4882a593Smuzhiyun 	},
527*4882a593Smuzhiyun 	.n_linear_ranges = 1,
528*4882a593Smuzhiyun 	.n_voltages = 128,
529*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
530*4882a593Smuzhiyun };
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun static const struct regulator_desc pm8998_pldo = {
533*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
534*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000),
535*4882a593Smuzhiyun 	},
536*4882a593Smuzhiyun 	.n_linear_ranges = 1,
537*4882a593Smuzhiyun 	.n_voltages = 256,
538*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
539*4882a593Smuzhiyun };
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun static const struct regulator_desc pm8998_pldo_lv = {
542*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
543*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000),
544*4882a593Smuzhiyun 	},
545*4882a593Smuzhiyun 	.n_linear_ranges = 1,
546*4882a593Smuzhiyun 	.n_voltages = 128,
547*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
548*4882a593Smuzhiyun };
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun static const struct regulator_desc pm8998_switch = {
551*4882a593Smuzhiyun 	.ops = &rpm_switch_ops,
552*4882a593Smuzhiyun };
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun static const struct regulator_desc pmi8998_bob = {
555*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
556*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000),
557*4882a593Smuzhiyun 	},
558*4882a593Smuzhiyun 	.n_linear_ranges = 1,
559*4882a593Smuzhiyun 	.n_voltages = 84,
560*4882a593Smuzhiyun 	.ops = &rpm_bob_ops,
561*4882a593Smuzhiyun };
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun static const struct regulator_desc pm660_ftsmps = {
564*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
565*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(355000, 0, 199, 5000),
566*4882a593Smuzhiyun 	},
567*4882a593Smuzhiyun 	.n_linear_ranges = 1,
568*4882a593Smuzhiyun 	.n_voltages = 200,
569*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
570*4882a593Smuzhiyun };
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun static const struct regulator_desc pm660_hfsmps = {
573*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
574*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(320000, 0, 216, 8000),
575*4882a593Smuzhiyun 	},
576*4882a593Smuzhiyun 	.n_linear_ranges = 1,
577*4882a593Smuzhiyun 	.n_voltages = 217,
578*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
579*4882a593Smuzhiyun };
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun static const struct regulator_desc pm660_ht_nldo = {
582*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
583*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(312000, 0, 124, 8000),
584*4882a593Smuzhiyun 	},
585*4882a593Smuzhiyun 	.n_linear_ranges = 1,
586*4882a593Smuzhiyun 	.n_voltages = 125,
587*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
588*4882a593Smuzhiyun };
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun static const struct regulator_desc pm660_ht_lvpldo = {
591*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
592*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000),
593*4882a593Smuzhiyun 	},
594*4882a593Smuzhiyun 	.n_linear_ranges = 1,
595*4882a593Smuzhiyun 	.n_voltages = 63,
596*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
597*4882a593Smuzhiyun };
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun static const struct regulator_desc pm660_nldo660 = {
600*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
601*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000),
602*4882a593Smuzhiyun 	},
603*4882a593Smuzhiyun 	.n_linear_ranges = 1,
604*4882a593Smuzhiyun 	.n_voltages = 124,
605*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
606*4882a593Smuzhiyun };
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun static const struct regulator_desc pm660_pldo660 = {
609*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
610*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
611*4882a593Smuzhiyun 	},
612*4882a593Smuzhiyun 	.n_linear_ranges = 1,
613*4882a593Smuzhiyun 	.n_voltages = 256,
614*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
615*4882a593Smuzhiyun };
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun static const struct regulator_desc pm660l_bob = {
618*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
619*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1800000, 0, 84, 32000),
620*4882a593Smuzhiyun 	},
621*4882a593Smuzhiyun 	.n_linear_ranges = 1,
622*4882a593Smuzhiyun 	.n_voltages = 85,
623*4882a593Smuzhiyun 	.ops = &rpm_bob_ops,
624*4882a593Smuzhiyun };
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun static const struct regulator_desc pms405_hfsmps3 = {
627*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
628*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
629*4882a593Smuzhiyun 	},
630*4882a593Smuzhiyun 	.n_linear_ranges = 1,
631*4882a593Smuzhiyun 	.n_voltages = 216,
632*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
633*4882a593Smuzhiyun };
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun static const struct regulator_desc pms405_nldo300 = {
636*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
637*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
638*4882a593Smuzhiyun 	},
639*4882a593Smuzhiyun 	.n_linear_ranges = 1,
640*4882a593Smuzhiyun 	.n_voltages = 128,
641*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
642*4882a593Smuzhiyun };
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun static const struct regulator_desc pms405_nldo1200 = {
645*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
646*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
647*4882a593Smuzhiyun 	},
648*4882a593Smuzhiyun 	.n_linear_ranges = 1,
649*4882a593Smuzhiyun 	.n_voltages = 128,
650*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
651*4882a593Smuzhiyun };
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun static const struct regulator_desc pms405_pldo50 = {
654*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
655*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
656*4882a593Smuzhiyun 	},
657*4882a593Smuzhiyun 	.n_linear_ranges = 1,
658*4882a593Smuzhiyun 	.n_voltages = 129,
659*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
660*4882a593Smuzhiyun };
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun static const struct regulator_desc pms405_pldo150 = {
663*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
664*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
665*4882a593Smuzhiyun 	},
666*4882a593Smuzhiyun 	.n_linear_ranges = 1,
667*4882a593Smuzhiyun 	.n_voltages = 129,
668*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
669*4882a593Smuzhiyun };
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun static const struct regulator_desc pms405_pldo600 = {
672*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
673*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000),
674*4882a593Smuzhiyun 	},
675*4882a593Smuzhiyun 	.n_linear_ranges = 1,
676*4882a593Smuzhiyun 	.n_voltages = 99,
677*4882a593Smuzhiyun 	.ops = &rpm_smps_ldo_ops,
678*4882a593Smuzhiyun };
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun static const struct regulator_desc mp5496_smpa2 = {
681*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
682*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(725000, 0, 27, 12500),
683*4882a593Smuzhiyun 	},
684*4882a593Smuzhiyun 	.n_linear_ranges = 1,
685*4882a593Smuzhiyun 	.n_voltages = 28,
686*4882a593Smuzhiyun 	.ops = &rpm_mp5496_ops,
687*4882a593Smuzhiyun };
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun static const struct regulator_desc mp5496_ldoa2 = {
690*4882a593Smuzhiyun 	.linear_ranges = (struct linear_range[]) {
691*4882a593Smuzhiyun 		REGULATOR_LINEAR_RANGE(1800000, 0, 60, 25000),
692*4882a593Smuzhiyun 	},
693*4882a593Smuzhiyun 	.n_linear_ranges = 1,
694*4882a593Smuzhiyun 	.n_voltages = 61,
695*4882a593Smuzhiyun 	.ops = &rpm_mp5496_ops,
696*4882a593Smuzhiyun };
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun struct rpm_regulator_data {
699*4882a593Smuzhiyun 	const char *name;
700*4882a593Smuzhiyun 	u32 type;
701*4882a593Smuzhiyun 	u32 id;
702*4882a593Smuzhiyun 	const struct regulator_desc *desc;
703*4882a593Smuzhiyun 	const char *supply;
704*4882a593Smuzhiyun };
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
707*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
708*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
709*4882a593Smuzhiyun 	{}
710*4882a593Smuzhiyun };
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
713*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
714*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
715*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
716*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
717*4882a593Smuzhiyun 	{ "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
718*4882a593Smuzhiyun 	{ "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
719*4882a593Smuzhiyun 	{ "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
720*4882a593Smuzhiyun 	{ "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
721*4882a593Smuzhiyun 	{}
722*4882a593Smuzhiyun };
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
725*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
726*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
727*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
728*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
729*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
730*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
731*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
732*4882a593Smuzhiyun 	{ "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
733*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
734*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
735*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
736*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
737*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
738*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
739*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
740*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
741*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
742*4882a593Smuzhiyun 	{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
743*4882a593Smuzhiyun 	{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
744*4882a593Smuzhiyun 	{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
745*4882a593Smuzhiyun 	{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
746*4882a593Smuzhiyun 	{ "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
747*4882a593Smuzhiyun 	{}
748*4882a593Smuzhiyun };
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
751*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
752*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
753*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
754*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
757*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
758*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
759*4882a593Smuzhiyun 	{ "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
760*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
761*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
762*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
763*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
764*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
765*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
766*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
767*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
768*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
769*4882a593Smuzhiyun 	{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
770*4882a593Smuzhiyun 	{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
771*4882a593Smuzhiyun 	{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
772*4882a593Smuzhiyun 	{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
773*4882a593Smuzhiyun 	{ "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
774*4882a593Smuzhiyun 	{ "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
775*4882a593Smuzhiyun 	{ "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
776*4882a593Smuzhiyun 	{ "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
777*4882a593Smuzhiyun 	{ "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
778*4882a593Smuzhiyun 	{ "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
779*4882a593Smuzhiyun 	{ "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun 	{ "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
782*4882a593Smuzhiyun 	{ "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
783*4882a593Smuzhiyun 	{ "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun 	{ "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
786*4882a593Smuzhiyun 	{ "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	{}
789*4882a593Smuzhiyun };
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
792*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
793*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
794*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
795*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
796*4882a593Smuzhiyun 	{ "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
797*4882a593Smuzhiyun 	{ "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
798*4882a593Smuzhiyun 	{ "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
799*4882a593Smuzhiyun 	{ "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
800*4882a593Smuzhiyun 	{ "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
801*4882a593Smuzhiyun 	{ "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
802*4882a593Smuzhiyun 	{ "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
803*4882a593Smuzhiyun 	{ "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
806*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
807*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
808*4882a593Smuzhiyun 	{ "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
809*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
810*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
811*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
812*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
813*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
814*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
815*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
816*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
817*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
818*4882a593Smuzhiyun 	{ "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
819*4882a593Smuzhiyun 	{ "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
820*4882a593Smuzhiyun 	{ "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
821*4882a593Smuzhiyun 	{ "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
822*4882a593Smuzhiyun 	{ "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
823*4882a593Smuzhiyun 	{ "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
824*4882a593Smuzhiyun 	{ "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
825*4882a593Smuzhiyun 	{ "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
826*4882a593Smuzhiyun 	{ "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
827*4882a593Smuzhiyun 	{ "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
828*4882a593Smuzhiyun 	{ "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
829*4882a593Smuzhiyun 	{ "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
830*4882a593Smuzhiyun 	{ "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
831*4882a593Smuzhiyun 	{ "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	{ "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
834*4882a593Smuzhiyun 	{ "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
835*4882a593Smuzhiyun 	{ "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
836*4882a593Smuzhiyun 	{ "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
837*4882a593Smuzhiyun 	{ "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	{}
840*4882a593Smuzhiyun };
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8950_regulators[] = {
843*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPA, 1, &pm8950_hfsmps, "vdd_s1" },
844*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &pm8950_hfsmps, "vdd_s2" },
845*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPA, 3, &pm8950_hfsmps, "vdd_s3" },
846*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_SMPA, 4, &pm8950_hfsmps, "vdd_s4" },
847*4882a593Smuzhiyun 	/* S5 is managed via SPMI. */
848*4882a593Smuzhiyun 	{ "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_hfsmps, "vdd_s6" },
849*4882a593Smuzhiyun 
850*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOA, 1, &pm8950_ult_nldo, "vdd_l1_l19" },
851*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &pm8950_ult_nldo, "vdd_l2_l23" },
852*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOA, 3, &pm8950_ult_nldo, "vdd_l3" },
853*4882a593Smuzhiyun 	/* L4 seems not to exist. */
854*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
855*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
856*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
857*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
858*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
859*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_nldo, "vdd_l9_l10_l13_l14_l15_l18"},
860*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
861*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
862*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
863*4882a593Smuzhiyun 	{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
864*4882a593Smuzhiyun 	{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
865*4882a593Smuzhiyun 	{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l5_l6_l7_l16" },
866*4882a593Smuzhiyun 	{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
867*4882a593Smuzhiyun 	/* L18 seems not to exist. */
868*4882a593Smuzhiyun 	{ "l19", QCOM_SMD_RPM_LDOA, 19, &pm8950_pldo, "vdd_l1_l19" },
869*4882a593Smuzhiyun 	/* L20 & L21 seem not to exist. */
870*4882a593Smuzhiyun 	{ "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_pldo, "vdd_l8_l11_l12_l17_l22" },
871*4882a593Smuzhiyun 	{ "l23", QCOM_SMD_RPM_LDOA, 23, &pm8950_pldo, "vdd_l2_l23" },
872*4882a593Smuzhiyun 	{}
873*4882a593Smuzhiyun };
874*4882a593Smuzhiyun 
875*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8953_regulators[] = {
876*4882a593Smuzhiyun 	{  "s1", QCOM_SMD_RPM_SMPA,  1, &pm8998_hfsmps, "vdd_s1" },
877*4882a593Smuzhiyun 	{  "s2", QCOM_SMD_RPM_SMPA,  2, &pm8998_hfsmps, "vdd_s2" },
878*4882a593Smuzhiyun 	{  "s3", QCOM_SMD_RPM_SMPA,  3, &pm8998_hfsmps, "vdd_s3" },
879*4882a593Smuzhiyun 	{  "s4", QCOM_SMD_RPM_SMPA,  4, &pm8998_hfsmps, "vdd_s4" },
880*4882a593Smuzhiyun 	{  "s5", QCOM_SMD_RPM_SMPA,  5, &pm8950_ftsmps2p5, "vdd_s5" },
881*4882a593Smuzhiyun 	{  "s6", QCOM_SMD_RPM_SMPA,  6, &pm8950_ftsmps2p5, "vdd_s6" },
882*4882a593Smuzhiyun 	{  "s7", QCOM_SMD_RPM_SMPA,  7, &pm8998_hfsmps, "vdd_s7" },
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	{  "l1", QCOM_SMD_RPM_LDOA,  1, &pm8953_ult_nldo, "vdd_l1" },
885*4882a593Smuzhiyun 	{  "l2", QCOM_SMD_RPM_LDOA,  2, &pm8953_ult_nldo, "vdd_l2_l3" },
886*4882a593Smuzhiyun 	{  "l3", QCOM_SMD_RPM_LDOA,  3, &pm8953_ult_nldo, "vdd_l2_l3" },
887*4882a593Smuzhiyun 	{  "l4", QCOM_SMD_RPM_LDOA,  4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
888*4882a593Smuzhiyun 	{  "l5", QCOM_SMD_RPM_LDOA,  5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
889*4882a593Smuzhiyun 	{  "l6", QCOM_SMD_RPM_LDOA,  6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
890*4882a593Smuzhiyun 	{  "l7", QCOM_SMD_RPM_LDOA,  7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
891*4882a593Smuzhiyun 	{  "l8", QCOM_SMD_RPM_LDOA,  8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
892*4882a593Smuzhiyun 	{  "l9", QCOM_SMD_RPM_LDOA,  9, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
893*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
894*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
895*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
896*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
897*4882a593Smuzhiyun 	{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
898*4882a593Smuzhiyun 	{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
899*4882a593Smuzhiyun 	{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
900*4882a593Smuzhiyun 	{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
901*4882a593Smuzhiyun 	{ "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
902*4882a593Smuzhiyun 	{ "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l4_l5_l6_l7_l16_l19" },
903*4882a593Smuzhiyun 	{ "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo,    "vdd_l20" },
904*4882a593Smuzhiyun 	{ "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo,    "vdd_l21" },
905*4882a593Smuzhiyun 	{ "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
906*4882a593Smuzhiyun 	{ "l23", QCOM_SMD_RPM_LDOA, 23, &pm8953_ult_nldo, "vdd_l23" },
907*4882a593Smuzhiyun 	{}
908*4882a593Smuzhiyun };
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8994_regulators[] = {
911*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" },
912*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" },
913*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
914*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
915*4882a593Smuzhiyun 	{ "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" },
916*4882a593Smuzhiyun 	{ "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" },
917*4882a593Smuzhiyun 	{ "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" },
918*4882a593Smuzhiyun 	{ "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" },
919*4882a593Smuzhiyun 	{ "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" },
920*4882a593Smuzhiyun 	{ "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" },
921*4882a593Smuzhiyun 	{ "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" },
922*4882a593Smuzhiyun 	{ "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" },
923*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" },
924*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" },
925*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" },
926*4882a593Smuzhiyun 	{ "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" },
927*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" },
928*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" },
929*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" },
930*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" },
931*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
932*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
933*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" },
934*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" },
935*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
936*4882a593Smuzhiyun 	{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" },
937*4882a593Smuzhiyun 	{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" },
938*4882a593Smuzhiyun 	{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" },
939*4882a593Smuzhiyun 	{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" },
940*4882a593Smuzhiyun 	{ "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
941*4882a593Smuzhiyun 	{ "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
942*4882a593Smuzhiyun 	{ "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" },
943*4882a593Smuzhiyun 	{ "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" },
944*4882a593Smuzhiyun 	{ "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
945*4882a593Smuzhiyun 	{ "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
946*4882a593Smuzhiyun 	{ "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
947*4882a593Smuzhiyun 	{ "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" },
948*4882a593Smuzhiyun 	{ "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" },
949*4882a593Smuzhiyun 	{ "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" },
950*4882a593Smuzhiyun 	{ "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" },
951*4882a593Smuzhiyun 	{ "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" },
952*4882a593Smuzhiyun 	{ "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" },
953*4882a593Smuzhiyun 	{ "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" },
954*4882a593Smuzhiyun 	{ "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" },
955*4882a593Smuzhiyun 	{ "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" },
956*4882a593Smuzhiyun 	{ "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" },
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun 	{}
959*4882a593Smuzhiyun };
960*4882a593Smuzhiyun 
961*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pmi8994_regulators[] = {
962*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" },
963*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" },
964*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" },
965*4882a593Smuzhiyun 	{ "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" },
966*4882a593Smuzhiyun 	{}
967*4882a593Smuzhiyun };
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8998_regulators[] = {
970*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" },
971*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" },
972*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
973*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
974*4882a593Smuzhiyun 	{ "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
975*4882a593Smuzhiyun 	{ "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" },
976*4882a593Smuzhiyun 	{ "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" },
977*4882a593Smuzhiyun 	{ "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" },
978*4882a593Smuzhiyun 	{ "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" },
979*4882a593Smuzhiyun 	{ "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" },
980*4882a593Smuzhiyun 	{ "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" },
981*4882a593Smuzhiyun 	{ "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" },
982*4882a593Smuzhiyun 	{ "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" },
983*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" },
984*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" },
985*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" },
986*4882a593Smuzhiyun 	{ "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" },
987*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" },
988*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" },
989*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
990*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" },
991*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" },
992*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" },
993*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" },
994*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
995*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" },
996*4882a593Smuzhiyun 	{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
997*4882a593Smuzhiyun 	{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
998*4882a593Smuzhiyun 	{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" },
999*4882a593Smuzhiyun 	{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" },
1000*4882a593Smuzhiyun 	{ "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" },
1001*4882a593Smuzhiyun 	{ "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" },
1002*4882a593Smuzhiyun 	{ "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" },
1003*4882a593Smuzhiyun 	{ "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" },
1004*4882a593Smuzhiyun 	{ "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" },
1005*4882a593Smuzhiyun 	{ "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" },
1006*4882a593Smuzhiyun 	{ "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" },
1007*4882a593Smuzhiyun 	{ "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" },
1008*4882a593Smuzhiyun 	{ "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" },
1009*4882a593Smuzhiyun 	{ "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" },
1010*4882a593Smuzhiyun 	{ "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" },
1011*4882a593Smuzhiyun 	{ "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" },
1012*4882a593Smuzhiyun 	{ "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" },
1013*4882a593Smuzhiyun 	{}
1014*4882a593Smuzhiyun };
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pmi8998_regulators[] = {
1017*4882a593Smuzhiyun 	{ "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" },
1018*4882a593Smuzhiyun 	{}
1019*4882a593Smuzhiyun };
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm660_regulators[] = {
1022*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" },
1023*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" },
1024*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" },
1025*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" },
1026*4882a593Smuzhiyun 	{ "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" },
1027*4882a593Smuzhiyun 	{ "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" },
1028*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" },
1029*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" },
1030*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" },
1031*4882a593Smuzhiyun 	/* l4 is unaccessible on PM660 */
1032*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" },
1033*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" },
1034*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" },
1035*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1036*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1037*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1038*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1039*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1040*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1041*4882a593Smuzhiyun 	{ "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
1042*4882a593Smuzhiyun 	{ "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1043*4882a593Smuzhiyun 	{ "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1044*4882a593Smuzhiyun 	{ "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1045*4882a593Smuzhiyun 	{ "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1046*4882a593Smuzhiyun 	{ "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
1047*4882a593Smuzhiyun 	{ }
1048*4882a593Smuzhiyun };
1049*4882a593Smuzhiyun 
1050*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm660l_regulators[] = {
1051*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" },
1052*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" },
1053*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" },
1054*4882a593Smuzhiyun 	{ "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" },
1055*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" },
1056*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" },
1057*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
1058*4882a593Smuzhiyun 	{ "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" },
1059*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
1060*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" },
1061*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
1062*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
1063*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
1064*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
1065*4882a593Smuzhiyun 	{ "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", },
1066*4882a593Smuzhiyun 	{ }
1067*4882a593Smuzhiyun };
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pms405_regulators[] = {
1070*4882a593Smuzhiyun 	{ "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" },
1071*4882a593Smuzhiyun 	{ "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" },
1072*4882a593Smuzhiyun 	{ "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" },
1073*4882a593Smuzhiyun 	{ "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" },
1074*4882a593Smuzhiyun 	{ "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" },
1075*4882a593Smuzhiyun 	{ "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" },
1076*4882a593Smuzhiyun 	{ "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" },
1077*4882a593Smuzhiyun 	{ "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" },
1078*4882a593Smuzhiyun 	{ "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" },
1079*4882a593Smuzhiyun 	{ "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" },
1080*4882a593Smuzhiyun 	{ "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" },
1081*4882a593Smuzhiyun 	{ "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" },
1082*4882a593Smuzhiyun 	{ "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" },
1083*4882a593Smuzhiyun 	{ "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" },
1084*4882a593Smuzhiyun 	{ "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" },
1085*4882a593Smuzhiyun 	{ "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1086*4882a593Smuzhiyun 	{ "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1087*4882a593Smuzhiyun 	{ "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1088*4882a593Smuzhiyun 	{}
1089*4882a593Smuzhiyun };
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun static const struct of_device_id rpm_of_match[] = {
1092*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-mp5496-regulators", .data = &rpm_mp5496_regulators },
1093*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
1094*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
1095*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
1096*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators },
1097*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8953-regulators", .data = &rpm_pm8953_regulators },
1098*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators },
1099*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators },
1100*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators },
1101*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators },
1102*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
1103*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pmi8994-regulators", .data = &rpm_pmi8994_regulators },
1104*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators },
1105*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators },
1106*4882a593Smuzhiyun 	{}
1107*4882a593Smuzhiyun };
1108*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rpm_of_match);
1109*4882a593Smuzhiyun 
1110*4882a593Smuzhiyun /**
1111*4882a593Smuzhiyun  * rpm_regulator_init_vreg() - initialize all attributes of a qcom_smd-regulator
1112*4882a593Smuzhiyun  * @vreg:		Pointer to the individual qcom_smd-regulator resource
1113*4882a593Smuzhiyun  * @dev:		Pointer to the top level qcom_smd-regulator PMIC device
1114*4882a593Smuzhiyun  * @node:		Pointer to the individual qcom_smd-regulator resource
1115*4882a593Smuzhiyun  *			device node
1116*4882a593Smuzhiyun  * @rpm:		Pointer to the rpm bus node
1117*4882a593Smuzhiyun  * @pmic_rpm_data:	Pointer to a null-terminated array of qcom_smd-regulator
1118*4882a593Smuzhiyun  *			resources defined for the top level PMIC device
1119*4882a593Smuzhiyun  *
1120*4882a593Smuzhiyun  * Return: 0 on success, errno on failure
1121*4882a593Smuzhiyun  */
rpm_regulator_init_vreg(struct qcom_rpm_reg * vreg,struct device * dev,struct device_node * node,struct qcom_smd_rpm * rpm,const struct rpm_regulator_data * pmic_rpm_data)1122*4882a593Smuzhiyun static int rpm_regulator_init_vreg(struct qcom_rpm_reg *vreg, struct device *dev,
1123*4882a593Smuzhiyun 				   struct device_node *node, struct qcom_smd_rpm *rpm,
1124*4882a593Smuzhiyun 				   const struct rpm_regulator_data *pmic_rpm_data)
1125*4882a593Smuzhiyun {
1126*4882a593Smuzhiyun 	struct regulator_config config = {};
1127*4882a593Smuzhiyun 	const struct rpm_regulator_data *rpm_data;
1128*4882a593Smuzhiyun 	struct regulator_dev *rdev;
1129*4882a593Smuzhiyun 	int ret;
1130*4882a593Smuzhiyun 
1131*4882a593Smuzhiyun 	for (rpm_data = pmic_rpm_data; rpm_data->name; rpm_data++)
1132*4882a593Smuzhiyun 		if (of_node_name_eq(node, rpm_data->name))
1133*4882a593Smuzhiyun 			break;
1134*4882a593Smuzhiyun 
1135*4882a593Smuzhiyun 	if (!rpm_data->name) {
1136*4882a593Smuzhiyun 		dev_err(dev, "Unknown regulator %pOFn\n", node);
1137*4882a593Smuzhiyun 		return -EINVAL;
1138*4882a593Smuzhiyun 	}
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 	vreg->dev	= dev;
1141*4882a593Smuzhiyun 	vreg->rpm	= rpm;
1142*4882a593Smuzhiyun 	vreg->type	= rpm_data->type;
1143*4882a593Smuzhiyun 	vreg->id	= rpm_data->id;
1144*4882a593Smuzhiyun 
1145*4882a593Smuzhiyun 	memcpy(&vreg->desc, rpm_data->desc, sizeof(vreg->desc));
1146*4882a593Smuzhiyun 	vreg->desc.name = rpm_data->name;
1147*4882a593Smuzhiyun 	vreg->desc.supply_name = rpm_data->supply;
1148*4882a593Smuzhiyun 	vreg->desc.owner = THIS_MODULE;
1149*4882a593Smuzhiyun 	vreg->desc.type = REGULATOR_VOLTAGE;
1150*4882a593Smuzhiyun 	vreg->desc.of_match = rpm_data->name;
1151*4882a593Smuzhiyun 
1152*4882a593Smuzhiyun 	config.dev		= dev;
1153*4882a593Smuzhiyun 	config.of_node		= node;
1154*4882a593Smuzhiyun 	config.driver_data	= vreg;
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 	rdev = devm_regulator_register(dev, &vreg->desc, &config);
1157*4882a593Smuzhiyun 	if (IS_ERR(rdev)) {
1158*4882a593Smuzhiyun 		ret = PTR_ERR(rdev);
1159*4882a593Smuzhiyun 		dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", node, ret);
1160*4882a593Smuzhiyun 		return ret;
1161*4882a593Smuzhiyun 	}
1162*4882a593Smuzhiyun 
1163*4882a593Smuzhiyun 	return 0;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun 
rpm_reg_probe(struct platform_device * pdev)1166*4882a593Smuzhiyun static int rpm_reg_probe(struct platform_device *pdev)
1167*4882a593Smuzhiyun {
1168*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
1169*4882a593Smuzhiyun 	const struct rpm_regulator_data *vreg_data;
1170*4882a593Smuzhiyun 	struct device_node *node;
1171*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg;
1172*4882a593Smuzhiyun 	struct qcom_smd_rpm *rpm;
1173*4882a593Smuzhiyun 	int ret;
1174*4882a593Smuzhiyun 
1175*4882a593Smuzhiyun 	rpm = dev_get_drvdata(pdev->dev.parent);
1176*4882a593Smuzhiyun 	if (!rpm) {
1177*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Unable to retrieve handle to rpm\n");
1178*4882a593Smuzhiyun 		return -ENODEV;
1179*4882a593Smuzhiyun 	}
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 	vreg_data = of_device_get_match_data(dev);
1182*4882a593Smuzhiyun 	if (!vreg_data)
1183*4882a593Smuzhiyun 		return -ENODEV;
1184*4882a593Smuzhiyun 
1185*4882a593Smuzhiyun 	for_each_available_child_of_node(dev->of_node, node) {
1186*4882a593Smuzhiyun 		vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
1187*4882a593Smuzhiyun 		if (!vreg) {
1188*4882a593Smuzhiyun 			of_node_put(node);
1189*4882a593Smuzhiyun 			return -ENOMEM;
1190*4882a593Smuzhiyun 		}
1191*4882a593Smuzhiyun 
1192*4882a593Smuzhiyun 		ret = rpm_regulator_init_vreg(vreg, dev, node, rpm, vreg_data);
1193*4882a593Smuzhiyun 
1194*4882a593Smuzhiyun 		if (ret < 0) {
1195*4882a593Smuzhiyun 			of_node_put(node);
1196*4882a593Smuzhiyun 			return ret;
1197*4882a593Smuzhiyun 		}
1198*4882a593Smuzhiyun 	}
1199*4882a593Smuzhiyun 
1200*4882a593Smuzhiyun 	return 0;
1201*4882a593Smuzhiyun }
1202*4882a593Smuzhiyun 
1203*4882a593Smuzhiyun static struct platform_driver rpm_reg_driver = {
1204*4882a593Smuzhiyun 	.probe = rpm_reg_probe,
1205*4882a593Smuzhiyun 	.driver = {
1206*4882a593Smuzhiyun 		.name  = "qcom_rpm_smd_regulator",
1207*4882a593Smuzhiyun 		.of_match_table = rpm_of_match,
1208*4882a593Smuzhiyun 	},
1209*4882a593Smuzhiyun };
1210*4882a593Smuzhiyun 
rpm_reg_init(void)1211*4882a593Smuzhiyun static int __init rpm_reg_init(void)
1212*4882a593Smuzhiyun {
1213*4882a593Smuzhiyun 	return platform_driver_register(&rpm_reg_driver);
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun subsys_initcall(rpm_reg_init);
1216*4882a593Smuzhiyun 
rpm_reg_exit(void)1217*4882a593Smuzhiyun static void __exit rpm_reg_exit(void)
1218*4882a593Smuzhiyun {
1219*4882a593Smuzhiyun 	platform_driver_unregister(&rpm_reg_driver);
1220*4882a593Smuzhiyun }
1221*4882a593Smuzhiyun module_exit(rpm_reg_exit)
1222*4882a593Smuzhiyun 
1223*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
1224*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1225