xref: /OK3568_Linux_fs/kernel/drivers/regulator/qcom_rpm-regulator.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2014, Sony Mobile Communications AB.
4*4882a593Smuzhiyun  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/of_device.h>
11*4882a593Smuzhiyun #include <linux/regulator/driver.h>
12*4882a593Smuzhiyun #include <linux/regulator/machine.h>
13*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
14*4882a593Smuzhiyun #include <linux/mfd/qcom_rpm.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <dt-bindings/mfd/qcom-rpm.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define MAX_REQUEST_LEN 2
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun struct request_member {
21*4882a593Smuzhiyun 	int		word;
22*4882a593Smuzhiyun 	unsigned int	mask;
23*4882a593Smuzhiyun 	int		shift;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun struct rpm_reg_parts {
27*4882a593Smuzhiyun 	struct request_member mV;		/* used if voltage is in mV */
28*4882a593Smuzhiyun 	struct request_member uV;		/* used if voltage is in uV */
29*4882a593Smuzhiyun 	struct request_member ip;		/* peak current in mA */
30*4882a593Smuzhiyun 	struct request_member pd;		/* pull down enable */
31*4882a593Smuzhiyun 	struct request_member ia;		/* average current in mA */
32*4882a593Smuzhiyun 	struct request_member fm;		/* force mode */
33*4882a593Smuzhiyun 	struct request_member pm;		/* power mode */
34*4882a593Smuzhiyun 	struct request_member pc;		/* pin control */
35*4882a593Smuzhiyun 	struct request_member pf;		/* pin function */
36*4882a593Smuzhiyun 	struct request_member enable_state;	/* NCP and switch */
37*4882a593Smuzhiyun 	struct request_member comp_mode;	/* NCP */
38*4882a593Smuzhiyun 	struct request_member freq;		/* frequency: NCP and SMPS */
39*4882a593Smuzhiyun 	struct request_member freq_clk_src;	/* clock source: SMPS */
40*4882a593Smuzhiyun 	struct request_member hpm;		/* switch: control OCP and SS */
41*4882a593Smuzhiyun 	int request_len;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define FORCE_MODE_IS_2_BITS(reg) \
45*4882a593Smuzhiyun 	(((reg)->parts->fm.mask >> (reg)->parts->fm.shift) == 3)
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun struct qcom_rpm_reg {
48*4882a593Smuzhiyun 	struct qcom_rpm *rpm;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	struct mutex lock;
51*4882a593Smuzhiyun 	struct device *dev;
52*4882a593Smuzhiyun 	struct regulator_desc desc;
53*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	int resource;
56*4882a593Smuzhiyun 	u32 val[MAX_REQUEST_LEN];
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	int uV;
59*4882a593Smuzhiyun 	int is_enabled;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	bool supports_force_mode_auto;
62*4882a593Smuzhiyun 	bool supports_force_mode_bypass;
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static const struct rpm_reg_parts rpm8660_ldo_parts = {
66*4882a593Smuzhiyun 	.request_len    = 2,
67*4882a593Smuzhiyun 	.mV             = { 0, 0x00000FFF,  0 },
68*4882a593Smuzhiyun 	.ip             = { 0, 0x00FFF000, 12 },
69*4882a593Smuzhiyun 	.fm             = { 0, 0x03000000, 24 },
70*4882a593Smuzhiyun 	.pc             = { 0, 0x3C000000, 26 },
71*4882a593Smuzhiyun 	.pf             = { 0, 0xC0000000, 30 },
72*4882a593Smuzhiyun 	.pd             = { 1, 0x00000001,  0 },
73*4882a593Smuzhiyun 	.ia             = { 1, 0x00001FFE,  1 },
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static const struct rpm_reg_parts rpm8660_smps_parts = {
77*4882a593Smuzhiyun 	.request_len    = 2,
78*4882a593Smuzhiyun 	.mV             = { 0, 0x00000FFF,  0 },
79*4882a593Smuzhiyun 	.ip             = { 0, 0x00FFF000, 12 },
80*4882a593Smuzhiyun 	.fm             = { 0, 0x03000000, 24 },
81*4882a593Smuzhiyun 	.pc             = { 0, 0x3C000000, 26 },
82*4882a593Smuzhiyun 	.pf             = { 0, 0xC0000000, 30 },
83*4882a593Smuzhiyun 	.pd             = { 1, 0x00000001,  0 },
84*4882a593Smuzhiyun 	.ia             = { 1, 0x00001FFE,  1 },
85*4882a593Smuzhiyun 	.freq           = { 1, 0x001FE000, 13 },
86*4882a593Smuzhiyun 	.freq_clk_src   = { 1, 0x00600000, 21 },
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun static const struct rpm_reg_parts rpm8660_switch_parts = {
90*4882a593Smuzhiyun 	.request_len    = 1,
91*4882a593Smuzhiyun 	.enable_state   = { 0, 0x00000001,  0 },
92*4882a593Smuzhiyun 	.pd             = { 0, 0x00000002,  1 },
93*4882a593Smuzhiyun 	.pc             = { 0, 0x0000003C,  2 },
94*4882a593Smuzhiyun 	.pf             = { 0, 0x000000C0,  6 },
95*4882a593Smuzhiyun 	.hpm            = { 0, 0x00000300,  8 },
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun static const struct rpm_reg_parts rpm8660_ncp_parts = {
99*4882a593Smuzhiyun 	.request_len    = 1,
100*4882a593Smuzhiyun 	.mV             = { 0, 0x00000FFF,  0 },
101*4882a593Smuzhiyun 	.enable_state   = { 0, 0x00001000, 12 },
102*4882a593Smuzhiyun 	.comp_mode      = { 0, 0x00002000, 13 },
103*4882a593Smuzhiyun 	.freq           = { 0, 0x003FC000, 14 },
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun static const struct rpm_reg_parts rpm8960_ldo_parts = {
107*4882a593Smuzhiyun 	.request_len    = 2,
108*4882a593Smuzhiyun 	.uV             = { 0, 0x007FFFFF,  0 },
109*4882a593Smuzhiyun 	.pd             = { 0, 0x00800000, 23 },
110*4882a593Smuzhiyun 	.pc             = { 0, 0x0F000000, 24 },
111*4882a593Smuzhiyun 	.pf             = { 0, 0xF0000000, 28 },
112*4882a593Smuzhiyun 	.ip             = { 1, 0x000003FF,  0 },
113*4882a593Smuzhiyun 	.ia             = { 1, 0x000FFC00, 10 },
114*4882a593Smuzhiyun 	.fm             = { 1, 0x00700000, 20 },
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun static const struct rpm_reg_parts rpm8960_smps_parts = {
118*4882a593Smuzhiyun 	.request_len    = 2,
119*4882a593Smuzhiyun 	.uV             = { 0, 0x007FFFFF,  0 },
120*4882a593Smuzhiyun 	.pd             = { 0, 0x00800000, 23 },
121*4882a593Smuzhiyun 	.pc             = { 0, 0x0F000000, 24 },
122*4882a593Smuzhiyun 	.pf             = { 0, 0xF0000000, 28 },
123*4882a593Smuzhiyun 	.ip             = { 1, 0x000003FF,  0 },
124*4882a593Smuzhiyun 	.ia             = { 1, 0x000FFC00, 10 },
125*4882a593Smuzhiyun 	.fm             = { 1, 0x00700000, 20 },
126*4882a593Smuzhiyun 	.pm             = { 1, 0x00800000, 23 },
127*4882a593Smuzhiyun 	.freq           = { 1, 0x1F000000, 24 },
128*4882a593Smuzhiyun 	.freq_clk_src   = { 1, 0x60000000, 29 },
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun static const struct rpm_reg_parts rpm8960_switch_parts = {
132*4882a593Smuzhiyun 	.request_len    = 1,
133*4882a593Smuzhiyun 	.enable_state   = { 0, 0x00000001,  0 },
134*4882a593Smuzhiyun 	.pd             = { 0, 0x00000002,  1 },
135*4882a593Smuzhiyun 	.pc             = { 0, 0x0000003C,  2 },
136*4882a593Smuzhiyun 	.pf             = { 0, 0x000003C0,  6 },
137*4882a593Smuzhiyun 	.hpm            = { 0, 0x00000C00, 10 },
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun static const struct rpm_reg_parts rpm8960_ncp_parts = {
141*4882a593Smuzhiyun 	.request_len    = 1,
142*4882a593Smuzhiyun 	.uV             = { 0, 0x007FFFFF,  0 },
143*4882a593Smuzhiyun 	.enable_state   = { 0, 0x00800000, 23 },
144*4882a593Smuzhiyun 	.comp_mode      = { 0, 0x01000000, 24 },
145*4882a593Smuzhiyun 	.freq           = { 0, 0x3E000000, 25 },
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /*
149*4882a593Smuzhiyun  * Physically available PMIC regulator voltage ranges
150*4882a593Smuzhiyun  */
151*4882a593Smuzhiyun static const struct linear_range pldo_ranges[] = {
152*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 750000,   0,  59, 12500),
153*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(1500000,  60, 123, 25000),
154*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(3100000, 124, 160, 50000),
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static const struct linear_range nldo_ranges[] = {
158*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 750000,   0,  63, 12500),
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun static const struct linear_range nldo1200_ranges[] = {
162*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 375000,   0,  59,  6250),
163*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 750000,  60, 123, 12500),
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun static const struct linear_range smps_ranges[] = {
167*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 375000,   0,  29, 12500),
168*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 750000,  30,  89, 12500),
169*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(1500000,  90, 153, 25000),
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun static const struct linear_range ftsmps_ranges[] = {
173*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 350000,   0,   6, 50000),
174*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 700000,   7,  63, 12500),
175*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(1500000,  64, 100, 50000),
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun static const struct linear_range smb208_ranges[] = {
179*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 375000,   0,  29, 12500),
180*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE( 750000,  30,  89, 12500),
181*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(1500000,  90, 153, 25000),
182*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(3100000, 154, 234, 25000),
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun static const struct linear_range ncp_ranges[] = {
186*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(1500000,   0,  31, 50000),
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
rpm_reg_write(struct qcom_rpm_reg * vreg,const struct request_member * req,const int value)189*4882a593Smuzhiyun static int rpm_reg_write(struct qcom_rpm_reg *vreg,
190*4882a593Smuzhiyun 			 const struct request_member *req,
191*4882a593Smuzhiyun 			 const int value)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	if (WARN_ON((value << req->shift) & ~req->mask))
194*4882a593Smuzhiyun 		return -EINVAL;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	vreg->val[req->word] &= ~req->mask;
197*4882a593Smuzhiyun 	vreg->val[req->word] |= value << req->shift;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	return qcom_rpm_write(vreg->rpm,
200*4882a593Smuzhiyun 			      QCOM_RPM_ACTIVE_STATE,
201*4882a593Smuzhiyun 			      vreg->resource,
202*4882a593Smuzhiyun 			      vreg->val,
203*4882a593Smuzhiyun 			      vreg->parts->request_len);
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
rpm_reg_set_mV_sel(struct regulator_dev * rdev,unsigned selector)206*4882a593Smuzhiyun static int rpm_reg_set_mV_sel(struct regulator_dev *rdev,
207*4882a593Smuzhiyun 			      unsigned selector)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
210*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
211*4882a593Smuzhiyun 	const struct request_member *req = &parts->mV;
212*4882a593Smuzhiyun 	int ret = 0;
213*4882a593Smuzhiyun 	int uV;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	if (req->mask == 0)
216*4882a593Smuzhiyun 		return -EINVAL;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	uV = regulator_list_voltage_linear_range(rdev, selector);
219*4882a593Smuzhiyun 	if (uV < 0)
220*4882a593Smuzhiyun 		return uV;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
223*4882a593Smuzhiyun 	if (vreg->is_enabled)
224*4882a593Smuzhiyun 		ret = rpm_reg_write(vreg, req, uV / 1000);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	if (!ret)
227*4882a593Smuzhiyun 		vreg->uV = uV;
228*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	return ret;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
rpm_reg_set_uV_sel(struct regulator_dev * rdev,unsigned selector)233*4882a593Smuzhiyun static int rpm_reg_set_uV_sel(struct regulator_dev *rdev,
234*4882a593Smuzhiyun 			      unsigned selector)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
237*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
238*4882a593Smuzhiyun 	const struct request_member *req = &parts->uV;
239*4882a593Smuzhiyun 	int ret = 0;
240*4882a593Smuzhiyun 	int uV;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	if (req->mask == 0)
243*4882a593Smuzhiyun 		return -EINVAL;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	uV = regulator_list_voltage_linear_range(rdev, selector);
246*4882a593Smuzhiyun 	if (uV < 0)
247*4882a593Smuzhiyun 		return uV;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
250*4882a593Smuzhiyun 	if (vreg->is_enabled)
251*4882a593Smuzhiyun 		ret = rpm_reg_write(vreg, req, uV);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	if (!ret)
254*4882a593Smuzhiyun 		vreg->uV = uV;
255*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	return ret;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun 
rpm_reg_get_voltage(struct regulator_dev * rdev)260*4882a593Smuzhiyun static int rpm_reg_get_voltage(struct regulator_dev *rdev)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	return vreg->uV;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
rpm_reg_mV_enable(struct regulator_dev * rdev)267*4882a593Smuzhiyun static int rpm_reg_mV_enable(struct regulator_dev *rdev)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
270*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
271*4882a593Smuzhiyun 	const struct request_member *req = &parts->mV;
272*4882a593Smuzhiyun 	int ret;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	if (req->mask == 0)
275*4882a593Smuzhiyun 		return -EINVAL;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
278*4882a593Smuzhiyun 	ret = rpm_reg_write(vreg, req, vreg->uV / 1000);
279*4882a593Smuzhiyun 	if (!ret)
280*4882a593Smuzhiyun 		vreg->is_enabled = 1;
281*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	return ret;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun 
rpm_reg_uV_enable(struct regulator_dev * rdev)286*4882a593Smuzhiyun static int rpm_reg_uV_enable(struct regulator_dev *rdev)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
289*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
290*4882a593Smuzhiyun 	const struct request_member *req = &parts->uV;
291*4882a593Smuzhiyun 	int ret;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	if (req->mask == 0)
294*4882a593Smuzhiyun 		return -EINVAL;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
297*4882a593Smuzhiyun 	ret = rpm_reg_write(vreg, req, vreg->uV);
298*4882a593Smuzhiyun 	if (!ret)
299*4882a593Smuzhiyun 		vreg->is_enabled = 1;
300*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	return ret;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun 
rpm_reg_switch_enable(struct regulator_dev * rdev)305*4882a593Smuzhiyun static int rpm_reg_switch_enable(struct regulator_dev *rdev)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
308*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
309*4882a593Smuzhiyun 	const struct request_member *req = &parts->enable_state;
310*4882a593Smuzhiyun 	int ret;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	if (req->mask == 0)
313*4882a593Smuzhiyun 		return -EINVAL;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
316*4882a593Smuzhiyun 	ret = rpm_reg_write(vreg, req, 1);
317*4882a593Smuzhiyun 	if (!ret)
318*4882a593Smuzhiyun 		vreg->is_enabled = 1;
319*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	return ret;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
rpm_reg_mV_disable(struct regulator_dev * rdev)324*4882a593Smuzhiyun static int rpm_reg_mV_disable(struct regulator_dev *rdev)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
327*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
328*4882a593Smuzhiyun 	const struct request_member *req = &parts->mV;
329*4882a593Smuzhiyun 	int ret;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	if (req->mask == 0)
332*4882a593Smuzhiyun 		return -EINVAL;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
335*4882a593Smuzhiyun 	ret = rpm_reg_write(vreg, req, 0);
336*4882a593Smuzhiyun 	if (!ret)
337*4882a593Smuzhiyun 		vreg->is_enabled = 0;
338*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	return ret;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun 
rpm_reg_uV_disable(struct regulator_dev * rdev)343*4882a593Smuzhiyun static int rpm_reg_uV_disable(struct regulator_dev *rdev)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
346*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
347*4882a593Smuzhiyun 	const struct request_member *req = &parts->uV;
348*4882a593Smuzhiyun 	int ret;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	if (req->mask == 0)
351*4882a593Smuzhiyun 		return -EINVAL;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
354*4882a593Smuzhiyun 	ret = rpm_reg_write(vreg, req, 0);
355*4882a593Smuzhiyun 	if (!ret)
356*4882a593Smuzhiyun 		vreg->is_enabled = 0;
357*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	return ret;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun 
rpm_reg_switch_disable(struct regulator_dev * rdev)362*4882a593Smuzhiyun static int rpm_reg_switch_disable(struct regulator_dev *rdev)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
365*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
366*4882a593Smuzhiyun 	const struct request_member *req = &parts->enable_state;
367*4882a593Smuzhiyun 	int ret;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	if (req->mask == 0)
370*4882a593Smuzhiyun 		return -EINVAL;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
373*4882a593Smuzhiyun 	ret = rpm_reg_write(vreg, req, 0);
374*4882a593Smuzhiyun 	if (!ret)
375*4882a593Smuzhiyun 		vreg->is_enabled = 0;
376*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	return ret;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
rpm_reg_is_enabled(struct regulator_dev * rdev)381*4882a593Smuzhiyun static int rpm_reg_is_enabled(struct regulator_dev *rdev)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	return vreg->is_enabled;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun 
rpm_reg_set_load(struct regulator_dev * rdev,int load_uA)388*4882a593Smuzhiyun static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
391*4882a593Smuzhiyun 	const struct rpm_reg_parts *parts = vreg->parts;
392*4882a593Smuzhiyun 	const struct request_member *req = &parts->ia;
393*4882a593Smuzhiyun 	int load_mA = load_uA / 1000;
394*4882a593Smuzhiyun 	int max_mA = req->mask >> req->shift;
395*4882a593Smuzhiyun 	int ret;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	if (req->mask == 0)
398*4882a593Smuzhiyun 		return -EINVAL;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	if (load_mA > max_mA)
401*4882a593Smuzhiyun 		load_mA = max_mA;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	mutex_lock(&vreg->lock);
404*4882a593Smuzhiyun 	ret = rpm_reg_write(vreg, req, load_mA);
405*4882a593Smuzhiyun 	mutex_unlock(&vreg->lock);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	return ret;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun static const struct regulator_ops uV_ops = {
411*4882a593Smuzhiyun 	.list_voltage = regulator_list_voltage_linear_range,
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	.set_voltage_sel = rpm_reg_set_uV_sel,
414*4882a593Smuzhiyun 	.get_voltage = rpm_reg_get_voltage,
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	.enable = rpm_reg_uV_enable,
417*4882a593Smuzhiyun 	.disable = rpm_reg_uV_disable,
418*4882a593Smuzhiyun 	.is_enabled = rpm_reg_is_enabled,
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	.set_load = rpm_reg_set_load,
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun static const struct regulator_ops mV_ops = {
424*4882a593Smuzhiyun 	.list_voltage = regulator_list_voltage_linear_range,
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	.set_voltage_sel = rpm_reg_set_mV_sel,
427*4882a593Smuzhiyun 	.get_voltage = rpm_reg_get_voltage,
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	.enable = rpm_reg_mV_enable,
430*4882a593Smuzhiyun 	.disable = rpm_reg_mV_disable,
431*4882a593Smuzhiyun 	.is_enabled = rpm_reg_is_enabled,
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	.set_load = rpm_reg_set_load,
434*4882a593Smuzhiyun };
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun static const struct regulator_ops switch_ops = {
437*4882a593Smuzhiyun 	.enable = rpm_reg_switch_enable,
438*4882a593Smuzhiyun 	.disable = rpm_reg_switch_disable,
439*4882a593Smuzhiyun 	.is_enabled = rpm_reg_is_enabled,
440*4882a593Smuzhiyun };
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun /*
443*4882a593Smuzhiyun  * PM8018 regulators
444*4882a593Smuzhiyun  */
445*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8018_pldo = {
446*4882a593Smuzhiyun 	.desc.linear_ranges = pldo_ranges,
447*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
448*4882a593Smuzhiyun 	.desc.n_voltages = 161,
449*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
450*4882a593Smuzhiyun 	.parts = &rpm8960_ldo_parts,
451*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
452*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8018_nldo = {
456*4882a593Smuzhiyun 	.desc.linear_ranges = nldo_ranges,
457*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
458*4882a593Smuzhiyun 	.desc.n_voltages = 64,
459*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
460*4882a593Smuzhiyun 	.parts = &rpm8960_ldo_parts,
461*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
462*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
463*4882a593Smuzhiyun };
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8018_smps = {
466*4882a593Smuzhiyun 	.desc.linear_ranges = smps_ranges,
467*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
468*4882a593Smuzhiyun 	.desc.n_voltages = 154,
469*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
470*4882a593Smuzhiyun 	.parts = &rpm8960_smps_parts,
471*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
472*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
473*4882a593Smuzhiyun };
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8018_switch = {
476*4882a593Smuzhiyun 	.desc.ops = &switch_ops,
477*4882a593Smuzhiyun 	.parts = &rpm8960_switch_parts,
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun /*
481*4882a593Smuzhiyun  * PM8058 regulators
482*4882a593Smuzhiyun  */
483*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8058_pldo = {
484*4882a593Smuzhiyun 	.desc.linear_ranges = pldo_ranges,
485*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
486*4882a593Smuzhiyun 	.desc.n_voltages = 161,
487*4882a593Smuzhiyun 	.desc.ops = &mV_ops,
488*4882a593Smuzhiyun 	.parts = &rpm8660_ldo_parts,
489*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
490*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8058_nldo = {
494*4882a593Smuzhiyun 	.desc.linear_ranges = nldo_ranges,
495*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
496*4882a593Smuzhiyun 	.desc.n_voltages = 64,
497*4882a593Smuzhiyun 	.desc.ops = &mV_ops,
498*4882a593Smuzhiyun 	.parts = &rpm8660_ldo_parts,
499*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
500*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
501*4882a593Smuzhiyun };
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8058_smps = {
504*4882a593Smuzhiyun 	.desc.linear_ranges = smps_ranges,
505*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
506*4882a593Smuzhiyun 	.desc.n_voltages = 154,
507*4882a593Smuzhiyun 	.desc.ops = &mV_ops,
508*4882a593Smuzhiyun 	.parts = &rpm8660_smps_parts,
509*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
510*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
511*4882a593Smuzhiyun };
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8058_ncp = {
514*4882a593Smuzhiyun 	.desc.linear_ranges = ncp_ranges,
515*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(ncp_ranges),
516*4882a593Smuzhiyun 	.desc.n_voltages = 32,
517*4882a593Smuzhiyun 	.desc.ops = &mV_ops,
518*4882a593Smuzhiyun 	.parts = &rpm8660_ncp_parts,
519*4882a593Smuzhiyun };
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8058_switch = {
522*4882a593Smuzhiyun 	.desc.ops = &switch_ops,
523*4882a593Smuzhiyun 	.parts = &rpm8660_switch_parts,
524*4882a593Smuzhiyun };
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun /*
527*4882a593Smuzhiyun  * PM8901 regulators
528*4882a593Smuzhiyun  */
529*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8901_pldo = {
530*4882a593Smuzhiyun 	.desc.linear_ranges = pldo_ranges,
531*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
532*4882a593Smuzhiyun 	.desc.n_voltages = 161,
533*4882a593Smuzhiyun 	.desc.ops = &mV_ops,
534*4882a593Smuzhiyun 	.parts = &rpm8660_ldo_parts,
535*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
536*4882a593Smuzhiyun 	.supports_force_mode_bypass = true,
537*4882a593Smuzhiyun };
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8901_nldo = {
540*4882a593Smuzhiyun 	.desc.linear_ranges = nldo_ranges,
541*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
542*4882a593Smuzhiyun 	.desc.n_voltages = 64,
543*4882a593Smuzhiyun 	.desc.ops = &mV_ops,
544*4882a593Smuzhiyun 	.parts = &rpm8660_ldo_parts,
545*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
546*4882a593Smuzhiyun 	.supports_force_mode_bypass = true,
547*4882a593Smuzhiyun };
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8901_ftsmps = {
550*4882a593Smuzhiyun 	.desc.linear_ranges = ftsmps_ranges,
551*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(ftsmps_ranges),
552*4882a593Smuzhiyun 	.desc.n_voltages = 101,
553*4882a593Smuzhiyun 	.desc.ops = &mV_ops,
554*4882a593Smuzhiyun 	.parts = &rpm8660_smps_parts,
555*4882a593Smuzhiyun 	.supports_force_mode_auto = true,
556*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
557*4882a593Smuzhiyun };
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8901_switch = {
560*4882a593Smuzhiyun 	.desc.ops = &switch_ops,
561*4882a593Smuzhiyun 	.parts = &rpm8660_switch_parts,
562*4882a593Smuzhiyun };
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun /*
565*4882a593Smuzhiyun  * PM8921 regulators
566*4882a593Smuzhiyun  */
567*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8921_pldo = {
568*4882a593Smuzhiyun 	.desc.linear_ranges = pldo_ranges,
569*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
570*4882a593Smuzhiyun 	.desc.n_voltages = 161,
571*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
572*4882a593Smuzhiyun 	.parts = &rpm8960_ldo_parts,
573*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
574*4882a593Smuzhiyun 	.supports_force_mode_bypass = true,
575*4882a593Smuzhiyun };
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8921_nldo = {
578*4882a593Smuzhiyun 	.desc.linear_ranges = nldo_ranges,
579*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
580*4882a593Smuzhiyun 	.desc.n_voltages = 64,
581*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
582*4882a593Smuzhiyun 	.parts = &rpm8960_ldo_parts,
583*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
584*4882a593Smuzhiyun 	.supports_force_mode_bypass = true,
585*4882a593Smuzhiyun };
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8921_nldo1200 = {
588*4882a593Smuzhiyun 	.desc.linear_ranges = nldo1200_ranges,
589*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(nldo1200_ranges),
590*4882a593Smuzhiyun 	.desc.n_voltages = 124,
591*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
592*4882a593Smuzhiyun 	.parts = &rpm8960_ldo_parts,
593*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
594*4882a593Smuzhiyun 	.supports_force_mode_bypass = true,
595*4882a593Smuzhiyun };
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8921_smps = {
598*4882a593Smuzhiyun 	.desc.linear_ranges = smps_ranges,
599*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
600*4882a593Smuzhiyun 	.desc.n_voltages = 154,
601*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
602*4882a593Smuzhiyun 	.parts = &rpm8960_smps_parts,
603*4882a593Smuzhiyun 	.supports_force_mode_auto = true,
604*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
605*4882a593Smuzhiyun };
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8921_ncp = {
608*4882a593Smuzhiyun 	.desc.linear_ranges = ncp_ranges,
609*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(ncp_ranges),
610*4882a593Smuzhiyun 	.desc.n_voltages = 32,
611*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
612*4882a593Smuzhiyun 	.parts = &rpm8960_ncp_parts,
613*4882a593Smuzhiyun };
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun static const struct qcom_rpm_reg pm8921_switch = {
616*4882a593Smuzhiyun 	.desc.ops = &switch_ops,
617*4882a593Smuzhiyun 	.parts = &rpm8960_switch_parts,
618*4882a593Smuzhiyun };
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun static const struct qcom_rpm_reg smb208_smps = {
621*4882a593Smuzhiyun 	.desc.linear_ranges = smb208_ranges,
622*4882a593Smuzhiyun 	.desc.n_linear_ranges = ARRAY_SIZE(smb208_ranges),
623*4882a593Smuzhiyun 	.desc.n_voltages = 235,
624*4882a593Smuzhiyun 	.desc.ops = &uV_ops,
625*4882a593Smuzhiyun 	.parts = &rpm8960_smps_parts,
626*4882a593Smuzhiyun 	.supports_force_mode_auto = false,
627*4882a593Smuzhiyun 	.supports_force_mode_bypass = false,
628*4882a593Smuzhiyun };
629*4882a593Smuzhiyun 
rpm_reg_set(struct qcom_rpm_reg * vreg,const struct request_member * req,const int value)630*4882a593Smuzhiyun static int rpm_reg_set(struct qcom_rpm_reg *vreg,
631*4882a593Smuzhiyun 		       const struct request_member *req,
632*4882a593Smuzhiyun 		       const int value)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun 	if (req->mask == 0 || (value << req->shift) & ~req->mask)
635*4882a593Smuzhiyun 		return -EINVAL;
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	vreg->val[req->word] &= ~req->mask;
638*4882a593Smuzhiyun 	vreg->val[req->word] |= value << req->shift;
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 	return 0;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun 
rpm_reg_of_parse_freq(struct device * dev,struct device_node * node,struct qcom_rpm_reg * vreg)643*4882a593Smuzhiyun static int rpm_reg_of_parse_freq(struct device *dev,
644*4882a593Smuzhiyun 				 struct device_node *node,
645*4882a593Smuzhiyun 				 struct qcom_rpm_reg *vreg)
646*4882a593Smuzhiyun {
647*4882a593Smuzhiyun 	static const int freq_table[] = {
648*4882a593Smuzhiyun 		19200000, 9600000, 6400000, 4800000, 3840000, 3200000, 2740000,
649*4882a593Smuzhiyun 		2400000, 2130000, 1920000, 1750000, 1600000, 1480000, 1370000,
650*4882a593Smuzhiyun 		1280000, 1200000,
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	};
653*4882a593Smuzhiyun 	const char *key;
654*4882a593Smuzhiyun 	u32 freq;
655*4882a593Smuzhiyun 	int ret;
656*4882a593Smuzhiyun 	int i;
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	key = "qcom,switch-mode-frequency";
659*4882a593Smuzhiyun 	ret = of_property_read_u32(node, key, &freq);
660*4882a593Smuzhiyun 	if (ret) {
661*4882a593Smuzhiyun 		dev_err(dev, "regulator requires %s property\n", key);
662*4882a593Smuzhiyun 		return -EINVAL;
663*4882a593Smuzhiyun 	}
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(freq_table); i++) {
666*4882a593Smuzhiyun 		if (freq == freq_table[i]) {
667*4882a593Smuzhiyun 			rpm_reg_set(vreg, &vreg->parts->freq, i + 1);
668*4882a593Smuzhiyun 			return 0;
669*4882a593Smuzhiyun 		}
670*4882a593Smuzhiyun 	}
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun 	dev_err(dev, "invalid frequency %d\n", freq);
673*4882a593Smuzhiyun 	return -EINVAL;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun 
rpm_reg_of_parse(struct device_node * node,const struct regulator_desc * desc,struct regulator_config * config)676*4882a593Smuzhiyun static int rpm_reg_of_parse(struct device_node *node,
677*4882a593Smuzhiyun 			    const struct regulator_desc *desc,
678*4882a593Smuzhiyun 			    struct regulator_config *config)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg = config->driver_data;
681*4882a593Smuzhiyun 	struct device *dev = config->dev;
682*4882a593Smuzhiyun 	const char *key;
683*4882a593Smuzhiyun 	u32 force_mode;
684*4882a593Smuzhiyun 	bool pwm;
685*4882a593Smuzhiyun 	u32 val;
686*4882a593Smuzhiyun 	int ret;
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	key = "bias-pull-down";
689*4882a593Smuzhiyun 	if (of_property_read_bool(node, key)) {
690*4882a593Smuzhiyun 		ret = rpm_reg_set(vreg, &vreg->parts->pd, 1);
691*4882a593Smuzhiyun 		if (ret) {
692*4882a593Smuzhiyun 			dev_err(dev, "%s is invalid", key);
693*4882a593Smuzhiyun 			return ret;
694*4882a593Smuzhiyun 		}
695*4882a593Smuzhiyun 	}
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	if (vreg->parts->freq.mask) {
698*4882a593Smuzhiyun 		ret = rpm_reg_of_parse_freq(dev, node, vreg);
699*4882a593Smuzhiyun 		if (ret < 0)
700*4882a593Smuzhiyun 			return ret;
701*4882a593Smuzhiyun 	}
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	if (vreg->parts->pm.mask) {
704*4882a593Smuzhiyun 		key = "qcom,power-mode-hysteretic";
705*4882a593Smuzhiyun 		pwm = !of_property_read_bool(node, key);
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 		ret = rpm_reg_set(vreg, &vreg->parts->pm, pwm);
708*4882a593Smuzhiyun 		if (ret) {
709*4882a593Smuzhiyun 			dev_err(dev, "failed to set power mode\n");
710*4882a593Smuzhiyun 			return ret;
711*4882a593Smuzhiyun 		}
712*4882a593Smuzhiyun 	}
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	if (vreg->parts->fm.mask) {
715*4882a593Smuzhiyun 		force_mode = -1;
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 		key = "qcom,force-mode";
718*4882a593Smuzhiyun 		ret = of_property_read_u32(node, key, &val);
719*4882a593Smuzhiyun 		if (ret == -EINVAL) {
720*4882a593Smuzhiyun 			val = QCOM_RPM_FORCE_MODE_NONE;
721*4882a593Smuzhiyun 		} else if (ret < 0) {
722*4882a593Smuzhiyun 			dev_err(dev, "failed to read %s\n", key);
723*4882a593Smuzhiyun 			return ret;
724*4882a593Smuzhiyun 		}
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun 		/*
727*4882a593Smuzhiyun 		 * If force-mode is encoded as 2 bits then the
728*4882a593Smuzhiyun 		 * possible register values are:
729*4882a593Smuzhiyun 		 * NONE, LPM, HPM
730*4882a593Smuzhiyun 		 * otherwise:
731*4882a593Smuzhiyun 		 * NONE, LPM, AUTO, HPM, BYPASS
732*4882a593Smuzhiyun 		 */
733*4882a593Smuzhiyun 		switch (val) {
734*4882a593Smuzhiyun 		case QCOM_RPM_FORCE_MODE_NONE:
735*4882a593Smuzhiyun 			force_mode = 0;
736*4882a593Smuzhiyun 			break;
737*4882a593Smuzhiyun 		case QCOM_RPM_FORCE_MODE_LPM:
738*4882a593Smuzhiyun 			force_mode = 1;
739*4882a593Smuzhiyun 			break;
740*4882a593Smuzhiyun 		case QCOM_RPM_FORCE_MODE_HPM:
741*4882a593Smuzhiyun 			if (FORCE_MODE_IS_2_BITS(vreg))
742*4882a593Smuzhiyun 				force_mode = 2;
743*4882a593Smuzhiyun 			else
744*4882a593Smuzhiyun 				force_mode = 3;
745*4882a593Smuzhiyun 			break;
746*4882a593Smuzhiyun 		case QCOM_RPM_FORCE_MODE_AUTO:
747*4882a593Smuzhiyun 			if (vreg->supports_force_mode_auto)
748*4882a593Smuzhiyun 				force_mode = 2;
749*4882a593Smuzhiyun 			break;
750*4882a593Smuzhiyun 		case QCOM_RPM_FORCE_MODE_BYPASS:
751*4882a593Smuzhiyun 			if (vreg->supports_force_mode_bypass)
752*4882a593Smuzhiyun 				force_mode = 4;
753*4882a593Smuzhiyun 			break;
754*4882a593Smuzhiyun 		}
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun 		if (force_mode == -1) {
757*4882a593Smuzhiyun 			dev_err(dev, "invalid force mode\n");
758*4882a593Smuzhiyun 			return -EINVAL;
759*4882a593Smuzhiyun 		}
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun 		ret = rpm_reg_set(vreg, &vreg->parts->fm, force_mode);
762*4882a593Smuzhiyun 		if (ret) {
763*4882a593Smuzhiyun 			dev_err(dev, "failed to set force mode\n");
764*4882a593Smuzhiyun 			return ret;
765*4882a593Smuzhiyun 		}
766*4882a593Smuzhiyun 	}
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 	return 0;
769*4882a593Smuzhiyun }
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun struct rpm_regulator_data {
772*4882a593Smuzhiyun 	const char *name;
773*4882a593Smuzhiyun 	int resource;
774*4882a593Smuzhiyun 	const struct qcom_rpm_reg *template;
775*4882a593Smuzhiyun 	const char *supply;
776*4882a593Smuzhiyun };
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8018_regulators[] = {
779*4882a593Smuzhiyun 	{ "s1",  QCOM_RPM_PM8018_SMPS1, &pm8018_smps, "vdd_s1" },
780*4882a593Smuzhiyun 	{ "s2",  QCOM_RPM_PM8018_SMPS2, &pm8018_smps, "vdd_s2" },
781*4882a593Smuzhiyun 	{ "s3",  QCOM_RPM_PM8018_SMPS3, &pm8018_smps, "vdd_s3" },
782*4882a593Smuzhiyun 	{ "s4",  QCOM_RPM_PM8018_SMPS4, &pm8018_smps, "vdd_s4" },
783*4882a593Smuzhiyun 	{ "s5",  QCOM_RPM_PM8018_SMPS5, &pm8018_smps, "vdd_s5" },
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun 	{ "l2",  QCOM_RPM_PM8018_LDO2,  &pm8018_pldo, "vdd_l2" },
786*4882a593Smuzhiyun 	{ "l3",  QCOM_RPM_PM8018_LDO3,  &pm8018_pldo, "vdd_l3" },
787*4882a593Smuzhiyun 	{ "l4",  QCOM_RPM_PM8018_LDO4,  &pm8018_pldo, "vdd_l4" },
788*4882a593Smuzhiyun 	{ "l5",  QCOM_RPM_PM8018_LDO5,  &pm8018_pldo, "vdd_l5" },
789*4882a593Smuzhiyun 	{ "l6",  QCOM_RPM_PM8018_LDO6,  &pm8018_pldo, "vdd_l7" },
790*4882a593Smuzhiyun 	{ "l7",  QCOM_RPM_PM8018_LDO7,  &pm8018_pldo, "vdd_l7" },
791*4882a593Smuzhiyun 	{ "l8",  QCOM_RPM_PM8018_LDO8,  &pm8018_nldo, "vdd_l8" },
792*4882a593Smuzhiyun 	{ "l9",  QCOM_RPM_PM8018_LDO9,  &pm8921_nldo1200,
793*4882a593Smuzhiyun 						      "vdd_l9_l10_l11_l12" },
794*4882a593Smuzhiyun 	{ "l10", QCOM_RPM_PM8018_LDO10, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
795*4882a593Smuzhiyun 	{ "l11", QCOM_RPM_PM8018_LDO11, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
796*4882a593Smuzhiyun 	{ "l12", QCOM_RPM_PM8018_LDO12, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
797*4882a593Smuzhiyun 	{ "l14", QCOM_RPM_PM8018_LDO14, &pm8018_pldo, "vdd_l14" },
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	{ "lvs1", QCOM_RPM_PM8018_LVS1, &pm8018_switch, "lvs1_in" },
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	{ }
802*4882a593Smuzhiyun };
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8058_regulators[] = {
805*4882a593Smuzhiyun 	{ "s0",   QCOM_RPM_PM8058_SMPS0,  &pm8058_smps, "vdd_s0" },
806*4882a593Smuzhiyun 	{ "s1",   QCOM_RPM_PM8058_SMPS1,  &pm8058_smps, "vdd_s1" },
807*4882a593Smuzhiyun 	{ "s2",   QCOM_RPM_PM8058_SMPS2,  &pm8058_smps, "vdd_s2" },
808*4882a593Smuzhiyun 	{ "s3",   QCOM_RPM_PM8058_SMPS3,  &pm8058_smps, "vdd_s3" },
809*4882a593Smuzhiyun 	{ "s4",   QCOM_RPM_PM8058_SMPS4,  &pm8058_smps, "vdd_s4" },
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun 	{ "l0",   QCOM_RPM_PM8058_LDO0,   &pm8058_nldo, "vdd_l0_l1_lvs"	},
812*4882a593Smuzhiyun 	{ "l1",   QCOM_RPM_PM8058_LDO1,   &pm8058_nldo, "vdd_l0_l1_lvs" },
813*4882a593Smuzhiyun 	{ "l2",   QCOM_RPM_PM8058_LDO2,   &pm8058_pldo, "vdd_l2_l11_l12" },
814*4882a593Smuzhiyun 	{ "l3",   QCOM_RPM_PM8058_LDO3,   &pm8058_pldo, "vdd_l3_l4_l5" },
815*4882a593Smuzhiyun 	{ "l4",   QCOM_RPM_PM8058_LDO4,   &pm8058_pldo, "vdd_l3_l4_l5" },
816*4882a593Smuzhiyun 	{ "l5",   QCOM_RPM_PM8058_LDO5,   &pm8058_pldo, "vdd_l3_l4_l5" },
817*4882a593Smuzhiyun 	{ "l6",   QCOM_RPM_PM8058_LDO6,   &pm8058_pldo, "vdd_l6_l7" },
818*4882a593Smuzhiyun 	{ "l7",   QCOM_RPM_PM8058_LDO7,   &pm8058_pldo, "vdd_l6_l7" },
819*4882a593Smuzhiyun 	{ "l8",   QCOM_RPM_PM8058_LDO8,   &pm8058_pldo, "vdd_l8" },
820*4882a593Smuzhiyun 	{ "l9",   QCOM_RPM_PM8058_LDO9,   &pm8058_pldo, "vdd_l9" },
821*4882a593Smuzhiyun 	{ "l10",  QCOM_RPM_PM8058_LDO10,  &pm8058_pldo, "vdd_l10" },
822*4882a593Smuzhiyun 	{ "l11",  QCOM_RPM_PM8058_LDO11,  &pm8058_pldo, "vdd_l2_l11_l12" },
823*4882a593Smuzhiyun 	{ "l12",  QCOM_RPM_PM8058_LDO12,  &pm8058_pldo, "vdd_l2_l11_l12" },
824*4882a593Smuzhiyun 	{ "l13",  QCOM_RPM_PM8058_LDO13,  &pm8058_pldo, "vdd_l13_l16" },
825*4882a593Smuzhiyun 	{ "l14",  QCOM_RPM_PM8058_LDO14,  &pm8058_pldo, "vdd_l14_l15" },
826*4882a593Smuzhiyun 	{ "l15",  QCOM_RPM_PM8058_LDO15,  &pm8058_pldo, "vdd_l14_l15" },
827*4882a593Smuzhiyun 	{ "l16",  QCOM_RPM_PM8058_LDO16,  &pm8058_pldo, "vdd_l13_l16" },
828*4882a593Smuzhiyun 	{ "l17",  QCOM_RPM_PM8058_LDO17,  &pm8058_pldo, "vdd_l17_l18" },
829*4882a593Smuzhiyun 	{ "l18",  QCOM_RPM_PM8058_LDO18,  &pm8058_pldo, "vdd_l17_l18" },
830*4882a593Smuzhiyun 	{ "l19",  QCOM_RPM_PM8058_LDO19,  &pm8058_pldo, "vdd_l19_l20" },
831*4882a593Smuzhiyun 	{ "l20",  QCOM_RPM_PM8058_LDO20,  &pm8058_pldo, "vdd_l19_l20" },
832*4882a593Smuzhiyun 	{ "l21",  QCOM_RPM_PM8058_LDO21,  &pm8058_nldo, "vdd_l21" },
833*4882a593Smuzhiyun 	{ "l22",  QCOM_RPM_PM8058_LDO22,  &pm8058_nldo, "vdd_l22" },
834*4882a593Smuzhiyun 	{ "l23",  QCOM_RPM_PM8058_LDO23,  &pm8058_nldo, "vdd_l23_l24_l25" },
835*4882a593Smuzhiyun 	{ "l24",  QCOM_RPM_PM8058_LDO24,  &pm8058_nldo, "vdd_l23_l24_l25" },
836*4882a593Smuzhiyun 	{ "l25",  QCOM_RPM_PM8058_LDO25,  &pm8058_nldo, "vdd_l23_l24_l25" },
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun 	{ "lvs0", QCOM_RPM_PM8058_LVS0, &pm8058_switch, "vdd_l0_l1_lvs" },
839*4882a593Smuzhiyun 	{ "lvs1", QCOM_RPM_PM8058_LVS1, &pm8058_switch, "vdd_l0_l1_lvs" },
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 	{ "ncp",  QCOM_RPM_PM8058_NCP, &pm8058_ncp, "vdd_ncp" },
842*4882a593Smuzhiyun 	{ }
843*4882a593Smuzhiyun };
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8901_regulators[] = {
846*4882a593Smuzhiyun 	{ "s0",   QCOM_RPM_PM8901_SMPS0, &pm8901_ftsmps, "vdd_s0" },
847*4882a593Smuzhiyun 	{ "s1",   QCOM_RPM_PM8901_SMPS1, &pm8901_ftsmps, "vdd_s1" },
848*4882a593Smuzhiyun 	{ "s2",   QCOM_RPM_PM8901_SMPS2, &pm8901_ftsmps, "vdd_s2" },
849*4882a593Smuzhiyun 	{ "s3",   QCOM_RPM_PM8901_SMPS3, &pm8901_ftsmps, "vdd_s3" },
850*4882a593Smuzhiyun 	{ "s4",   QCOM_RPM_PM8901_SMPS4, &pm8901_ftsmps, "vdd_s4" },
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 	{ "l0",   QCOM_RPM_PM8901_LDO0, &pm8901_nldo, "vdd_l0" },
853*4882a593Smuzhiyun 	{ "l1",   QCOM_RPM_PM8901_LDO1, &pm8901_pldo, "vdd_l1" },
854*4882a593Smuzhiyun 	{ "l2",   QCOM_RPM_PM8901_LDO2, &pm8901_pldo, "vdd_l2" },
855*4882a593Smuzhiyun 	{ "l3",   QCOM_RPM_PM8901_LDO3, &pm8901_pldo, "vdd_l3" },
856*4882a593Smuzhiyun 	{ "l4",   QCOM_RPM_PM8901_LDO4, &pm8901_pldo, "vdd_l4" },
857*4882a593Smuzhiyun 	{ "l5",   QCOM_RPM_PM8901_LDO5, &pm8901_pldo, "vdd_l5" },
858*4882a593Smuzhiyun 	{ "l6",   QCOM_RPM_PM8901_LDO6, &pm8901_pldo, "vdd_l6" },
859*4882a593Smuzhiyun 
860*4882a593Smuzhiyun 	{ "lvs0", QCOM_RPM_PM8901_LVS0, &pm8901_switch, "lvs0_in" },
861*4882a593Smuzhiyun 	{ "lvs1", QCOM_RPM_PM8901_LVS1, &pm8901_switch, "lvs1_in" },
862*4882a593Smuzhiyun 	{ "lvs2", QCOM_RPM_PM8901_LVS2, &pm8901_switch, "lvs2_in" },
863*4882a593Smuzhiyun 	{ "lvs3", QCOM_RPM_PM8901_LVS3, &pm8901_switch, "lvs3_in" },
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	{ "mvs", QCOM_RPM_PM8901_MVS, &pm8901_switch, "mvs_in" },
866*4882a593Smuzhiyun 	{ }
867*4882a593Smuzhiyun };
868*4882a593Smuzhiyun 
869*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_pm8921_regulators[] = {
870*4882a593Smuzhiyun 	{ "s1",  QCOM_RPM_PM8921_SMPS1, &pm8921_smps, "vdd_s1" },
871*4882a593Smuzhiyun 	{ "s2",  QCOM_RPM_PM8921_SMPS2, &pm8921_smps, "vdd_s2" },
872*4882a593Smuzhiyun 	{ "s3",  QCOM_RPM_PM8921_SMPS3, &pm8921_smps },
873*4882a593Smuzhiyun 	{ "s4",  QCOM_RPM_PM8921_SMPS4, &pm8921_smps, "vdd_s4" },
874*4882a593Smuzhiyun 	{ "s7",  QCOM_RPM_PM8921_SMPS7, &pm8921_smps, "vdd_s7" },
875*4882a593Smuzhiyun 	{ "s8",  QCOM_RPM_PM8921_SMPS8, &pm8921_smps, "vdd_s8"  },
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	{ "l1",  QCOM_RPM_PM8921_LDO1, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
878*4882a593Smuzhiyun 	{ "l2",  QCOM_RPM_PM8921_LDO2, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
879*4882a593Smuzhiyun 	{ "l3",  QCOM_RPM_PM8921_LDO3, &pm8921_pldo, "vdd_l3_l15_l17" },
880*4882a593Smuzhiyun 	{ "l4",  QCOM_RPM_PM8921_LDO4, &pm8921_pldo, "vdd_l4_l14" },
881*4882a593Smuzhiyun 	{ "l5",  QCOM_RPM_PM8921_LDO5, &pm8921_pldo, "vdd_l5_l8_l16" },
882*4882a593Smuzhiyun 	{ "l6",  QCOM_RPM_PM8921_LDO6, &pm8921_pldo, "vdd_l6_l7" },
883*4882a593Smuzhiyun 	{ "l7",  QCOM_RPM_PM8921_LDO7, &pm8921_pldo, "vdd_l6_l7" },
884*4882a593Smuzhiyun 	{ "l8",  QCOM_RPM_PM8921_LDO8, &pm8921_pldo, "vdd_l5_l8_l16" },
885*4882a593Smuzhiyun 	{ "l9",  QCOM_RPM_PM8921_LDO9, &pm8921_pldo, "vdd_l9_l11" },
886*4882a593Smuzhiyun 	{ "l10", QCOM_RPM_PM8921_LDO10, &pm8921_pldo, "vdd_l10_l22" },
887*4882a593Smuzhiyun 	{ "l11", QCOM_RPM_PM8921_LDO11, &pm8921_pldo, "vdd_l9_l11" },
888*4882a593Smuzhiyun 	{ "l12", QCOM_RPM_PM8921_LDO12, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
889*4882a593Smuzhiyun 	{ "l14", QCOM_RPM_PM8921_LDO14, &pm8921_pldo, "vdd_l4_l14" },
890*4882a593Smuzhiyun 	{ "l15", QCOM_RPM_PM8921_LDO15, &pm8921_pldo, "vdd_l3_l15_l17" },
891*4882a593Smuzhiyun 	{ "l16", QCOM_RPM_PM8921_LDO16, &pm8921_pldo, "vdd_l5_l8_l16" },
892*4882a593Smuzhiyun 	{ "l17", QCOM_RPM_PM8921_LDO17, &pm8921_pldo, "vdd_l3_l15_l17" },
893*4882a593Smuzhiyun 	{ "l18", QCOM_RPM_PM8921_LDO18, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
894*4882a593Smuzhiyun 	{ "l21", QCOM_RPM_PM8921_LDO21, &pm8921_pldo, "vdd_l21_l23_l29" },
895*4882a593Smuzhiyun 	{ "l22", QCOM_RPM_PM8921_LDO22, &pm8921_pldo, "vdd_l10_l22" },
896*4882a593Smuzhiyun 	{ "l23", QCOM_RPM_PM8921_LDO23, &pm8921_pldo, "vdd_l21_l23_l29" },
897*4882a593Smuzhiyun 	{ "l24", QCOM_RPM_PM8921_LDO24, &pm8921_nldo1200, "vdd_l24" },
898*4882a593Smuzhiyun 	{ "l25", QCOM_RPM_PM8921_LDO25, &pm8921_nldo1200, "vdd_l25" },
899*4882a593Smuzhiyun 	{ "l26", QCOM_RPM_PM8921_LDO26, &pm8921_nldo1200, "vdd_l26" },
900*4882a593Smuzhiyun 	{ "l27", QCOM_RPM_PM8921_LDO27, &pm8921_nldo1200, "vdd_l27" },
901*4882a593Smuzhiyun 	{ "l28", QCOM_RPM_PM8921_LDO28, &pm8921_nldo1200, "vdd_l28" },
902*4882a593Smuzhiyun 	{ "l29", QCOM_RPM_PM8921_LDO29, &pm8921_pldo, "vdd_l21_l23_l29" },
903*4882a593Smuzhiyun 
904*4882a593Smuzhiyun 	{ "lvs1", QCOM_RPM_PM8921_LVS1, &pm8921_switch, "vin_lvs1_3_6" },
905*4882a593Smuzhiyun 	{ "lvs2", QCOM_RPM_PM8921_LVS2, &pm8921_switch, "vin_lvs2" },
906*4882a593Smuzhiyun 	{ "lvs3", QCOM_RPM_PM8921_LVS3, &pm8921_switch, "vin_lvs1_3_6" },
907*4882a593Smuzhiyun 	{ "lvs4", QCOM_RPM_PM8921_LVS4, &pm8921_switch, "vin_lvs4_5_7" },
908*4882a593Smuzhiyun 	{ "lvs5", QCOM_RPM_PM8921_LVS5, &pm8921_switch, "vin_lvs4_5_7" },
909*4882a593Smuzhiyun 	{ "lvs6", QCOM_RPM_PM8921_LVS6, &pm8921_switch, "vin_lvs1_3_6" },
910*4882a593Smuzhiyun 	{ "lvs7", QCOM_RPM_PM8921_LVS7, &pm8921_switch, "vin_lvs4_5_7" },
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	{ "usb-switch", QCOM_RPM_USB_OTG_SWITCH, &pm8921_switch, "vin_5vs" },
913*4882a593Smuzhiyun 	{ "hdmi-switch", QCOM_RPM_HDMI_SWITCH, &pm8921_switch, "vin_5vs" },
914*4882a593Smuzhiyun 	{ "ncp", QCOM_RPM_PM8921_NCP, &pm8921_ncp, "vdd_ncp" },
915*4882a593Smuzhiyun 	{ }
916*4882a593Smuzhiyun };
917*4882a593Smuzhiyun 
918*4882a593Smuzhiyun static const struct rpm_regulator_data rpm_smb208_regulators[] = {
919*4882a593Smuzhiyun 	{ "s1a",  QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" },
920*4882a593Smuzhiyun 	{ "s1b",  QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" },
921*4882a593Smuzhiyun 	{ "s2a",  QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" },
922*4882a593Smuzhiyun 	{ "s2b",  QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" },
923*4882a593Smuzhiyun 	{ }
924*4882a593Smuzhiyun };
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun static const struct of_device_id rpm_of_match[] = {
927*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8018-regulators",
928*4882a593Smuzhiyun 		.data = &rpm_pm8018_regulators },
929*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators },
930*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators },
931*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators },
932*4882a593Smuzhiyun 	{ .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators },
933*4882a593Smuzhiyun 	{ }
934*4882a593Smuzhiyun };
935*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rpm_of_match);
936*4882a593Smuzhiyun 
rpm_reg_probe(struct platform_device * pdev)937*4882a593Smuzhiyun static int rpm_reg_probe(struct platform_device *pdev)
938*4882a593Smuzhiyun {
939*4882a593Smuzhiyun 	const struct rpm_regulator_data *reg;
940*4882a593Smuzhiyun 	const struct of_device_id *match;
941*4882a593Smuzhiyun 	struct regulator_config config = { };
942*4882a593Smuzhiyun 	struct regulator_dev *rdev;
943*4882a593Smuzhiyun 	struct qcom_rpm_reg *vreg;
944*4882a593Smuzhiyun 	struct qcom_rpm *rpm;
945*4882a593Smuzhiyun 
946*4882a593Smuzhiyun 	rpm = dev_get_drvdata(pdev->dev.parent);
947*4882a593Smuzhiyun 	if (!rpm) {
948*4882a593Smuzhiyun 		dev_err(&pdev->dev, "unable to retrieve handle to rpm\n");
949*4882a593Smuzhiyun 		return -ENODEV;
950*4882a593Smuzhiyun 	}
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	match = of_match_device(rpm_of_match, &pdev->dev);
953*4882a593Smuzhiyun 	if (!match) {
954*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to match device\n");
955*4882a593Smuzhiyun 		return -ENODEV;
956*4882a593Smuzhiyun 	}
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun 	for (reg = match->data; reg->name; reg++) {
959*4882a593Smuzhiyun 		vreg = devm_kmalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
960*4882a593Smuzhiyun 		if (!vreg)
961*4882a593Smuzhiyun 			return -ENOMEM;
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun 		memcpy(vreg, reg->template, sizeof(*vreg));
964*4882a593Smuzhiyun 		mutex_init(&vreg->lock);
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 		vreg->dev = &pdev->dev;
967*4882a593Smuzhiyun 		vreg->resource = reg->resource;
968*4882a593Smuzhiyun 		vreg->rpm = rpm;
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 		vreg->desc.id = -1;
971*4882a593Smuzhiyun 		vreg->desc.owner = THIS_MODULE;
972*4882a593Smuzhiyun 		vreg->desc.type = REGULATOR_VOLTAGE;
973*4882a593Smuzhiyun 		vreg->desc.name = reg->name;
974*4882a593Smuzhiyun 		vreg->desc.supply_name = reg->supply;
975*4882a593Smuzhiyun 		vreg->desc.of_match = reg->name;
976*4882a593Smuzhiyun 		vreg->desc.of_parse_cb = rpm_reg_of_parse;
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 		config.dev = &pdev->dev;
979*4882a593Smuzhiyun 		config.driver_data = vreg;
980*4882a593Smuzhiyun 		rdev = devm_regulator_register(&pdev->dev, &vreg->desc, &config);
981*4882a593Smuzhiyun 		if (IS_ERR(rdev)) {
982*4882a593Smuzhiyun 			dev_err(&pdev->dev, "failed to register %s\n", reg->name);
983*4882a593Smuzhiyun 			return PTR_ERR(rdev);
984*4882a593Smuzhiyun 		}
985*4882a593Smuzhiyun 	}
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 	return 0;
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun static struct platform_driver rpm_reg_driver = {
991*4882a593Smuzhiyun 	.probe          = rpm_reg_probe,
992*4882a593Smuzhiyun 	.driver  = {
993*4882a593Smuzhiyun 		.name  = "qcom_rpm_reg",
994*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(rpm_of_match),
995*4882a593Smuzhiyun 	},
996*4882a593Smuzhiyun };
997*4882a593Smuzhiyun 
rpm_reg_init(void)998*4882a593Smuzhiyun static int __init rpm_reg_init(void)
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun 	return platform_driver_register(&rpm_reg_driver);
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun subsys_initcall(rpm_reg_init);
1003*4882a593Smuzhiyun 
rpm_reg_exit(void)1004*4882a593Smuzhiyun static void __exit rpm_reg_exit(void)
1005*4882a593Smuzhiyun {
1006*4882a593Smuzhiyun 	platform_driver_unregister(&rpm_reg_driver);
1007*4882a593Smuzhiyun }
1008*4882a593Smuzhiyun module_exit(rpm_reg_exit)
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
1011*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1012