1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // pv88090-regulator.c - Regulator device driver for PV88090
4*4882a593Smuzhiyun // Copyright (C) 2015 Powerventure Semiconductor Ltd.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/err.h>
7*4882a593Smuzhiyun #include <linux/i2c.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/regulator/driver.h>
12*4882a593Smuzhiyun #include <linux/regulator/machine.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
17*4882a593Smuzhiyun #include "pv88090-regulator.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define PV88090_MAX_REGULATORS 5
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* PV88090 REGULATOR IDs */
22*4882a593Smuzhiyun enum {
23*4882a593Smuzhiyun /* BUCKs */
24*4882a593Smuzhiyun PV88090_ID_BUCK1,
25*4882a593Smuzhiyun PV88090_ID_BUCK2,
26*4882a593Smuzhiyun PV88090_ID_BUCK3,
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* LDOs */
29*4882a593Smuzhiyun PV88090_ID_LDO1,
30*4882a593Smuzhiyun PV88090_ID_LDO2,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct pv88090_regulator {
34*4882a593Smuzhiyun struct regulator_desc desc;
35*4882a593Smuzhiyun unsigned int conf;
36*4882a593Smuzhiyun unsigned int conf2;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct pv88090 {
40*4882a593Smuzhiyun struct device *dev;
41*4882a593Smuzhiyun struct regmap *regmap;
42*4882a593Smuzhiyun struct regulator_dev *rdev[PV88090_MAX_REGULATORS];
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct pv88090_buck_voltage {
46*4882a593Smuzhiyun int min_uV;
47*4882a593Smuzhiyun int max_uV;
48*4882a593Smuzhiyun int uV_step;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static const struct regmap_config pv88090_regmap_config = {
52*4882a593Smuzhiyun .reg_bits = 8,
53*4882a593Smuzhiyun .val_bits = 8,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Current limits array (in uA) for BUCK1, BUCK2, BUCK3.
57*4882a593Smuzhiyun * Entry indexes corresponds to register values.
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const unsigned int pv88090_buck1_limits[] = {
61*4882a593Smuzhiyun 220000, 440000, 660000, 880000, 1100000, 1320000, 1540000, 1760000,
62*4882a593Smuzhiyun 1980000, 2200000, 2420000, 2640000, 2860000, 3080000, 3300000, 3520000,
63*4882a593Smuzhiyun 3740000, 3960000, 4180000, 4400000, 4620000, 4840000, 5060000, 5280000,
64*4882a593Smuzhiyun 5500000, 5720000, 5940000, 6160000, 6380000, 6600000, 6820000, 7040000
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const unsigned int pv88090_buck23_limits[] = {
68*4882a593Smuzhiyun 1496000, 2393000, 3291000, 4189000
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct pv88090_buck_voltage pv88090_buck_vol[3] = {
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun .min_uV = 600000,
74*4882a593Smuzhiyun .max_uV = 1393750,
75*4882a593Smuzhiyun .uV_step = 6250,
76*4882a593Smuzhiyun },
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun .min_uV = 1400000,
80*4882a593Smuzhiyun .max_uV = 2193750,
81*4882a593Smuzhiyun .uV_step = 6250,
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun .min_uV = 1250000,
85*4882a593Smuzhiyun .max_uV = 2837500,
86*4882a593Smuzhiyun .uV_step = 12500,
87*4882a593Smuzhiyun },
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
pv88090_buck_get_mode(struct regulator_dev * rdev)90*4882a593Smuzhiyun static unsigned int pv88090_buck_get_mode(struct regulator_dev *rdev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct pv88090_regulator *info = rdev_get_drvdata(rdev);
93*4882a593Smuzhiyun unsigned int data;
94*4882a593Smuzhiyun int ret, mode = 0;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, info->conf, &data);
97*4882a593Smuzhiyun if (ret < 0)
98*4882a593Smuzhiyun return ret;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun switch (data & PV88090_BUCK1_MODE_MASK) {
101*4882a593Smuzhiyun case PV88090_BUCK_MODE_SYNC:
102*4882a593Smuzhiyun mode = REGULATOR_MODE_FAST;
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun case PV88090_BUCK_MODE_AUTO:
105*4882a593Smuzhiyun mode = REGULATOR_MODE_NORMAL;
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun case PV88090_BUCK_MODE_SLEEP:
108*4882a593Smuzhiyun mode = REGULATOR_MODE_STANDBY;
109*4882a593Smuzhiyun break;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return mode;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
pv88090_buck_set_mode(struct regulator_dev * rdev,unsigned int mode)115*4882a593Smuzhiyun static int pv88090_buck_set_mode(struct regulator_dev *rdev,
116*4882a593Smuzhiyun unsigned int mode)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun struct pv88090_regulator *info = rdev_get_drvdata(rdev);
119*4882a593Smuzhiyun int val = 0;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun switch (mode) {
122*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
123*4882a593Smuzhiyun val = PV88090_BUCK_MODE_SYNC;
124*4882a593Smuzhiyun break;
125*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
126*4882a593Smuzhiyun val = PV88090_BUCK_MODE_AUTO;
127*4882a593Smuzhiyun break;
128*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
129*4882a593Smuzhiyun val = PV88090_BUCK_MODE_SLEEP;
130*4882a593Smuzhiyun break;
131*4882a593Smuzhiyun default:
132*4882a593Smuzhiyun return -EINVAL;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, info->conf,
136*4882a593Smuzhiyun PV88090_BUCK1_MODE_MASK, val);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static const struct regulator_ops pv88090_buck_ops = {
140*4882a593Smuzhiyun .get_mode = pv88090_buck_get_mode,
141*4882a593Smuzhiyun .set_mode = pv88090_buck_set_mode,
142*4882a593Smuzhiyun .enable = regulator_enable_regmap,
143*4882a593Smuzhiyun .disable = regulator_disable_regmap,
144*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
145*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
146*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
147*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
148*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
149*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static const struct regulator_ops pv88090_ldo_ops = {
153*4882a593Smuzhiyun .enable = regulator_enable_regmap,
154*4882a593Smuzhiyun .disable = regulator_disable_regmap,
155*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
156*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
157*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
158*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun #define PV88090_BUCK(chip, regl_name, min, step, max, limits_array) \
162*4882a593Smuzhiyun {\
163*4882a593Smuzhiyun .desc = {\
164*4882a593Smuzhiyun .id = chip##_ID_##regl_name,\
165*4882a593Smuzhiyun .name = __stringify(chip##_##regl_name),\
166*4882a593Smuzhiyun .of_match = of_match_ptr(#regl_name),\
167*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),\
168*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,\
169*4882a593Smuzhiyun .owner = THIS_MODULE,\
170*4882a593Smuzhiyun .ops = &pv88090_buck_ops,\
171*4882a593Smuzhiyun .min_uV = min, \
172*4882a593Smuzhiyun .uV_step = step, \
173*4882a593Smuzhiyun .n_voltages = ((max) - (min))/(step) + 1, \
174*4882a593Smuzhiyun .enable_reg = PV88090_REG_##regl_name##_CONF0, \
175*4882a593Smuzhiyun .enable_mask = PV88090_##regl_name##_EN, \
176*4882a593Smuzhiyun .vsel_reg = PV88090_REG_##regl_name##_CONF0, \
177*4882a593Smuzhiyun .vsel_mask = PV88090_V##regl_name##_MASK, \
178*4882a593Smuzhiyun .curr_table = limits_array, \
179*4882a593Smuzhiyun .n_current_limits = ARRAY_SIZE(limits_array), \
180*4882a593Smuzhiyun .csel_reg = PV88090_REG_##regl_name##_CONF1, \
181*4882a593Smuzhiyun .csel_mask = PV88090_##regl_name##_ILIM_MASK, \
182*4882a593Smuzhiyun },\
183*4882a593Smuzhiyun .conf = PV88090_REG_##regl_name##_CONF1, \
184*4882a593Smuzhiyun .conf2 = PV88090_REG_##regl_name##_CONF2, \
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun #define PV88090_LDO(chip, regl_name, min, step, max) \
188*4882a593Smuzhiyun {\
189*4882a593Smuzhiyun .desc = {\
190*4882a593Smuzhiyun .id = chip##_ID_##regl_name,\
191*4882a593Smuzhiyun .name = __stringify(chip##_##regl_name),\
192*4882a593Smuzhiyun .of_match = of_match_ptr(#regl_name),\
193*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),\
194*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,\
195*4882a593Smuzhiyun .owner = THIS_MODULE,\
196*4882a593Smuzhiyun .ops = &pv88090_ldo_ops,\
197*4882a593Smuzhiyun .min_uV = min, \
198*4882a593Smuzhiyun .uV_step = step, \
199*4882a593Smuzhiyun .n_voltages = ((max) - (min))/(step) + 1, \
200*4882a593Smuzhiyun .enable_reg = PV88090_REG_##regl_name##_CONT, \
201*4882a593Smuzhiyun .enable_mask = PV88090_##regl_name##_EN, \
202*4882a593Smuzhiyun .vsel_reg = PV88090_REG_##regl_name##_CONT, \
203*4882a593Smuzhiyun .vsel_mask = PV88090_V##regl_name##_MASK, \
204*4882a593Smuzhiyun },\
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static struct pv88090_regulator pv88090_regulator_info[] = {
208*4882a593Smuzhiyun PV88090_BUCK(PV88090, BUCK1, 600000, 6250, 1393750,
209*4882a593Smuzhiyun pv88090_buck1_limits),
210*4882a593Smuzhiyun PV88090_BUCK(PV88090, BUCK2, 600000, 6250, 1393750,
211*4882a593Smuzhiyun pv88090_buck23_limits),
212*4882a593Smuzhiyun PV88090_BUCK(PV88090, BUCK3, 600000, 6250, 1393750,
213*4882a593Smuzhiyun pv88090_buck23_limits),
214*4882a593Smuzhiyun PV88090_LDO(PV88090, LDO1, 1200000, 50000, 4350000),
215*4882a593Smuzhiyun PV88090_LDO(PV88090, LDO2, 650000, 25000, 2225000),
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
pv88090_irq_handler(int irq,void * data)218*4882a593Smuzhiyun static irqreturn_t pv88090_irq_handler(int irq, void *data)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct pv88090 *chip = data;
221*4882a593Smuzhiyun int i, reg_val, err, ret = IRQ_NONE;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun err = regmap_read(chip->regmap, PV88090_REG_EVENT_A, ®_val);
224*4882a593Smuzhiyun if (err < 0)
225*4882a593Smuzhiyun goto error_i2c;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun if (reg_val & PV88090_E_VDD_FLT) {
228*4882a593Smuzhiyun for (i = 0; i < PV88090_MAX_REGULATORS; i++) {
229*4882a593Smuzhiyun if (chip->rdev[i] != NULL)
230*4882a593Smuzhiyun regulator_notifier_call_chain(chip->rdev[i],
231*4882a593Smuzhiyun REGULATOR_EVENT_UNDER_VOLTAGE,
232*4882a593Smuzhiyun NULL);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun err = regmap_write(chip->regmap, PV88090_REG_EVENT_A,
236*4882a593Smuzhiyun PV88090_E_VDD_FLT);
237*4882a593Smuzhiyun if (err < 0)
238*4882a593Smuzhiyun goto error_i2c;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ret = IRQ_HANDLED;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun if (reg_val & PV88090_E_OVER_TEMP) {
244*4882a593Smuzhiyun for (i = 0; i < PV88090_MAX_REGULATORS; i++) {
245*4882a593Smuzhiyun if (chip->rdev[i] != NULL)
246*4882a593Smuzhiyun regulator_notifier_call_chain(chip->rdev[i],
247*4882a593Smuzhiyun REGULATOR_EVENT_OVER_TEMP,
248*4882a593Smuzhiyun NULL);
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun err = regmap_write(chip->regmap, PV88090_REG_EVENT_A,
252*4882a593Smuzhiyun PV88090_E_OVER_TEMP);
253*4882a593Smuzhiyun if (err < 0)
254*4882a593Smuzhiyun goto error_i2c;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun ret = IRQ_HANDLED;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun return ret;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun error_i2c:
262*4882a593Smuzhiyun dev_err(chip->dev, "I2C error : %d\n", err);
263*4882a593Smuzhiyun return IRQ_NONE;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /*
267*4882a593Smuzhiyun * I2C driver interface functions
268*4882a593Smuzhiyun */
pv88090_i2c_probe(struct i2c_client * i2c)269*4882a593Smuzhiyun static int pv88090_i2c_probe(struct i2c_client *i2c)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct regulator_init_data *init_data = dev_get_platdata(&i2c->dev);
272*4882a593Smuzhiyun struct pv88090 *chip;
273*4882a593Smuzhiyun struct regulator_config config = { };
274*4882a593Smuzhiyun int error, i, ret = 0;
275*4882a593Smuzhiyun unsigned int conf2, range, index;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun chip = devm_kzalloc(&i2c->dev, sizeof(struct pv88090), GFP_KERNEL);
278*4882a593Smuzhiyun if (!chip)
279*4882a593Smuzhiyun return -ENOMEM;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun chip->dev = &i2c->dev;
282*4882a593Smuzhiyun chip->regmap = devm_regmap_init_i2c(i2c, &pv88090_regmap_config);
283*4882a593Smuzhiyun if (IS_ERR(chip->regmap)) {
284*4882a593Smuzhiyun error = PTR_ERR(chip->regmap);
285*4882a593Smuzhiyun dev_err(chip->dev, "Failed to allocate register map: %d\n",
286*4882a593Smuzhiyun error);
287*4882a593Smuzhiyun return error;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun i2c_set_clientdata(i2c, chip);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun if (i2c->irq != 0) {
293*4882a593Smuzhiyun ret = regmap_write(chip->regmap, PV88090_REG_MASK_A, 0xFF);
294*4882a593Smuzhiyun if (ret < 0) {
295*4882a593Smuzhiyun dev_err(chip->dev,
296*4882a593Smuzhiyun "Failed to mask A reg: %d\n", ret);
297*4882a593Smuzhiyun return ret;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun ret = regmap_write(chip->regmap, PV88090_REG_MASK_B, 0xFF);
301*4882a593Smuzhiyun if (ret < 0) {
302*4882a593Smuzhiyun dev_err(chip->dev,
303*4882a593Smuzhiyun "Failed to mask B reg: %d\n", ret);
304*4882a593Smuzhiyun return ret;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
308*4882a593Smuzhiyun pv88090_irq_handler,
309*4882a593Smuzhiyun IRQF_TRIGGER_LOW|IRQF_ONESHOT,
310*4882a593Smuzhiyun "pv88090", chip);
311*4882a593Smuzhiyun if (ret != 0) {
312*4882a593Smuzhiyun dev_err(chip->dev, "Failed to request IRQ: %d\n",
313*4882a593Smuzhiyun i2c->irq);
314*4882a593Smuzhiyun return ret;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun ret = regmap_update_bits(chip->regmap, PV88090_REG_MASK_A,
318*4882a593Smuzhiyun PV88090_M_VDD_FLT | PV88090_M_OVER_TEMP, 0);
319*4882a593Smuzhiyun if (ret < 0) {
320*4882a593Smuzhiyun dev_err(chip->dev,
321*4882a593Smuzhiyun "Failed to update mask reg: %d\n", ret);
322*4882a593Smuzhiyun return ret;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun } else {
326*4882a593Smuzhiyun dev_warn(chip->dev, "No IRQ configured\n");
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun config.dev = chip->dev;
330*4882a593Smuzhiyun config.regmap = chip->regmap;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun for (i = 0; i < PV88090_MAX_REGULATORS; i++) {
333*4882a593Smuzhiyun if (init_data)
334*4882a593Smuzhiyun config.init_data = &init_data[i];
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun if (i == PV88090_ID_BUCK2 || i == PV88090_ID_BUCK3) {
337*4882a593Smuzhiyun ret = regmap_read(chip->regmap,
338*4882a593Smuzhiyun pv88090_regulator_info[i].conf2, &conf2);
339*4882a593Smuzhiyun if (ret < 0)
340*4882a593Smuzhiyun return ret;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun conf2 = (conf2 >> PV88090_BUCK_VDAC_RANGE_SHIFT) &
343*4882a593Smuzhiyun PV88090_BUCK_VDAC_RANGE_MASK;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun ret = regmap_read(chip->regmap,
346*4882a593Smuzhiyun PV88090_REG_BUCK_FOLD_RANGE, &range);
347*4882a593Smuzhiyun if (ret < 0)
348*4882a593Smuzhiyun return ret;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun range = (range >>
351*4882a593Smuzhiyun (PV88090_BUCK_VRANGE_GAIN_SHIFT + i - 1)) &
352*4882a593Smuzhiyun PV88090_BUCK_VRANGE_GAIN_MASK;
353*4882a593Smuzhiyun index = ((range << 1) | conf2);
354*4882a593Smuzhiyun if (index > PV88090_ID_BUCK3) {
355*4882a593Smuzhiyun dev_err(chip->dev,
356*4882a593Smuzhiyun "Invalid index(%d)\n", index);
357*4882a593Smuzhiyun return -EINVAL;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun pv88090_regulator_info[i].desc.min_uV
361*4882a593Smuzhiyun = pv88090_buck_vol[index].min_uV;
362*4882a593Smuzhiyun pv88090_regulator_info[i].desc.uV_step
363*4882a593Smuzhiyun = pv88090_buck_vol[index].uV_step;
364*4882a593Smuzhiyun pv88090_regulator_info[i].desc.n_voltages
365*4882a593Smuzhiyun = ((pv88090_buck_vol[index].max_uV)
366*4882a593Smuzhiyun - (pv88090_buck_vol[index].min_uV))
367*4882a593Smuzhiyun /(pv88090_buck_vol[index].uV_step) + 1;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun config.driver_data = (void *)&pv88090_regulator_info[i];
371*4882a593Smuzhiyun chip->rdev[i] = devm_regulator_register(chip->dev,
372*4882a593Smuzhiyun &pv88090_regulator_info[i].desc, &config);
373*4882a593Smuzhiyun if (IS_ERR(chip->rdev[i])) {
374*4882a593Smuzhiyun dev_err(chip->dev,
375*4882a593Smuzhiyun "Failed to register PV88090 regulator\n");
376*4882a593Smuzhiyun return PTR_ERR(chip->rdev[i]);
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun return 0;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun static const struct i2c_device_id pv88090_i2c_id[] = {
384*4882a593Smuzhiyun {"pv88090", 0},
385*4882a593Smuzhiyun {},
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, pv88090_i2c_id);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun #ifdef CONFIG_OF
390*4882a593Smuzhiyun static const struct of_device_id pv88090_dt_ids[] = {
391*4882a593Smuzhiyun { .compatible = "pvs,pv88090", .data = &pv88090_i2c_id[0] },
392*4882a593Smuzhiyun {},
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, pv88090_dt_ids);
395*4882a593Smuzhiyun #endif
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun static struct i2c_driver pv88090_regulator_driver = {
398*4882a593Smuzhiyun .driver = {
399*4882a593Smuzhiyun .name = "pv88090",
400*4882a593Smuzhiyun .of_match_table = of_match_ptr(pv88090_dt_ids),
401*4882a593Smuzhiyun },
402*4882a593Smuzhiyun .probe_new = pv88090_i2c_probe,
403*4882a593Smuzhiyun .id_table = pv88090_i2c_id,
404*4882a593Smuzhiyun };
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun module_i2c_driver(pv88090_regulator_driver);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun MODULE_AUTHOR("James Ban <James.Ban.opensource@diasemi.com>");
409*4882a593Smuzhiyun MODULE_DESCRIPTION("Regulator device driver for Powerventure PV88090");
410*4882a593Smuzhiyun MODULE_LICENSE("GPL");
411