1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // pv88080-regulator.c - Regulator device driver for PV88080
4*4882a593Smuzhiyun // Copyright (C) 2016 Powerventure Semiconductor Ltd.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/err.h>
7*4882a593Smuzhiyun #include <linux/i2c.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/regulator/driver.h>
13*4882a593Smuzhiyun #include <linux/regulator/machine.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
18*4882a593Smuzhiyun #include "pv88080-regulator.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define PV88080_MAX_REGULATORS 4
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* PV88080 REGULATOR IDs */
23*4882a593Smuzhiyun enum {
24*4882a593Smuzhiyun /* BUCKs */
25*4882a593Smuzhiyun PV88080_ID_BUCK1,
26*4882a593Smuzhiyun PV88080_ID_BUCK2,
27*4882a593Smuzhiyun PV88080_ID_BUCK3,
28*4882a593Smuzhiyun PV88080_ID_HVBUCK,
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun enum pv88080_types {
32*4882a593Smuzhiyun TYPE_PV88080_AA,
33*4882a593Smuzhiyun TYPE_PV88080_BA,
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct pv88080_regulator {
37*4882a593Smuzhiyun struct regulator_desc desc;
38*4882a593Smuzhiyun unsigned int mode_reg;
39*4882a593Smuzhiyun unsigned int conf2;
40*4882a593Smuzhiyun unsigned int conf5;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct pv88080 {
44*4882a593Smuzhiyun struct device *dev;
45*4882a593Smuzhiyun struct regmap *regmap;
46*4882a593Smuzhiyun struct regulator_dev *rdev[PV88080_MAX_REGULATORS];
47*4882a593Smuzhiyun unsigned long type;
48*4882a593Smuzhiyun const struct pv88080_compatible_regmap *regmap_config;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun struct pv88080_buck_voltage {
52*4882a593Smuzhiyun int min_uV;
53*4882a593Smuzhiyun int max_uV;
54*4882a593Smuzhiyun int uV_step;
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct pv88080_buck_regmap {
58*4882a593Smuzhiyun /* REGS */
59*4882a593Smuzhiyun int buck_enable_reg;
60*4882a593Smuzhiyun int buck_vsel_reg;
61*4882a593Smuzhiyun int buck_mode_reg;
62*4882a593Smuzhiyun int buck_limit_reg;
63*4882a593Smuzhiyun int buck_vdac_range_reg;
64*4882a593Smuzhiyun int buck_vrange_gain_reg;
65*4882a593Smuzhiyun /* MASKS */
66*4882a593Smuzhiyun int buck_enable_mask;
67*4882a593Smuzhiyun int buck_vsel_mask;
68*4882a593Smuzhiyun int buck_limit_mask;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct pv88080_compatible_regmap {
72*4882a593Smuzhiyun /* BUCK1, 2, 3 */
73*4882a593Smuzhiyun struct pv88080_buck_regmap buck_regmap[PV88080_MAX_REGULATORS-1];
74*4882a593Smuzhiyun /* HVBUCK */
75*4882a593Smuzhiyun int hvbuck_enable_reg;
76*4882a593Smuzhiyun int hvbuck_vsel_reg;
77*4882a593Smuzhiyun int hvbuck_enable_mask;
78*4882a593Smuzhiyun int hvbuck_vsel_mask;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct regmap_config pv88080_regmap_config = {
82*4882a593Smuzhiyun .reg_bits = 8,
83*4882a593Smuzhiyun .val_bits = 8,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* Current limits array (in uA) for BUCK1, BUCK2, BUCK3.
87*4882a593Smuzhiyun * Entry indexes corresponds to register values.
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static const unsigned int pv88080_buck1_limits[] = {
91*4882a593Smuzhiyun 3230000, 5130000, 6960000, 8790000
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static const unsigned int pv88080_buck23_limits[] = {
95*4882a593Smuzhiyun 1496000, 2393000, 3291000, 4189000
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static const struct pv88080_buck_voltage pv88080_buck_vol[2] = {
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun .min_uV = 600000,
101*4882a593Smuzhiyun .max_uV = 1393750,
102*4882a593Smuzhiyun .uV_step = 6250,
103*4882a593Smuzhiyun },
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun .min_uV = 1400000,
106*4882a593Smuzhiyun .max_uV = 2193750,
107*4882a593Smuzhiyun .uV_step = 6250,
108*4882a593Smuzhiyun },
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun static const struct pv88080_compatible_regmap pv88080_aa_regs = {
112*4882a593Smuzhiyun /* BUCK1 */
113*4882a593Smuzhiyun .buck_regmap[0] = {
114*4882a593Smuzhiyun .buck_enable_reg = PV88080AA_REG_BUCK1_CONF0,
115*4882a593Smuzhiyun .buck_vsel_reg = PV88080AA_REG_BUCK1_CONF0,
116*4882a593Smuzhiyun .buck_mode_reg = PV88080AA_REG_BUCK1_CONF1,
117*4882a593Smuzhiyun .buck_limit_reg = PV88080AA_REG_BUCK1_CONF1,
118*4882a593Smuzhiyun .buck_vdac_range_reg = PV88080AA_REG_BUCK1_CONF2,
119*4882a593Smuzhiyun .buck_vrange_gain_reg = PV88080AA_REG_BUCK1_CONF5,
120*4882a593Smuzhiyun .buck_enable_mask = PV88080_BUCK1_EN,
121*4882a593Smuzhiyun .buck_vsel_mask = PV88080_VBUCK1_MASK,
122*4882a593Smuzhiyun .buck_limit_mask = PV88080_BUCK1_ILIM_MASK,
123*4882a593Smuzhiyun },
124*4882a593Smuzhiyun /* BUCK2 */
125*4882a593Smuzhiyun .buck_regmap[1] = {
126*4882a593Smuzhiyun .buck_enable_reg = PV88080AA_REG_BUCK2_CONF0,
127*4882a593Smuzhiyun .buck_vsel_reg = PV88080AA_REG_BUCK2_CONF0,
128*4882a593Smuzhiyun .buck_mode_reg = PV88080AA_REG_BUCK2_CONF1,
129*4882a593Smuzhiyun .buck_limit_reg = PV88080AA_REG_BUCK2_CONF1,
130*4882a593Smuzhiyun .buck_vdac_range_reg = PV88080AA_REG_BUCK2_CONF2,
131*4882a593Smuzhiyun .buck_vrange_gain_reg = PV88080AA_REG_BUCK2_CONF5,
132*4882a593Smuzhiyun .buck_enable_mask = PV88080_BUCK2_EN,
133*4882a593Smuzhiyun .buck_vsel_mask = PV88080_VBUCK2_MASK,
134*4882a593Smuzhiyun .buck_limit_mask = PV88080_BUCK2_ILIM_MASK,
135*4882a593Smuzhiyun },
136*4882a593Smuzhiyun /* BUCK3 */
137*4882a593Smuzhiyun .buck_regmap[2] = {
138*4882a593Smuzhiyun .buck_enable_reg = PV88080AA_REG_BUCK3_CONF0,
139*4882a593Smuzhiyun .buck_vsel_reg = PV88080AA_REG_BUCK3_CONF0,
140*4882a593Smuzhiyun .buck_mode_reg = PV88080AA_REG_BUCK3_CONF1,
141*4882a593Smuzhiyun .buck_limit_reg = PV88080AA_REG_BUCK3_CONF1,
142*4882a593Smuzhiyun .buck_vdac_range_reg = PV88080AA_REG_BUCK3_CONF2,
143*4882a593Smuzhiyun .buck_vrange_gain_reg = PV88080AA_REG_BUCK3_CONF5,
144*4882a593Smuzhiyun .buck_enable_mask = PV88080_BUCK3_EN,
145*4882a593Smuzhiyun .buck_vsel_mask = PV88080_VBUCK3_MASK,
146*4882a593Smuzhiyun .buck_limit_mask = PV88080_BUCK3_ILIM_MASK,
147*4882a593Smuzhiyun },
148*4882a593Smuzhiyun /* HVBUCK */
149*4882a593Smuzhiyun .hvbuck_enable_reg = PV88080AA_REG_HVBUCK_CONF2,
150*4882a593Smuzhiyun .hvbuck_vsel_reg = PV88080AA_REG_HVBUCK_CONF1,
151*4882a593Smuzhiyun .hvbuck_enable_mask = PV88080_HVBUCK_EN,
152*4882a593Smuzhiyun .hvbuck_vsel_mask = PV88080_VHVBUCK_MASK,
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun static const struct pv88080_compatible_regmap pv88080_ba_regs = {
156*4882a593Smuzhiyun /* BUCK1 */
157*4882a593Smuzhiyun .buck_regmap[0] = {
158*4882a593Smuzhiyun .buck_enable_reg = PV88080BA_REG_BUCK1_CONF0,
159*4882a593Smuzhiyun .buck_vsel_reg = PV88080BA_REG_BUCK1_CONF0,
160*4882a593Smuzhiyun .buck_mode_reg = PV88080BA_REG_BUCK1_CONF1,
161*4882a593Smuzhiyun .buck_limit_reg = PV88080BA_REG_BUCK1_CONF1,
162*4882a593Smuzhiyun .buck_vdac_range_reg = PV88080BA_REG_BUCK1_CONF2,
163*4882a593Smuzhiyun .buck_vrange_gain_reg = PV88080BA_REG_BUCK1_CONF5,
164*4882a593Smuzhiyun .buck_enable_mask = PV88080_BUCK1_EN,
165*4882a593Smuzhiyun .buck_vsel_mask = PV88080_VBUCK1_MASK,
166*4882a593Smuzhiyun .buck_limit_mask = PV88080_BUCK1_ILIM_MASK,
167*4882a593Smuzhiyun },
168*4882a593Smuzhiyun /* BUCK2 */
169*4882a593Smuzhiyun .buck_regmap[1] = {
170*4882a593Smuzhiyun .buck_enable_reg = PV88080BA_REG_BUCK2_CONF0,
171*4882a593Smuzhiyun .buck_vsel_reg = PV88080BA_REG_BUCK2_CONF0,
172*4882a593Smuzhiyun .buck_mode_reg = PV88080BA_REG_BUCK2_CONF1,
173*4882a593Smuzhiyun .buck_limit_reg = PV88080BA_REG_BUCK2_CONF1,
174*4882a593Smuzhiyun .buck_vdac_range_reg = PV88080BA_REG_BUCK2_CONF2,
175*4882a593Smuzhiyun .buck_vrange_gain_reg = PV88080BA_REG_BUCK2_CONF5,
176*4882a593Smuzhiyun .buck_enable_mask = PV88080_BUCK2_EN,
177*4882a593Smuzhiyun .buck_vsel_mask = PV88080_VBUCK2_MASK,
178*4882a593Smuzhiyun .buck_limit_mask = PV88080_BUCK2_ILIM_MASK,
179*4882a593Smuzhiyun },
180*4882a593Smuzhiyun /* BUCK3 */
181*4882a593Smuzhiyun .buck_regmap[2] = {
182*4882a593Smuzhiyun .buck_enable_reg = PV88080BA_REG_BUCK3_CONF0,
183*4882a593Smuzhiyun .buck_vsel_reg = PV88080BA_REG_BUCK3_CONF0,
184*4882a593Smuzhiyun .buck_mode_reg = PV88080BA_REG_BUCK3_CONF1,
185*4882a593Smuzhiyun .buck_limit_reg = PV88080BA_REG_BUCK3_CONF1,
186*4882a593Smuzhiyun .buck_vdac_range_reg = PV88080BA_REG_BUCK3_CONF2,
187*4882a593Smuzhiyun .buck_vrange_gain_reg = PV88080BA_REG_BUCK3_CONF5,
188*4882a593Smuzhiyun .buck_enable_mask = PV88080_BUCK3_EN,
189*4882a593Smuzhiyun .buck_vsel_mask = PV88080_VBUCK3_MASK,
190*4882a593Smuzhiyun .buck_limit_mask = PV88080_BUCK3_ILIM_MASK,
191*4882a593Smuzhiyun },
192*4882a593Smuzhiyun /* HVBUCK */
193*4882a593Smuzhiyun .hvbuck_enable_reg = PV88080BA_REG_HVBUCK_CONF2,
194*4882a593Smuzhiyun .hvbuck_vsel_reg = PV88080BA_REG_HVBUCK_CONF1,
195*4882a593Smuzhiyun .hvbuck_enable_mask = PV88080_HVBUCK_EN,
196*4882a593Smuzhiyun .hvbuck_vsel_mask = PV88080_VHVBUCK_MASK,
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun #ifdef CONFIG_OF
200*4882a593Smuzhiyun static const struct of_device_id pv88080_dt_ids[] = {
201*4882a593Smuzhiyun { .compatible = "pvs,pv88080", .data = (void *)TYPE_PV88080_AA },
202*4882a593Smuzhiyun { .compatible = "pvs,pv88080-aa", .data = (void *)TYPE_PV88080_AA },
203*4882a593Smuzhiyun { .compatible = "pvs,pv88080-ba", .data = (void *)TYPE_PV88080_BA },
204*4882a593Smuzhiyun {},
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, pv88080_dt_ids);
207*4882a593Smuzhiyun #endif
208*4882a593Smuzhiyun
pv88080_buck_get_mode(struct regulator_dev * rdev)209*4882a593Smuzhiyun static unsigned int pv88080_buck_get_mode(struct regulator_dev *rdev)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun struct pv88080_regulator *info = rdev_get_drvdata(rdev);
212*4882a593Smuzhiyun unsigned int data;
213*4882a593Smuzhiyun int ret, mode = 0;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, info->mode_reg, &data);
216*4882a593Smuzhiyun if (ret < 0)
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun switch (data & PV88080_BUCK1_MODE_MASK) {
220*4882a593Smuzhiyun case PV88080_BUCK_MODE_SYNC:
221*4882a593Smuzhiyun mode = REGULATOR_MODE_FAST;
222*4882a593Smuzhiyun break;
223*4882a593Smuzhiyun case PV88080_BUCK_MODE_AUTO:
224*4882a593Smuzhiyun mode = REGULATOR_MODE_NORMAL;
225*4882a593Smuzhiyun break;
226*4882a593Smuzhiyun case PV88080_BUCK_MODE_SLEEP:
227*4882a593Smuzhiyun mode = REGULATOR_MODE_STANDBY;
228*4882a593Smuzhiyun break;
229*4882a593Smuzhiyun default:
230*4882a593Smuzhiyun return -EINVAL;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun return mode;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
pv88080_buck_set_mode(struct regulator_dev * rdev,unsigned int mode)236*4882a593Smuzhiyun static int pv88080_buck_set_mode(struct regulator_dev *rdev,
237*4882a593Smuzhiyun unsigned int mode)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun struct pv88080_regulator *info = rdev_get_drvdata(rdev);
240*4882a593Smuzhiyun int val = 0;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun switch (mode) {
243*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
244*4882a593Smuzhiyun val = PV88080_BUCK_MODE_SYNC;
245*4882a593Smuzhiyun break;
246*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
247*4882a593Smuzhiyun val = PV88080_BUCK_MODE_AUTO;
248*4882a593Smuzhiyun break;
249*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
250*4882a593Smuzhiyun val = PV88080_BUCK_MODE_SLEEP;
251*4882a593Smuzhiyun break;
252*4882a593Smuzhiyun default:
253*4882a593Smuzhiyun return -EINVAL;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, info->mode_reg,
257*4882a593Smuzhiyun PV88080_BUCK1_MODE_MASK, val);
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun static const struct regulator_ops pv88080_buck_ops = {
261*4882a593Smuzhiyun .get_mode = pv88080_buck_get_mode,
262*4882a593Smuzhiyun .set_mode = pv88080_buck_set_mode,
263*4882a593Smuzhiyun .enable = regulator_enable_regmap,
264*4882a593Smuzhiyun .disable = regulator_disable_regmap,
265*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
266*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
267*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
268*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
269*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
270*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun static const struct regulator_ops pv88080_hvbuck_ops = {
274*4882a593Smuzhiyun .enable = regulator_enable_regmap,
275*4882a593Smuzhiyun .disable = regulator_disable_regmap,
276*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
277*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
278*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
279*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun #define PV88080_BUCK(chip, regl_name, min, step, max, limits_array) \
283*4882a593Smuzhiyun {\
284*4882a593Smuzhiyun .desc = {\
285*4882a593Smuzhiyun .id = chip##_ID_##regl_name,\
286*4882a593Smuzhiyun .name = __stringify(chip##_##regl_name),\
287*4882a593Smuzhiyun .of_match = of_match_ptr(#regl_name),\
288*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),\
289*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,\
290*4882a593Smuzhiyun .owner = THIS_MODULE,\
291*4882a593Smuzhiyun .ops = &pv88080_buck_ops,\
292*4882a593Smuzhiyun .min_uV = min, \
293*4882a593Smuzhiyun .uV_step = step, \
294*4882a593Smuzhiyun .n_voltages = ((max) - (min))/(step) + 1, \
295*4882a593Smuzhiyun .curr_table = limits_array, \
296*4882a593Smuzhiyun .n_current_limits = ARRAY_SIZE(limits_array), \
297*4882a593Smuzhiyun },\
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun #define PV88080_HVBUCK(chip, regl_name, min, step, max) \
301*4882a593Smuzhiyun {\
302*4882a593Smuzhiyun .desc = {\
303*4882a593Smuzhiyun .id = chip##_ID_##regl_name,\
304*4882a593Smuzhiyun .name = __stringify(chip##_##regl_name),\
305*4882a593Smuzhiyun .of_match = of_match_ptr(#regl_name),\
306*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),\
307*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,\
308*4882a593Smuzhiyun .owner = THIS_MODULE,\
309*4882a593Smuzhiyun .ops = &pv88080_hvbuck_ops,\
310*4882a593Smuzhiyun .min_uV = min, \
311*4882a593Smuzhiyun .uV_step = step, \
312*4882a593Smuzhiyun .n_voltages = ((max) - (min))/(step) + 1, \
313*4882a593Smuzhiyun },\
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun static struct pv88080_regulator pv88080_regulator_info[] = {
317*4882a593Smuzhiyun PV88080_BUCK(PV88080, BUCK1, 600000, 6250, 1393750,
318*4882a593Smuzhiyun pv88080_buck1_limits),
319*4882a593Smuzhiyun PV88080_BUCK(PV88080, BUCK2, 600000, 6250, 1393750,
320*4882a593Smuzhiyun pv88080_buck23_limits),
321*4882a593Smuzhiyun PV88080_BUCK(PV88080, BUCK3, 600000, 6250, 1393750,
322*4882a593Smuzhiyun pv88080_buck23_limits),
323*4882a593Smuzhiyun PV88080_HVBUCK(PV88080, HVBUCK, 0, 5000, 1275000),
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun
pv88080_irq_handler(int irq,void * data)326*4882a593Smuzhiyun static irqreturn_t pv88080_irq_handler(int irq, void *data)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun struct pv88080 *chip = data;
329*4882a593Smuzhiyun int i, reg_val, err, ret = IRQ_NONE;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun err = regmap_read(chip->regmap, PV88080_REG_EVENT_A, ®_val);
332*4882a593Smuzhiyun if (err < 0)
333*4882a593Smuzhiyun goto error_i2c;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (reg_val & PV88080_E_VDD_FLT) {
336*4882a593Smuzhiyun for (i = 0; i < PV88080_MAX_REGULATORS; i++) {
337*4882a593Smuzhiyun if (chip->rdev[i] != NULL)
338*4882a593Smuzhiyun regulator_notifier_call_chain(chip->rdev[i],
339*4882a593Smuzhiyun REGULATOR_EVENT_UNDER_VOLTAGE,
340*4882a593Smuzhiyun NULL);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun err = regmap_write(chip->regmap, PV88080_REG_EVENT_A,
344*4882a593Smuzhiyun PV88080_E_VDD_FLT);
345*4882a593Smuzhiyun if (err < 0)
346*4882a593Smuzhiyun goto error_i2c;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun ret = IRQ_HANDLED;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun if (reg_val & PV88080_E_OVER_TEMP) {
352*4882a593Smuzhiyun for (i = 0; i < PV88080_MAX_REGULATORS; i++) {
353*4882a593Smuzhiyun if (chip->rdev[i] != NULL)
354*4882a593Smuzhiyun regulator_notifier_call_chain(chip->rdev[i],
355*4882a593Smuzhiyun REGULATOR_EVENT_OVER_TEMP,
356*4882a593Smuzhiyun NULL);
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun err = regmap_write(chip->regmap, PV88080_REG_EVENT_A,
360*4882a593Smuzhiyun PV88080_E_OVER_TEMP);
361*4882a593Smuzhiyun if (err < 0)
362*4882a593Smuzhiyun goto error_i2c;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun ret = IRQ_HANDLED;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun return ret;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun error_i2c:
370*4882a593Smuzhiyun dev_err(chip->dev, "I2C error : %d\n", err);
371*4882a593Smuzhiyun return IRQ_NONE;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /*
375*4882a593Smuzhiyun * I2C driver interface functions
376*4882a593Smuzhiyun */
pv88080_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)377*4882a593Smuzhiyun static int pv88080_i2c_probe(struct i2c_client *i2c,
378*4882a593Smuzhiyun const struct i2c_device_id *id)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun struct regulator_init_data *init_data = dev_get_platdata(&i2c->dev);
381*4882a593Smuzhiyun struct pv88080 *chip;
382*4882a593Smuzhiyun const struct pv88080_compatible_regmap *regmap_config;
383*4882a593Smuzhiyun const struct of_device_id *match;
384*4882a593Smuzhiyun struct regulator_config config = { };
385*4882a593Smuzhiyun int i, error, ret;
386*4882a593Smuzhiyun unsigned int conf2, conf5;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun chip = devm_kzalloc(&i2c->dev, sizeof(struct pv88080), GFP_KERNEL);
389*4882a593Smuzhiyun if (!chip)
390*4882a593Smuzhiyun return -ENOMEM;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun chip->dev = &i2c->dev;
393*4882a593Smuzhiyun chip->regmap = devm_regmap_init_i2c(i2c, &pv88080_regmap_config);
394*4882a593Smuzhiyun if (IS_ERR(chip->regmap)) {
395*4882a593Smuzhiyun error = PTR_ERR(chip->regmap);
396*4882a593Smuzhiyun dev_err(chip->dev, "Failed to allocate register map: %d\n",
397*4882a593Smuzhiyun error);
398*4882a593Smuzhiyun return error;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun if (i2c->dev.of_node) {
402*4882a593Smuzhiyun match = of_match_node(pv88080_dt_ids, i2c->dev.of_node);
403*4882a593Smuzhiyun if (!match) {
404*4882a593Smuzhiyun dev_err(chip->dev, "Failed to get of_match_node\n");
405*4882a593Smuzhiyun return -EINVAL;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun chip->type = (unsigned long)match->data;
408*4882a593Smuzhiyun } else {
409*4882a593Smuzhiyun chip->type = id->driver_data;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun i2c_set_clientdata(i2c, chip);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun if (i2c->irq != 0) {
415*4882a593Smuzhiyun ret = regmap_write(chip->regmap, PV88080_REG_MASK_A, 0xFF);
416*4882a593Smuzhiyun if (ret < 0) {
417*4882a593Smuzhiyun dev_err(chip->dev,
418*4882a593Smuzhiyun "Failed to mask A reg: %d\n", ret);
419*4882a593Smuzhiyun return ret;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun ret = regmap_write(chip->regmap, PV88080_REG_MASK_B, 0xFF);
422*4882a593Smuzhiyun if (ret < 0) {
423*4882a593Smuzhiyun dev_err(chip->dev,
424*4882a593Smuzhiyun "Failed to mask B reg: %d\n", ret);
425*4882a593Smuzhiyun return ret;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun ret = regmap_write(chip->regmap, PV88080_REG_MASK_C, 0xFF);
428*4882a593Smuzhiyun if (ret < 0) {
429*4882a593Smuzhiyun dev_err(chip->dev,
430*4882a593Smuzhiyun "Failed to mask C reg: %d\n", ret);
431*4882a593Smuzhiyun return ret;
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
435*4882a593Smuzhiyun pv88080_irq_handler,
436*4882a593Smuzhiyun IRQF_TRIGGER_LOW|IRQF_ONESHOT,
437*4882a593Smuzhiyun "pv88080", chip);
438*4882a593Smuzhiyun if (ret != 0) {
439*4882a593Smuzhiyun dev_err(chip->dev, "Failed to request IRQ: %d\n",
440*4882a593Smuzhiyun i2c->irq);
441*4882a593Smuzhiyun return ret;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun ret = regmap_update_bits(chip->regmap, PV88080_REG_MASK_A,
445*4882a593Smuzhiyun PV88080_M_VDD_FLT | PV88080_M_OVER_TEMP, 0);
446*4882a593Smuzhiyun if (ret < 0) {
447*4882a593Smuzhiyun dev_err(chip->dev,
448*4882a593Smuzhiyun "Failed to update mask reg: %d\n", ret);
449*4882a593Smuzhiyun return ret;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun } else {
452*4882a593Smuzhiyun dev_warn(chip->dev, "No IRQ configured\n");
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun switch (chip->type) {
456*4882a593Smuzhiyun case TYPE_PV88080_AA:
457*4882a593Smuzhiyun chip->regmap_config = &pv88080_aa_regs;
458*4882a593Smuzhiyun break;
459*4882a593Smuzhiyun case TYPE_PV88080_BA:
460*4882a593Smuzhiyun chip->regmap_config = &pv88080_ba_regs;
461*4882a593Smuzhiyun break;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun regmap_config = chip->regmap_config;
465*4882a593Smuzhiyun config.dev = chip->dev;
466*4882a593Smuzhiyun config.regmap = chip->regmap;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun /* Registeration for BUCK1, 2, 3 */
469*4882a593Smuzhiyun for (i = 0; i < PV88080_MAX_REGULATORS-1; i++) {
470*4882a593Smuzhiyun if (init_data)
471*4882a593Smuzhiyun config.init_data = &init_data[i];
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun pv88080_regulator_info[i].desc.csel_reg
474*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_limit_reg;
475*4882a593Smuzhiyun pv88080_regulator_info[i].desc.csel_mask
476*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_limit_mask;
477*4882a593Smuzhiyun pv88080_regulator_info[i].mode_reg
478*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_mode_reg;
479*4882a593Smuzhiyun pv88080_regulator_info[i].conf2
480*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_vdac_range_reg;
481*4882a593Smuzhiyun pv88080_regulator_info[i].conf5
482*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_vrange_gain_reg;
483*4882a593Smuzhiyun pv88080_regulator_info[i].desc.enable_reg
484*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_enable_reg;
485*4882a593Smuzhiyun pv88080_regulator_info[i].desc.enable_mask
486*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_enable_mask;
487*4882a593Smuzhiyun pv88080_regulator_info[i].desc.vsel_reg
488*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_vsel_reg;
489*4882a593Smuzhiyun pv88080_regulator_info[i].desc.vsel_mask
490*4882a593Smuzhiyun = regmap_config->buck_regmap[i].buck_vsel_mask;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun ret = regmap_read(chip->regmap,
493*4882a593Smuzhiyun pv88080_regulator_info[i].conf2, &conf2);
494*4882a593Smuzhiyun if (ret < 0)
495*4882a593Smuzhiyun return ret;
496*4882a593Smuzhiyun conf2 = ((conf2 >> PV88080_BUCK_VDAC_RANGE_SHIFT) &
497*4882a593Smuzhiyun PV88080_BUCK_VDAC_RANGE_MASK);
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun ret = regmap_read(chip->regmap,
500*4882a593Smuzhiyun pv88080_regulator_info[i].conf5, &conf5);
501*4882a593Smuzhiyun if (ret < 0)
502*4882a593Smuzhiyun return ret;
503*4882a593Smuzhiyun conf5 = ((conf5 >> PV88080_BUCK_VRANGE_GAIN_SHIFT) &
504*4882a593Smuzhiyun PV88080_BUCK_VRANGE_GAIN_MASK);
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun pv88080_regulator_info[i].desc.min_uV =
507*4882a593Smuzhiyun pv88080_buck_vol[conf2].min_uV * (conf5+1);
508*4882a593Smuzhiyun pv88080_regulator_info[i].desc.uV_step =
509*4882a593Smuzhiyun pv88080_buck_vol[conf2].uV_step * (conf5+1);
510*4882a593Smuzhiyun pv88080_regulator_info[i].desc.n_voltages =
511*4882a593Smuzhiyun ((pv88080_buck_vol[conf2].max_uV * (conf5+1))
512*4882a593Smuzhiyun - (pv88080_regulator_info[i].desc.min_uV))
513*4882a593Smuzhiyun /(pv88080_regulator_info[i].desc.uV_step) + 1;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun config.driver_data = (void *)&pv88080_regulator_info[i];
516*4882a593Smuzhiyun chip->rdev[i] = devm_regulator_register(chip->dev,
517*4882a593Smuzhiyun &pv88080_regulator_info[i].desc, &config);
518*4882a593Smuzhiyun if (IS_ERR(chip->rdev[i])) {
519*4882a593Smuzhiyun dev_err(chip->dev,
520*4882a593Smuzhiyun "Failed to register PV88080 regulator\n");
521*4882a593Smuzhiyun return PTR_ERR(chip->rdev[i]);
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun pv88080_regulator_info[PV88080_ID_HVBUCK].desc.enable_reg
526*4882a593Smuzhiyun = regmap_config->hvbuck_enable_reg;
527*4882a593Smuzhiyun pv88080_regulator_info[PV88080_ID_HVBUCK].desc.enable_mask
528*4882a593Smuzhiyun = regmap_config->hvbuck_enable_mask;
529*4882a593Smuzhiyun pv88080_regulator_info[PV88080_ID_HVBUCK].desc.vsel_reg
530*4882a593Smuzhiyun = regmap_config->hvbuck_vsel_reg;
531*4882a593Smuzhiyun pv88080_regulator_info[PV88080_ID_HVBUCK].desc.vsel_mask
532*4882a593Smuzhiyun = regmap_config->hvbuck_vsel_mask;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* Registeration for HVBUCK */
535*4882a593Smuzhiyun if (init_data)
536*4882a593Smuzhiyun config.init_data = &init_data[PV88080_ID_HVBUCK];
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun config.driver_data = (void *)&pv88080_regulator_info[PV88080_ID_HVBUCK];
539*4882a593Smuzhiyun chip->rdev[PV88080_ID_HVBUCK] = devm_regulator_register(chip->dev,
540*4882a593Smuzhiyun &pv88080_regulator_info[PV88080_ID_HVBUCK].desc, &config);
541*4882a593Smuzhiyun if (IS_ERR(chip->rdev[PV88080_ID_HVBUCK])) {
542*4882a593Smuzhiyun dev_err(chip->dev, "Failed to register PV88080 regulator\n");
543*4882a593Smuzhiyun return PTR_ERR(chip->rdev[PV88080_ID_HVBUCK]);
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun return 0;
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun static const struct i2c_device_id pv88080_i2c_id[] = {
550*4882a593Smuzhiyun { "pv88080", TYPE_PV88080_AA },
551*4882a593Smuzhiyun { "pv88080-aa", TYPE_PV88080_AA },
552*4882a593Smuzhiyun { "pv88080-ba", TYPE_PV88080_BA },
553*4882a593Smuzhiyun {},
554*4882a593Smuzhiyun };
555*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, pv88080_i2c_id);
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun static struct i2c_driver pv88080_regulator_driver = {
558*4882a593Smuzhiyun .driver = {
559*4882a593Smuzhiyun .name = "pv88080",
560*4882a593Smuzhiyun .of_match_table = of_match_ptr(pv88080_dt_ids),
561*4882a593Smuzhiyun },
562*4882a593Smuzhiyun .probe = pv88080_i2c_probe,
563*4882a593Smuzhiyun .id_table = pv88080_i2c_id,
564*4882a593Smuzhiyun };
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun module_i2c_driver(pv88080_regulator_driver);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun MODULE_AUTHOR("James Ban <James.Ban.opensource@diasemi.com>");
569*4882a593Smuzhiyun MODULE_DESCRIPTION("Regulator device driver for Powerventure PV88080");
570*4882a593Smuzhiyun MODULE_LICENSE("GPL");
571