1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * pv88060-regulator.h - Regulator definitions for PV88060 4*4882a593Smuzhiyun * Copyright (C) 2015 Powerventure Semiconductor Ltd. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __PV88060_REGISTERS_H__ 8*4882a593Smuzhiyun #define __PV88060_REGISTERS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* System Control and Event Registers */ 11*4882a593Smuzhiyun #define PV88060_REG_EVENT_A 0x04 12*4882a593Smuzhiyun #define PV88060_REG_MASK_A 0x08 13*4882a593Smuzhiyun #define PV88060_REG_MASK_B 0x09 14*4882a593Smuzhiyun #define PV88060_REG_MASK_C 0x0A 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Regulator Registers */ 17*4882a593Smuzhiyun #define PV88060_REG_BUCK1_CONF0 0x1B 18*4882a593Smuzhiyun #define PV88060_REG_BUCK1_CONF1 0x1C 19*4882a593Smuzhiyun #define PV88060_REG_LDO1_CONF 0x1D 20*4882a593Smuzhiyun #define PV88060_REG_LDO2_CONF 0x1E 21*4882a593Smuzhiyun #define PV88060_REG_LDO3_CONF 0x1F 22*4882a593Smuzhiyun #define PV88060_REG_LDO4_CONF 0x20 23*4882a593Smuzhiyun #define PV88060_REG_LDO5_CONF 0x21 24*4882a593Smuzhiyun #define PV88060_REG_LDO6_CONF 0x22 25*4882a593Smuzhiyun #define PV88060_REG_LDO7_CONF 0x23 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define PV88060_REG_SW1_CONF 0x3B 28*4882a593Smuzhiyun #define PV88060_REG_SW2_CONF 0x3C 29*4882a593Smuzhiyun #define PV88060_REG_SW3_CONF 0x3D 30*4882a593Smuzhiyun #define PV88060_REG_SW4_CONF 0x3E 31*4882a593Smuzhiyun #define PV88060_REG_SW5_CONF 0x3F 32*4882a593Smuzhiyun #define PV88060_REG_SW6_CONF 0x40 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* PV88060_REG_EVENT_A (addr=0x04) */ 35*4882a593Smuzhiyun #define PV88060_E_VDD_FLT 0x01 36*4882a593Smuzhiyun #define PV88060_E_OVER_TEMP 0x02 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* PV88060_REG_MASK_A (addr=0x08) */ 39*4882a593Smuzhiyun #define PV88060_M_VDD_FLT 0x01 40*4882a593Smuzhiyun #define PV88060_M_OVER_TEMP 0x02 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* PV88060_REG_BUCK1_CONF0 (addr=0x1B) */ 43*4882a593Smuzhiyun #define PV88060_BUCK_EN 0x80 44*4882a593Smuzhiyun #define PV88060_VBUCK_MASK 0x7F 45*4882a593Smuzhiyun /* PV88060_REG_LDO1/2/3/4/5/6/7_CONT */ 46*4882a593Smuzhiyun #define PV88060_LDO_EN 0x40 47*4882a593Smuzhiyun #define PV88060_VLDO_MASK 0x3F 48*4882a593Smuzhiyun /* PV88060_REG_SW1/2/3/4/5_CONF */ 49*4882a593Smuzhiyun #define PV88060_SW_EN 0x80 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* PV88060_REG_BUCK1_CONF1 (addr=0x1C) */ 52*4882a593Smuzhiyun #define PV88060_BUCK_ILIM_SHIFT 2 53*4882a593Smuzhiyun #define PV88060_BUCK_ILIM_MASK 0x0C 54*4882a593Smuzhiyun #define PV88060_BUCK_MODE_SHIFT 0 55*4882a593Smuzhiyun #define PV88060_BUCK_MODE_MASK 0x03 56*4882a593Smuzhiyun #define PV88060_BUCK_MODE_SLEEP 0x00 57*4882a593Smuzhiyun #define PV88060_BUCK_MODE_AUTO 0x01 58*4882a593Smuzhiyun #define PV88060_BUCK_MODE_SYNC 0x02 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* __PV88060_REGISTERS_H__ */ 61