1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for Regulator part of Palmas PMIC Chips
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2011-2013 Texas Instruments Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Graeme Gregory <gg@slimlogic.co.uk>
8*4882a593Smuzhiyun * Author: Ian Lartey <ian@slimlogic.co.uk>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/regulator/driver.h>
17*4882a593Smuzhiyun #include <linux/regulator/machine.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/regmap.h>
20*4882a593Smuzhiyun #include <linux/mfd/palmas.h>
21*4882a593Smuzhiyun #include <linux/of.h>
22*4882a593Smuzhiyun #include <linux/of_platform.h>
23*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static const struct linear_range smps_low_ranges[] = {
26*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
27*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
28*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000),
29*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0),
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static const struct linear_range smps_high_ranges[] = {
33*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
34*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0),
35*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000),
36*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static struct palmas_regs_info palmas_generic_regs_info[] = {
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun .name = "SMPS12",
42*4882a593Smuzhiyun .sname = "smps1-in",
43*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS12_VOLTAGE,
44*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS12_CTRL,
45*4882a593Smuzhiyun .tstep_addr = PALMAS_SMPS12_TSTEP,
46*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
47*4882a593Smuzhiyun },
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun .name = "SMPS123",
50*4882a593Smuzhiyun .sname = "smps1-in",
51*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS12_VOLTAGE,
52*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS12_CTRL,
53*4882a593Smuzhiyun .tstep_addr = PALMAS_SMPS12_TSTEP,
54*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun .name = "SMPS3",
58*4882a593Smuzhiyun .sname = "smps3-in",
59*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS3_VOLTAGE,
60*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS3_CTRL,
61*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
62*4882a593Smuzhiyun },
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun .name = "SMPS45",
65*4882a593Smuzhiyun .sname = "smps4-in",
66*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS45_VOLTAGE,
67*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS45_CTRL,
68*4882a593Smuzhiyun .tstep_addr = PALMAS_SMPS45_TSTEP,
69*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun .name = "SMPS457",
73*4882a593Smuzhiyun .sname = "smps4-in",
74*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS45_VOLTAGE,
75*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS45_CTRL,
76*4882a593Smuzhiyun .tstep_addr = PALMAS_SMPS45_TSTEP,
77*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
78*4882a593Smuzhiyun },
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun .name = "SMPS6",
81*4882a593Smuzhiyun .sname = "smps6-in",
82*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS6_VOLTAGE,
83*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS6_CTRL,
84*4882a593Smuzhiyun .tstep_addr = PALMAS_SMPS6_TSTEP,
85*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
86*4882a593Smuzhiyun },
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun .name = "SMPS7",
89*4882a593Smuzhiyun .sname = "smps7-in",
90*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS7_VOLTAGE,
91*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS7_CTRL,
92*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun .name = "SMPS8",
96*4882a593Smuzhiyun .sname = "smps8-in",
97*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS8_VOLTAGE,
98*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS8_CTRL,
99*4882a593Smuzhiyun .tstep_addr = PALMAS_SMPS8_TSTEP,
100*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
101*4882a593Smuzhiyun },
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun .name = "SMPS9",
104*4882a593Smuzhiyun .sname = "smps9-in",
105*4882a593Smuzhiyun .vsel_addr = PALMAS_SMPS9_VOLTAGE,
106*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS9_CTRL,
107*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
108*4882a593Smuzhiyun },
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun .name = "SMPS10_OUT2",
111*4882a593Smuzhiyun .sname = "smps10-in",
112*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS10_CTRL,
113*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun .name = "SMPS10_OUT1",
117*4882a593Smuzhiyun .sname = "smps10-out2",
118*4882a593Smuzhiyun .ctrl_addr = PALMAS_SMPS10_CTRL,
119*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
120*4882a593Smuzhiyun },
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun .name = "LDO1",
123*4882a593Smuzhiyun .sname = "ldo1-in",
124*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO1_VOLTAGE,
125*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO1_CTRL,
126*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
127*4882a593Smuzhiyun },
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun .name = "LDO2",
130*4882a593Smuzhiyun .sname = "ldo2-in",
131*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO2_VOLTAGE,
132*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO2_CTRL,
133*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
134*4882a593Smuzhiyun },
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun .name = "LDO3",
137*4882a593Smuzhiyun .sname = "ldo3-in",
138*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO3_VOLTAGE,
139*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO3_CTRL,
140*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
141*4882a593Smuzhiyun },
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun .name = "LDO4",
144*4882a593Smuzhiyun .sname = "ldo4-in",
145*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO4_VOLTAGE,
146*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO4_CTRL,
147*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
148*4882a593Smuzhiyun },
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun .name = "LDO5",
151*4882a593Smuzhiyun .sname = "ldo5-in",
152*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO5_VOLTAGE,
153*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO5_CTRL,
154*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
155*4882a593Smuzhiyun },
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun .name = "LDO6",
158*4882a593Smuzhiyun .sname = "ldo6-in",
159*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO6_VOLTAGE,
160*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO6_CTRL,
161*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
162*4882a593Smuzhiyun },
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun .name = "LDO7",
165*4882a593Smuzhiyun .sname = "ldo7-in",
166*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO7_VOLTAGE,
167*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO7_CTRL,
168*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
169*4882a593Smuzhiyun },
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun .name = "LDO8",
172*4882a593Smuzhiyun .sname = "ldo8-in",
173*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO8_VOLTAGE,
174*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO8_CTRL,
175*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
176*4882a593Smuzhiyun },
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun .name = "LDO9",
179*4882a593Smuzhiyun .sname = "ldo9-in",
180*4882a593Smuzhiyun .vsel_addr = PALMAS_LDO9_VOLTAGE,
181*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDO9_CTRL,
182*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
183*4882a593Smuzhiyun },
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun .name = "LDOLN",
186*4882a593Smuzhiyun .sname = "ldoln-in",
187*4882a593Smuzhiyun .vsel_addr = PALMAS_LDOLN_VOLTAGE,
188*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDOLN_CTRL,
189*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
190*4882a593Smuzhiyun },
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun .name = "LDOUSB",
193*4882a593Smuzhiyun .sname = "ldousb-in",
194*4882a593Smuzhiyun .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
195*4882a593Smuzhiyun .ctrl_addr = PALMAS_LDOUSB_CTRL,
196*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
197*4882a593Smuzhiyun },
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun .name = "REGEN1",
200*4882a593Smuzhiyun .ctrl_addr = PALMAS_REGEN1_CTRL,
201*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
202*4882a593Smuzhiyun },
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun .name = "REGEN2",
205*4882a593Smuzhiyun .ctrl_addr = PALMAS_REGEN2_CTRL,
206*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
207*4882a593Smuzhiyun },
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun .name = "REGEN3",
210*4882a593Smuzhiyun .ctrl_addr = PALMAS_REGEN3_CTRL,
211*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
212*4882a593Smuzhiyun },
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun .name = "SYSEN1",
215*4882a593Smuzhiyun .ctrl_addr = PALMAS_SYSEN1_CTRL,
216*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
217*4882a593Smuzhiyun },
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun .name = "SYSEN2",
220*4882a593Smuzhiyun .ctrl_addr = PALMAS_SYSEN2_CTRL,
221*4882a593Smuzhiyun .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
222*4882a593Smuzhiyun },
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static struct palmas_regs_info tps65917_regs_info[] = {
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun .name = "SMPS1",
228*4882a593Smuzhiyun .sname = "smps1-in",
229*4882a593Smuzhiyun .vsel_addr = TPS65917_SMPS1_VOLTAGE,
230*4882a593Smuzhiyun .ctrl_addr = TPS65917_SMPS1_CTRL,
231*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
232*4882a593Smuzhiyun },
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun .name = "SMPS2",
235*4882a593Smuzhiyun .sname = "smps2-in",
236*4882a593Smuzhiyun .vsel_addr = TPS65917_SMPS2_VOLTAGE,
237*4882a593Smuzhiyun .ctrl_addr = TPS65917_SMPS2_CTRL,
238*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
239*4882a593Smuzhiyun },
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun .name = "SMPS3",
242*4882a593Smuzhiyun .sname = "smps3-in",
243*4882a593Smuzhiyun .vsel_addr = TPS65917_SMPS3_VOLTAGE,
244*4882a593Smuzhiyun .ctrl_addr = TPS65917_SMPS3_CTRL,
245*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
246*4882a593Smuzhiyun },
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun .name = "SMPS4",
249*4882a593Smuzhiyun .sname = "smps4-in",
250*4882a593Smuzhiyun .vsel_addr = TPS65917_SMPS4_VOLTAGE,
251*4882a593Smuzhiyun .ctrl_addr = TPS65917_SMPS4_CTRL,
252*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
253*4882a593Smuzhiyun },
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun .name = "SMPS5",
256*4882a593Smuzhiyun .sname = "smps5-in",
257*4882a593Smuzhiyun .vsel_addr = TPS65917_SMPS5_VOLTAGE,
258*4882a593Smuzhiyun .ctrl_addr = TPS65917_SMPS5_CTRL,
259*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
260*4882a593Smuzhiyun },
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun .name = "SMPS12",
263*4882a593Smuzhiyun .sname = "smps1-in",
264*4882a593Smuzhiyun .vsel_addr = TPS65917_SMPS1_VOLTAGE,
265*4882a593Smuzhiyun .ctrl_addr = TPS65917_SMPS1_CTRL,
266*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
267*4882a593Smuzhiyun },
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun .name = "LDO1",
270*4882a593Smuzhiyun .sname = "ldo1-in",
271*4882a593Smuzhiyun .vsel_addr = TPS65917_LDO1_VOLTAGE,
272*4882a593Smuzhiyun .ctrl_addr = TPS65917_LDO1_CTRL,
273*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
274*4882a593Smuzhiyun },
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun .name = "LDO2",
277*4882a593Smuzhiyun .sname = "ldo2-in",
278*4882a593Smuzhiyun .vsel_addr = TPS65917_LDO2_VOLTAGE,
279*4882a593Smuzhiyun .ctrl_addr = TPS65917_LDO2_CTRL,
280*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
281*4882a593Smuzhiyun },
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun .name = "LDO3",
284*4882a593Smuzhiyun .sname = "ldo3-in",
285*4882a593Smuzhiyun .vsel_addr = TPS65917_LDO3_VOLTAGE,
286*4882a593Smuzhiyun .ctrl_addr = TPS65917_LDO3_CTRL,
287*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
288*4882a593Smuzhiyun },
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun .name = "LDO4",
291*4882a593Smuzhiyun .sname = "ldo4-in",
292*4882a593Smuzhiyun .vsel_addr = TPS65917_LDO4_VOLTAGE,
293*4882a593Smuzhiyun .ctrl_addr = TPS65917_LDO4_CTRL,
294*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
295*4882a593Smuzhiyun },
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun .name = "LDO5",
298*4882a593Smuzhiyun .sname = "ldo5-in",
299*4882a593Smuzhiyun .vsel_addr = TPS65917_LDO5_VOLTAGE,
300*4882a593Smuzhiyun .ctrl_addr = TPS65917_LDO5_CTRL,
301*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
302*4882a593Smuzhiyun },
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun .name = "REGEN1",
305*4882a593Smuzhiyun .ctrl_addr = TPS65917_REGEN1_CTRL,
306*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
307*4882a593Smuzhiyun },
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun .name = "REGEN2",
310*4882a593Smuzhiyun .ctrl_addr = TPS65917_REGEN2_CTRL,
311*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
312*4882a593Smuzhiyun },
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun .name = "REGEN3",
315*4882a593Smuzhiyun .ctrl_addr = TPS65917_REGEN3_CTRL,
316*4882a593Smuzhiyun .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
317*4882a593Smuzhiyun },
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun #define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
321*4882a593Smuzhiyun [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
322*4882a593Smuzhiyun .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
323*4882a593Smuzhiyun .reg_offset = _offset, \
324*4882a593Smuzhiyun .bit_pos = _pos, \
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
328*4882a593Smuzhiyun EXTERNAL_REQUESTOR(REGEN1, 0, 0),
329*4882a593Smuzhiyun EXTERNAL_REQUESTOR(REGEN2, 0, 1),
330*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
331*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
332*4882a593Smuzhiyun EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
333*4882a593Smuzhiyun EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
334*4882a593Smuzhiyun EXTERNAL_REQUESTOR(REGEN3, 0, 6),
335*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SMPS12, 1, 0),
336*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SMPS3, 1, 1),
337*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SMPS45, 1, 2),
338*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SMPS6, 1, 3),
339*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SMPS7, 1, 4),
340*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SMPS8, 1, 5),
341*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SMPS9, 1, 6),
342*4882a593Smuzhiyun EXTERNAL_REQUESTOR(SMPS10, 1, 7),
343*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO1, 2, 0),
344*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO2, 2, 1),
345*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO3, 2, 2),
346*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO4, 2, 3),
347*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO5, 2, 4),
348*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO6, 2, 5),
349*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO7, 2, 6),
350*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO8, 2, 7),
351*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDO9, 3, 0),
352*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDOLN, 3, 1),
353*4882a593Smuzhiyun EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun #define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
357*4882a593Smuzhiyun [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
358*4882a593Smuzhiyun .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
359*4882a593Smuzhiyun .reg_offset = _offset, \
360*4882a593Smuzhiyun .bit_pos = _pos, \
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
364*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
365*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
366*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
367*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
368*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
369*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
370*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
371*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
372*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(SMPS12, 1, 5),
373*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
374*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
375*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
376*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
377*4882a593Smuzhiyun EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
378*4882a593Smuzhiyun };
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun static const unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun #define SMPS_CTRL_MODE_OFF 0x00
383*4882a593Smuzhiyun #define SMPS_CTRL_MODE_ON 0x01
384*4882a593Smuzhiyun #define SMPS_CTRL_MODE_ECO 0x02
385*4882a593Smuzhiyun #define SMPS_CTRL_MODE_PWM 0x03
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun #define PALMAS_SMPS_NUM_VOLTAGES 122
388*4882a593Smuzhiyun #define PALMAS_SMPS10_NUM_VOLTAGES 2
389*4882a593Smuzhiyun #define PALMAS_LDO_NUM_VOLTAGES 50
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun #define SMPS10_VSEL (1<<3)
392*4882a593Smuzhiyun #define SMPS10_BOOST_EN (1<<2)
393*4882a593Smuzhiyun #define SMPS10_BYPASS_EN (1<<1)
394*4882a593Smuzhiyun #define SMPS10_SWITCH_EN (1<<0)
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun #define REGULATOR_SLAVE 0
397*4882a593Smuzhiyun
palmas_smps_read(struct palmas * palmas,unsigned int reg,unsigned int * dest)398*4882a593Smuzhiyun static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
399*4882a593Smuzhiyun unsigned int *dest)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun unsigned int addr;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
palmas_smps_write(struct palmas * palmas,unsigned int reg,unsigned int value)408*4882a593Smuzhiyun static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
409*4882a593Smuzhiyun unsigned int value)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun unsigned int addr;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
palmas_ldo_read(struct palmas * palmas,unsigned int reg,unsigned int * dest)418*4882a593Smuzhiyun static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
419*4882a593Smuzhiyun unsigned int *dest)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun unsigned int addr;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
palmas_ldo_write(struct palmas * palmas,unsigned int reg,unsigned int value)428*4882a593Smuzhiyun static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
429*4882a593Smuzhiyun unsigned int value)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun unsigned int addr;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
palmas_set_mode_smps(struct regulator_dev * dev,unsigned int mode)438*4882a593Smuzhiyun static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun int id = rdev_get_id(dev);
441*4882a593Smuzhiyun int ret;
442*4882a593Smuzhiyun struct palmas_pmic *pmic = rdev_get_drvdata(dev);
443*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
444*4882a593Smuzhiyun struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
445*4882a593Smuzhiyun unsigned int reg;
446*4882a593Smuzhiyun bool rail_enable = true;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun ret = palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, ®);
449*4882a593Smuzhiyun if (ret)
450*4882a593Smuzhiyun return ret;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (reg == SMPS_CTRL_MODE_OFF)
455*4882a593Smuzhiyun rail_enable = false;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun switch (mode) {
458*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
459*4882a593Smuzhiyun reg |= SMPS_CTRL_MODE_ON;
460*4882a593Smuzhiyun break;
461*4882a593Smuzhiyun case REGULATOR_MODE_IDLE:
462*4882a593Smuzhiyun reg |= SMPS_CTRL_MODE_ECO;
463*4882a593Smuzhiyun break;
464*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
465*4882a593Smuzhiyun reg |= SMPS_CTRL_MODE_PWM;
466*4882a593Smuzhiyun break;
467*4882a593Smuzhiyun default:
468*4882a593Smuzhiyun return -EINVAL;
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
472*4882a593Smuzhiyun if (rail_enable)
473*4882a593Smuzhiyun palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg);
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun /* Switch the enable value to ensure this is used for enable */
476*4882a593Smuzhiyun pmic->desc[id].enable_val = pmic->current_reg_mode[id];
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun return 0;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
palmas_get_mode_smps(struct regulator_dev * dev)481*4882a593Smuzhiyun static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun struct palmas_pmic *pmic = rdev_get_drvdata(dev);
484*4882a593Smuzhiyun int id = rdev_get_id(dev);
485*4882a593Smuzhiyun unsigned int reg;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun switch (reg) {
490*4882a593Smuzhiyun case SMPS_CTRL_MODE_ON:
491*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
492*4882a593Smuzhiyun case SMPS_CTRL_MODE_ECO:
493*4882a593Smuzhiyun return REGULATOR_MODE_IDLE;
494*4882a593Smuzhiyun case SMPS_CTRL_MODE_PWM:
495*4882a593Smuzhiyun return REGULATOR_MODE_FAST;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun return 0;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
palmas_smps_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)501*4882a593Smuzhiyun static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
502*4882a593Smuzhiyun int ramp_delay)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun int id = rdev_get_id(rdev);
505*4882a593Smuzhiyun struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
506*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
507*4882a593Smuzhiyun struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
508*4882a593Smuzhiyun unsigned int reg = 0;
509*4882a593Smuzhiyun int ret;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /* SMPS3 and SMPS7 do not have tstep_addr setting */
512*4882a593Smuzhiyun switch (id) {
513*4882a593Smuzhiyun case PALMAS_REG_SMPS3:
514*4882a593Smuzhiyun case PALMAS_REG_SMPS7:
515*4882a593Smuzhiyun return 0;
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun if (ramp_delay <= 0)
519*4882a593Smuzhiyun reg = 0;
520*4882a593Smuzhiyun else if (ramp_delay <= 2500)
521*4882a593Smuzhiyun reg = 3;
522*4882a593Smuzhiyun else if (ramp_delay <= 5000)
523*4882a593Smuzhiyun reg = 2;
524*4882a593Smuzhiyun else
525*4882a593Smuzhiyun reg = 1;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg);
528*4882a593Smuzhiyun if (ret < 0) {
529*4882a593Smuzhiyun dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
530*4882a593Smuzhiyun return ret;
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
534*4882a593Smuzhiyun return ret;
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun static const struct regulator_ops palmas_ops_smps = {
538*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
539*4882a593Smuzhiyun .enable = regulator_enable_regmap,
540*4882a593Smuzhiyun .disable = regulator_disable_regmap,
541*4882a593Smuzhiyun .set_mode = palmas_set_mode_smps,
542*4882a593Smuzhiyun .get_mode = palmas_get_mode_smps,
543*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
544*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
545*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
546*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
547*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
548*4882a593Smuzhiyun .set_ramp_delay = palmas_smps_set_ramp_delay,
549*4882a593Smuzhiyun };
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun static const struct regulator_ops palmas_ops_ext_control_smps = {
552*4882a593Smuzhiyun .set_mode = palmas_set_mode_smps,
553*4882a593Smuzhiyun .get_mode = palmas_get_mode_smps,
554*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
555*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
556*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
557*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
558*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
559*4882a593Smuzhiyun .set_ramp_delay = palmas_smps_set_ramp_delay,
560*4882a593Smuzhiyun };
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun static const struct regulator_ops palmas_ops_smps10 = {
563*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
564*4882a593Smuzhiyun .enable = regulator_enable_regmap,
565*4882a593Smuzhiyun .disable = regulator_disable_regmap,
566*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
567*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
568*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
569*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
570*4882a593Smuzhiyun .set_bypass = regulator_set_bypass_regmap,
571*4882a593Smuzhiyun .get_bypass = regulator_get_bypass_regmap,
572*4882a593Smuzhiyun };
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun static const struct regulator_ops tps65917_ops_smps = {
575*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
576*4882a593Smuzhiyun .enable = regulator_enable_regmap,
577*4882a593Smuzhiyun .disable = regulator_disable_regmap,
578*4882a593Smuzhiyun .set_mode = palmas_set_mode_smps,
579*4882a593Smuzhiyun .get_mode = palmas_get_mode_smps,
580*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
581*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
582*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
583*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
584*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
585*4882a593Smuzhiyun };
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun static const struct regulator_ops tps65917_ops_ext_control_smps = {
588*4882a593Smuzhiyun .set_mode = palmas_set_mode_smps,
589*4882a593Smuzhiyun .get_mode = palmas_get_mode_smps,
590*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
591*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
592*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
593*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
594*4882a593Smuzhiyun };
595*4882a593Smuzhiyun
palmas_is_enabled_ldo(struct regulator_dev * dev)596*4882a593Smuzhiyun static int palmas_is_enabled_ldo(struct regulator_dev *dev)
597*4882a593Smuzhiyun {
598*4882a593Smuzhiyun int id = rdev_get_id(dev);
599*4882a593Smuzhiyun struct palmas_pmic *pmic = rdev_get_drvdata(dev);
600*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
601*4882a593Smuzhiyun struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
602*4882a593Smuzhiyun unsigned int reg;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, ®);
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun reg &= PALMAS_LDO1_CTRL_STATUS;
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun return !!(reg);
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun static const struct regulator_ops palmas_ops_ldo = {
612*4882a593Smuzhiyun .is_enabled = palmas_is_enabled_ldo,
613*4882a593Smuzhiyun .enable = regulator_enable_regmap,
614*4882a593Smuzhiyun .disable = regulator_disable_regmap,
615*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
616*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
617*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
618*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
619*4882a593Smuzhiyun };
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun static const struct regulator_ops palmas_ops_ldo9 = {
622*4882a593Smuzhiyun .is_enabled = palmas_is_enabled_ldo,
623*4882a593Smuzhiyun .enable = regulator_enable_regmap,
624*4882a593Smuzhiyun .disable = regulator_disable_regmap,
625*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
626*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
627*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
628*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
629*4882a593Smuzhiyun .set_bypass = regulator_set_bypass_regmap,
630*4882a593Smuzhiyun .get_bypass = regulator_get_bypass_regmap,
631*4882a593Smuzhiyun };
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun static const struct regulator_ops palmas_ops_ext_control_ldo = {
634*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
635*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
636*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
637*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
638*4882a593Smuzhiyun };
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun static const struct regulator_ops palmas_ops_extreg = {
641*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
642*4882a593Smuzhiyun .enable = regulator_enable_regmap,
643*4882a593Smuzhiyun .disable = regulator_disable_regmap,
644*4882a593Smuzhiyun };
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun static const struct regulator_ops palmas_ops_ext_control_extreg = {
647*4882a593Smuzhiyun };
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun static const struct regulator_ops tps65917_ops_ldo = {
650*4882a593Smuzhiyun .is_enabled = palmas_is_enabled_ldo,
651*4882a593Smuzhiyun .enable = regulator_enable_regmap,
652*4882a593Smuzhiyun .disable = regulator_disable_regmap,
653*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
654*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
655*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
656*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
657*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
658*4882a593Smuzhiyun };
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun static const struct regulator_ops tps65917_ops_ldo_1_2 = {
661*4882a593Smuzhiyun .is_enabled = palmas_is_enabled_ldo,
662*4882a593Smuzhiyun .enable = regulator_enable_regmap,
663*4882a593Smuzhiyun .disable = regulator_disable_regmap,
664*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
665*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
666*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
667*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
668*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
669*4882a593Smuzhiyun .set_bypass = regulator_set_bypass_regmap,
670*4882a593Smuzhiyun .get_bypass = regulator_get_bypass_regmap,
671*4882a593Smuzhiyun };
672*4882a593Smuzhiyun
palmas_regulator_config_external(struct palmas * palmas,int id,struct palmas_reg_init * reg_init)673*4882a593Smuzhiyun static int palmas_regulator_config_external(struct palmas *palmas, int id,
674*4882a593Smuzhiyun struct palmas_reg_init *reg_init)
675*4882a593Smuzhiyun {
676*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
677*4882a593Smuzhiyun struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
678*4882a593Smuzhiyun int ret;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id,
681*4882a593Smuzhiyun reg_init->roof_floor, true);
682*4882a593Smuzhiyun if (ret < 0)
683*4882a593Smuzhiyun dev_err(palmas->dev,
684*4882a593Smuzhiyun "Ext control config for regulator %d failed %d\n",
685*4882a593Smuzhiyun id, ret);
686*4882a593Smuzhiyun return ret;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun /*
690*4882a593Smuzhiyun * setup the hardware based sleep configuration of the SMPS/LDO regulators
691*4882a593Smuzhiyun * from the platform data. This is different to the software based control
692*4882a593Smuzhiyun * supported by the regulator framework as it is controlled by toggling
693*4882a593Smuzhiyun * pins on the PMIC such as PREQ, SYSEN, ...
694*4882a593Smuzhiyun */
palmas_smps_init(struct palmas * palmas,int id,struct palmas_reg_init * reg_init)695*4882a593Smuzhiyun static int palmas_smps_init(struct palmas *palmas, int id,
696*4882a593Smuzhiyun struct palmas_reg_init *reg_init)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun unsigned int reg;
699*4882a593Smuzhiyun int ret;
700*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
701*4882a593Smuzhiyun struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
702*4882a593Smuzhiyun unsigned int addr = rinfo->ctrl_addr;
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun ret = palmas_smps_read(palmas, addr, ®);
705*4882a593Smuzhiyun if (ret)
706*4882a593Smuzhiyun return ret;
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun switch (id) {
709*4882a593Smuzhiyun case PALMAS_REG_SMPS10_OUT1:
710*4882a593Smuzhiyun case PALMAS_REG_SMPS10_OUT2:
711*4882a593Smuzhiyun reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
712*4882a593Smuzhiyun if (reg_init->mode_sleep)
713*4882a593Smuzhiyun reg |= reg_init->mode_sleep <<
714*4882a593Smuzhiyun PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
715*4882a593Smuzhiyun break;
716*4882a593Smuzhiyun default:
717*4882a593Smuzhiyun if (reg_init->warm_reset)
718*4882a593Smuzhiyun reg |= PALMAS_SMPS12_CTRL_WR_S;
719*4882a593Smuzhiyun else
720*4882a593Smuzhiyun reg &= ~PALMAS_SMPS12_CTRL_WR_S;
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun if (reg_init->roof_floor)
723*4882a593Smuzhiyun reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
724*4882a593Smuzhiyun else
725*4882a593Smuzhiyun reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
728*4882a593Smuzhiyun if (reg_init->mode_sleep)
729*4882a593Smuzhiyun reg |= reg_init->mode_sleep <<
730*4882a593Smuzhiyun PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
731*4882a593Smuzhiyun }
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun ret = palmas_smps_write(palmas, addr, reg);
734*4882a593Smuzhiyun if (ret)
735*4882a593Smuzhiyun return ret;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun if (rinfo->vsel_addr && reg_init->vsel) {
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun reg = reg_init->vsel;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg);
742*4882a593Smuzhiyun if (ret)
743*4882a593Smuzhiyun return ret;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
747*4882a593Smuzhiyun (id != PALMAS_REG_SMPS10_OUT2)) {
748*4882a593Smuzhiyun /* Enable externally controlled regulator */
749*4882a593Smuzhiyun ret = palmas_smps_read(palmas, addr, ®);
750*4882a593Smuzhiyun if (ret < 0)
751*4882a593Smuzhiyun return ret;
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
754*4882a593Smuzhiyun reg |= SMPS_CTRL_MODE_ON;
755*4882a593Smuzhiyun ret = palmas_smps_write(palmas, addr, reg);
756*4882a593Smuzhiyun if (ret < 0)
757*4882a593Smuzhiyun return ret;
758*4882a593Smuzhiyun }
759*4882a593Smuzhiyun return palmas_regulator_config_external(palmas, id, reg_init);
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun return 0;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun
palmas_ldo_init(struct palmas * palmas,int id,struct palmas_reg_init * reg_init)764*4882a593Smuzhiyun static int palmas_ldo_init(struct palmas *palmas, int id,
765*4882a593Smuzhiyun struct palmas_reg_init *reg_init)
766*4882a593Smuzhiyun {
767*4882a593Smuzhiyun unsigned int reg;
768*4882a593Smuzhiyun unsigned int addr;
769*4882a593Smuzhiyun int ret;
770*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
771*4882a593Smuzhiyun struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun addr = rinfo->ctrl_addr;
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun ret = palmas_ldo_read(palmas, addr, ®);
776*4882a593Smuzhiyun if (ret)
777*4882a593Smuzhiyun return ret;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun if (reg_init->warm_reset)
780*4882a593Smuzhiyun reg |= PALMAS_LDO1_CTRL_WR_S;
781*4882a593Smuzhiyun else
782*4882a593Smuzhiyun reg &= ~PALMAS_LDO1_CTRL_WR_S;
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun if (reg_init->mode_sleep)
785*4882a593Smuzhiyun reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
786*4882a593Smuzhiyun else
787*4882a593Smuzhiyun reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun ret = palmas_ldo_write(palmas, addr, reg);
790*4882a593Smuzhiyun if (ret)
791*4882a593Smuzhiyun return ret;
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun if (reg_init->roof_floor) {
794*4882a593Smuzhiyun /* Enable externally controlled regulator */
795*4882a593Smuzhiyun ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
796*4882a593Smuzhiyun addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
797*4882a593Smuzhiyun PALMAS_LDO1_CTRL_MODE_ACTIVE);
798*4882a593Smuzhiyun if (ret < 0) {
799*4882a593Smuzhiyun dev_err(palmas->dev,
800*4882a593Smuzhiyun "LDO Register 0x%02x update failed %d\n",
801*4882a593Smuzhiyun addr, ret);
802*4882a593Smuzhiyun return ret;
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun return palmas_regulator_config_external(palmas, id, reg_init);
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun return 0;
807*4882a593Smuzhiyun }
808*4882a593Smuzhiyun
palmas_extreg_init(struct palmas * palmas,int id,struct palmas_reg_init * reg_init)809*4882a593Smuzhiyun static int palmas_extreg_init(struct palmas *palmas, int id,
810*4882a593Smuzhiyun struct palmas_reg_init *reg_init)
811*4882a593Smuzhiyun {
812*4882a593Smuzhiyun unsigned int addr;
813*4882a593Smuzhiyun int ret;
814*4882a593Smuzhiyun unsigned int val = 0;
815*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
816*4882a593Smuzhiyun struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun addr = rinfo->ctrl_addr;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun if (reg_init->mode_sleep)
821*4882a593Smuzhiyun val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
824*4882a593Smuzhiyun addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
825*4882a593Smuzhiyun if (ret < 0) {
826*4882a593Smuzhiyun dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
827*4882a593Smuzhiyun addr, ret);
828*4882a593Smuzhiyun return ret;
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun if (reg_init->roof_floor) {
832*4882a593Smuzhiyun /* Enable externally controlled regulator */
833*4882a593Smuzhiyun ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
834*4882a593Smuzhiyun addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
835*4882a593Smuzhiyun PALMAS_REGEN1_CTRL_MODE_ACTIVE);
836*4882a593Smuzhiyun if (ret < 0) {
837*4882a593Smuzhiyun dev_err(palmas->dev,
838*4882a593Smuzhiyun "Resource Register 0x%02x update failed %d\n",
839*4882a593Smuzhiyun addr, ret);
840*4882a593Smuzhiyun return ret;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun return palmas_regulator_config_external(palmas, id, reg_init);
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun return 0;
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun
palmas_enable_ldo8_track(struct palmas * palmas)847*4882a593Smuzhiyun static void palmas_enable_ldo8_track(struct palmas *palmas)
848*4882a593Smuzhiyun {
849*4882a593Smuzhiyun unsigned int reg;
850*4882a593Smuzhiyun unsigned int addr;
851*4882a593Smuzhiyun int ret;
852*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
853*4882a593Smuzhiyun struct palmas_regs_info *rinfo;
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8];
856*4882a593Smuzhiyun addr = rinfo->ctrl_addr;
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun ret = palmas_ldo_read(palmas, addr, ®);
859*4882a593Smuzhiyun if (ret) {
860*4882a593Smuzhiyun dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
861*4882a593Smuzhiyun return;
862*4882a593Smuzhiyun }
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
865*4882a593Smuzhiyun ret = palmas_ldo_write(palmas, addr, reg);
866*4882a593Smuzhiyun if (ret < 0) {
867*4882a593Smuzhiyun dev_err(palmas->dev, "Error in enabling tracking mode\n");
868*4882a593Smuzhiyun return;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun /*
871*4882a593Smuzhiyun * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
872*4882a593Smuzhiyun * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
873*4882a593Smuzhiyun * and can be set from 0.45 to 1.65 V.
874*4882a593Smuzhiyun */
875*4882a593Smuzhiyun addr = rinfo->vsel_addr;
876*4882a593Smuzhiyun ret = palmas_ldo_read(palmas, addr, ®);
877*4882a593Smuzhiyun if (ret) {
878*4882a593Smuzhiyun dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
879*4882a593Smuzhiyun return;
880*4882a593Smuzhiyun }
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
883*4882a593Smuzhiyun ret = palmas_ldo_write(palmas, addr, reg);
884*4882a593Smuzhiyun if (ret < 0)
885*4882a593Smuzhiyun dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun return;
888*4882a593Smuzhiyun }
889*4882a593Smuzhiyun
palmas_ldo_registration(struct palmas_pmic * pmic,struct palmas_pmic_driver_data * ddata,struct palmas_pmic_platform_data * pdata,const char * pdev_name,struct regulator_config config)890*4882a593Smuzhiyun static int palmas_ldo_registration(struct palmas_pmic *pmic,
891*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata,
892*4882a593Smuzhiyun struct palmas_pmic_platform_data *pdata,
893*4882a593Smuzhiyun const char *pdev_name,
894*4882a593Smuzhiyun struct regulator_config config)
895*4882a593Smuzhiyun {
896*4882a593Smuzhiyun int id, ret;
897*4882a593Smuzhiyun struct regulator_dev *rdev;
898*4882a593Smuzhiyun struct palmas_reg_init *reg_init;
899*4882a593Smuzhiyun struct palmas_regs_info *rinfo;
900*4882a593Smuzhiyun struct regulator_desc *desc;
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
903*4882a593Smuzhiyun if (pdata && pdata->reg_init[id])
904*4882a593Smuzhiyun reg_init = pdata->reg_init[id];
905*4882a593Smuzhiyun else
906*4882a593Smuzhiyun reg_init = NULL;
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun rinfo = &ddata->palmas_regs_info[id];
909*4882a593Smuzhiyun /* Miss out regulators which are not available due
910*4882a593Smuzhiyun * to alternate functions.
911*4882a593Smuzhiyun */
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun /* Register the regulators */
914*4882a593Smuzhiyun desc = &pmic->desc[id];
915*4882a593Smuzhiyun desc->name = rinfo->name;
916*4882a593Smuzhiyun desc->id = id;
917*4882a593Smuzhiyun desc->type = REGULATOR_VOLTAGE;
918*4882a593Smuzhiyun desc->owner = THIS_MODULE;
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun if (id < PALMAS_REG_REGEN1) {
921*4882a593Smuzhiyun desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
922*4882a593Smuzhiyun if (reg_init && reg_init->roof_floor)
923*4882a593Smuzhiyun desc->ops = &palmas_ops_ext_control_ldo;
924*4882a593Smuzhiyun else
925*4882a593Smuzhiyun desc->ops = &palmas_ops_ldo;
926*4882a593Smuzhiyun desc->min_uV = 900000;
927*4882a593Smuzhiyun desc->uV_step = 50000;
928*4882a593Smuzhiyun desc->linear_min_sel = 1;
929*4882a593Smuzhiyun desc->enable_time = 500;
930*4882a593Smuzhiyun desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
931*4882a593Smuzhiyun rinfo->vsel_addr);
932*4882a593Smuzhiyun desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
933*4882a593Smuzhiyun desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
934*4882a593Smuzhiyun rinfo->ctrl_addr);
935*4882a593Smuzhiyun desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun /* Check if LDO8 is in tracking mode or not */
938*4882a593Smuzhiyun if (pdata && (id == PALMAS_REG_LDO8) &&
939*4882a593Smuzhiyun pdata->enable_ldo8_tracking) {
940*4882a593Smuzhiyun palmas_enable_ldo8_track(pmic->palmas);
941*4882a593Smuzhiyun desc->min_uV = 450000;
942*4882a593Smuzhiyun desc->uV_step = 25000;
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun /* LOD6 in vibrator mode will have enable time 2000us */
946*4882a593Smuzhiyun if (pdata && pdata->ldo6_vibrator &&
947*4882a593Smuzhiyun (id == PALMAS_REG_LDO6))
948*4882a593Smuzhiyun desc->enable_time = 2000;
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun if (id == PALMAS_REG_LDO9) {
951*4882a593Smuzhiyun desc->ops = &palmas_ops_ldo9;
952*4882a593Smuzhiyun desc->bypass_reg = desc->enable_reg;
953*4882a593Smuzhiyun desc->bypass_val_on =
954*4882a593Smuzhiyun PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
955*4882a593Smuzhiyun desc->bypass_mask =
956*4882a593Smuzhiyun PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun } else {
959*4882a593Smuzhiyun if (!ddata->has_regen3 && id == PALMAS_REG_REGEN3)
960*4882a593Smuzhiyun continue;
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun desc->n_voltages = 1;
963*4882a593Smuzhiyun if (reg_init && reg_init->roof_floor)
964*4882a593Smuzhiyun desc->ops = &palmas_ops_ext_control_extreg;
965*4882a593Smuzhiyun else
966*4882a593Smuzhiyun desc->ops = &palmas_ops_extreg;
967*4882a593Smuzhiyun desc->enable_reg =
968*4882a593Smuzhiyun PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
969*4882a593Smuzhiyun rinfo->ctrl_addr);
970*4882a593Smuzhiyun desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun if (pdata)
974*4882a593Smuzhiyun config.init_data = pdata->reg_data[id];
975*4882a593Smuzhiyun else
976*4882a593Smuzhiyun config.init_data = NULL;
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun desc->supply_name = rinfo->sname;
979*4882a593Smuzhiyun config.of_node = ddata->palmas_matches[id].of_node;
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun rdev = devm_regulator_register(pmic->dev, desc, &config);
982*4882a593Smuzhiyun if (IS_ERR(rdev)) {
983*4882a593Smuzhiyun dev_err(pmic->dev,
984*4882a593Smuzhiyun "failed to register %s regulator\n",
985*4882a593Smuzhiyun pdev_name);
986*4882a593Smuzhiyun return PTR_ERR(rdev);
987*4882a593Smuzhiyun }
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun /* Initialise sleep/init values from platform data */
990*4882a593Smuzhiyun if (pdata) {
991*4882a593Smuzhiyun reg_init = pdata->reg_init[id];
992*4882a593Smuzhiyun if (reg_init) {
993*4882a593Smuzhiyun if (id <= ddata->ldo_end)
994*4882a593Smuzhiyun ret = palmas_ldo_init(pmic->palmas, id,
995*4882a593Smuzhiyun reg_init);
996*4882a593Smuzhiyun else
997*4882a593Smuzhiyun ret = palmas_extreg_init(pmic->palmas,
998*4882a593Smuzhiyun id, reg_init);
999*4882a593Smuzhiyun if (ret)
1000*4882a593Smuzhiyun return ret;
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun }
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun return 0;
1006*4882a593Smuzhiyun }
1007*4882a593Smuzhiyun
tps65917_ldo_registration(struct palmas_pmic * pmic,struct palmas_pmic_driver_data * ddata,struct palmas_pmic_platform_data * pdata,const char * pdev_name,struct regulator_config config)1008*4882a593Smuzhiyun static int tps65917_ldo_registration(struct palmas_pmic *pmic,
1009*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata,
1010*4882a593Smuzhiyun struct palmas_pmic_platform_data *pdata,
1011*4882a593Smuzhiyun const char *pdev_name,
1012*4882a593Smuzhiyun struct regulator_config config)
1013*4882a593Smuzhiyun {
1014*4882a593Smuzhiyun int id, ret;
1015*4882a593Smuzhiyun struct regulator_dev *rdev;
1016*4882a593Smuzhiyun struct palmas_reg_init *reg_init;
1017*4882a593Smuzhiyun struct palmas_regs_info *rinfo;
1018*4882a593Smuzhiyun struct regulator_desc *desc;
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
1021*4882a593Smuzhiyun if (pdata && pdata->reg_init[id])
1022*4882a593Smuzhiyun reg_init = pdata->reg_init[id];
1023*4882a593Smuzhiyun else
1024*4882a593Smuzhiyun reg_init = NULL;
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun /* Miss out regulators which are not available due
1027*4882a593Smuzhiyun * to alternate functions.
1028*4882a593Smuzhiyun */
1029*4882a593Smuzhiyun rinfo = &ddata->palmas_regs_info[id];
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun /* Register the regulators */
1032*4882a593Smuzhiyun desc = &pmic->desc[id];
1033*4882a593Smuzhiyun desc->name = rinfo->name;
1034*4882a593Smuzhiyun desc->id = id;
1035*4882a593Smuzhiyun desc->type = REGULATOR_VOLTAGE;
1036*4882a593Smuzhiyun desc->owner = THIS_MODULE;
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun if (id < TPS65917_REG_REGEN1) {
1039*4882a593Smuzhiyun desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
1040*4882a593Smuzhiyun if (reg_init && reg_init->roof_floor)
1041*4882a593Smuzhiyun desc->ops = &palmas_ops_ext_control_ldo;
1042*4882a593Smuzhiyun else
1043*4882a593Smuzhiyun desc->ops = &tps65917_ops_ldo;
1044*4882a593Smuzhiyun desc->min_uV = 900000;
1045*4882a593Smuzhiyun desc->uV_step = 50000;
1046*4882a593Smuzhiyun desc->linear_min_sel = 1;
1047*4882a593Smuzhiyun desc->enable_time = 500;
1048*4882a593Smuzhiyun desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1049*4882a593Smuzhiyun rinfo->vsel_addr);
1050*4882a593Smuzhiyun desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1051*4882a593Smuzhiyun desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1052*4882a593Smuzhiyun rinfo->ctrl_addr);
1053*4882a593Smuzhiyun desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
1054*4882a593Smuzhiyun /*
1055*4882a593Smuzhiyun * To be confirmed. Discussion on going with PMIC Team.
1056*4882a593Smuzhiyun * It is of the order of ~60mV/uS.
1057*4882a593Smuzhiyun */
1058*4882a593Smuzhiyun desc->ramp_delay = 2500;
1059*4882a593Smuzhiyun if (id == TPS65917_REG_LDO1 ||
1060*4882a593Smuzhiyun id == TPS65917_REG_LDO2) {
1061*4882a593Smuzhiyun desc->ops = &tps65917_ops_ldo_1_2;
1062*4882a593Smuzhiyun desc->bypass_reg = desc->enable_reg;
1063*4882a593Smuzhiyun desc->bypass_val_on =
1064*4882a593Smuzhiyun TPS65917_LDO1_CTRL_BYPASS_EN;
1065*4882a593Smuzhiyun desc->bypass_mask =
1066*4882a593Smuzhiyun TPS65917_LDO1_CTRL_BYPASS_EN;
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun } else {
1069*4882a593Smuzhiyun desc->n_voltages = 1;
1070*4882a593Smuzhiyun if (reg_init && reg_init->roof_floor)
1071*4882a593Smuzhiyun desc->ops = &palmas_ops_ext_control_extreg;
1072*4882a593Smuzhiyun else
1073*4882a593Smuzhiyun desc->ops = &palmas_ops_extreg;
1074*4882a593Smuzhiyun desc->enable_reg =
1075*4882a593Smuzhiyun PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
1076*4882a593Smuzhiyun rinfo->ctrl_addr);
1077*4882a593Smuzhiyun desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun if (pdata)
1081*4882a593Smuzhiyun config.init_data = pdata->reg_data[id];
1082*4882a593Smuzhiyun else
1083*4882a593Smuzhiyun config.init_data = NULL;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun desc->supply_name = rinfo->sname;
1086*4882a593Smuzhiyun config.of_node = ddata->palmas_matches[id].of_node;
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun rdev = devm_regulator_register(pmic->dev, desc, &config);
1089*4882a593Smuzhiyun if (IS_ERR(rdev)) {
1090*4882a593Smuzhiyun dev_err(pmic->dev,
1091*4882a593Smuzhiyun "failed to register %s regulator\n",
1092*4882a593Smuzhiyun pdev_name);
1093*4882a593Smuzhiyun return PTR_ERR(rdev);
1094*4882a593Smuzhiyun }
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun /* Initialise sleep/init values from platform data */
1097*4882a593Smuzhiyun if (pdata) {
1098*4882a593Smuzhiyun reg_init = pdata->reg_init[id];
1099*4882a593Smuzhiyun if (reg_init) {
1100*4882a593Smuzhiyun if (id < TPS65917_REG_REGEN1)
1101*4882a593Smuzhiyun ret = palmas_ldo_init(pmic->palmas,
1102*4882a593Smuzhiyun id, reg_init);
1103*4882a593Smuzhiyun else
1104*4882a593Smuzhiyun ret = palmas_extreg_init(pmic->palmas,
1105*4882a593Smuzhiyun id, reg_init);
1106*4882a593Smuzhiyun if (ret)
1107*4882a593Smuzhiyun return ret;
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun return 0;
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun
palmas_smps_registration(struct palmas_pmic * pmic,struct palmas_pmic_driver_data * ddata,struct palmas_pmic_platform_data * pdata,const char * pdev_name,struct regulator_config config)1115*4882a593Smuzhiyun static int palmas_smps_registration(struct palmas_pmic *pmic,
1116*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata,
1117*4882a593Smuzhiyun struct palmas_pmic_platform_data *pdata,
1118*4882a593Smuzhiyun const char *pdev_name,
1119*4882a593Smuzhiyun struct regulator_config config)
1120*4882a593Smuzhiyun {
1121*4882a593Smuzhiyun int id, ret;
1122*4882a593Smuzhiyun unsigned int addr, reg;
1123*4882a593Smuzhiyun struct regulator_dev *rdev;
1124*4882a593Smuzhiyun struct palmas_reg_init *reg_init;
1125*4882a593Smuzhiyun struct palmas_regs_info *rinfo;
1126*4882a593Smuzhiyun struct regulator_desc *desc;
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
1129*4882a593Smuzhiyun bool ramp_delay_support = false;
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun /*
1132*4882a593Smuzhiyun * Miss out regulators which are not available due
1133*4882a593Smuzhiyun * to slaving configurations.
1134*4882a593Smuzhiyun */
1135*4882a593Smuzhiyun switch (id) {
1136*4882a593Smuzhiyun case PALMAS_REG_SMPS12:
1137*4882a593Smuzhiyun case PALMAS_REG_SMPS3:
1138*4882a593Smuzhiyun if (pmic->smps123)
1139*4882a593Smuzhiyun continue;
1140*4882a593Smuzhiyun if (id == PALMAS_REG_SMPS12)
1141*4882a593Smuzhiyun ramp_delay_support = true;
1142*4882a593Smuzhiyun break;
1143*4882a593Smuzhiyun case PALMAS_REG_SMPS123:
1144*4882a593Smuzhiyun if (!pmic->smps123)
1145*4882a593Smuzhiyun continue;
1146*4882a593Smuzhiyun ramp_delay_support = true;
1147*4882a593Smuzhiyun break;
1148*4882a593Smuzhiyun case PALMAS_REG_SMPS45:
1149*4882a593Smuzhiyun case PALMAS_REG_SMPS7:
1150*4882a593Smuzhiyun if (pmic->smps457)
1151*4882a593Smuzhiyun continue;
1152*4882a593Smuzhiyun if (id == PALMAS_REG_SMPS45)
1153*4882a593Smuzhiyun ramp_delay_support = true;
1154*4882a593Smuzhiyun break;
1155*4882a593Smuzhiyun case PALMAS_REG_SMPS457:
1156*4882a593Smuzhiyun if (!pmic->smps457)
1157*4882a593Smuzhiyun continue;
1158*4882a593Smuzhiyun ramp_delay_support = true;
1159*4882a593Smuzhiyun break;
1160*4882a593Smuzhiyun case PALMAS_REG_SMPS10_OUT1:
1161*4882a593Smuzhiyun case PALMAS_REG_SMPS10_OUT2:
1162*4882a593Smuzhiyun if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
1163*4882a593Smuzhiyun continue;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun rinfo = &ddata->palmas_regs_info[id];
1166*4882a593Smuzhiyun desc = &pmic->desc[id];
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
1169*4882a593Smuzhiyun ramp_delay_support = true;
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun if (ramp_delay_support) {
1172*4882a593Smuzhiyun addr = rinfo->tstep_addr;
1173*4882a593Smuzhiyun ret = palmas_smps_read(pmic->palmas, addr, ®);
1174*4882a593Smuzhiyun if (ret < 0) {
1175*4882a593Smuzhiyun dev_err(pmic->dev,
1176*4882a593Smuzhiyun "reading TSTEP reg failed: %d\n", ret);
1177*4882a593Smuzhiyun return ret;
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3];
1180*4882a593Smuzhiyun pmic->ramp_delay[id] = desc->ramp_delay;
1181*4882a593Smuzhiyun }
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun /* Initialise sleep/init values from platform data */
1184*4882a593Smuzhiyun if (pdata && pdata->reg_init[id]) {
1185*4882a593Smuzhiyun reg_init = pdata->reg_init[id];
1186*4882a593Smuzhiyun ret = palmas_smps_init(pmic->palmas, id, reg_init);
1187*4882a593Smuzhiyun if (ret)
1188*4882a593Smuzhiyun return ret;
1189*4882a593Smuzhiyun } else {
1190*4882a593Smuzhiyun reg_init = NULL;
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun /* Register the regulators */
1194*4882a593Smuzhiyun desc->name = rinfo->name;
1195*4882a593Smuzhiyun desc->id = id;
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun switch (id) {
1198*4882a593Smuzhiyun case PALMAS_REG_SMPS10_OUT1:
1199*4882a593Smuzhiyun case PALMAS_REG_SMPS10_OUT2:
1200*4882a593Smuzhiyun desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
1201*4882a593Smuzhiyun desc->ops = &palmas_ops_smps10;
1202*4882a593Smuzhiyun desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1203*4882a593Smuzhiyun PALMAS_SMPS10_CTRL);
1204*4882a593Smuzhiyun desc->vsel_mask = SMPS10_VSEL;
1205*4882a593Smuzhiyun desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1206*4882a593Smuzhiyun PALMAS_SMPS10_CTRL);
1207*4882a593Smuzhiyun if (id == PALMAS_REG_SMPS10_OUT1)
1208*4882a593Smuzhiyun desc->enable_mask = SMPS10_SWITCH_EN;
1209*4882a593Smuzhiyun else
1210*4882a593Smuzhiyun desc->enable_mask = SMPS10_BOOST_EN;
1211*4882a593Smuzhiyun desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1212*4882a593Smuzhiyun PALMAS_SMPS10_CTRL);
1213*4882a593Smuzhiyun desc->bypass_val_on = SMPS10_BYPASS_EN;
1214*4882a593Smuzhiyun desc->bypass_mask = SMPS10_BYPASS_EN;
1215*4882a593Smuzhiyun desc->min_uV = 3750000;
1216*4882a593Smuzhiyun desc->uV_step = 1250000;
1217*4882a593Smuzhiyun break;
1218*4882a593Smuzhiyun default:
1219*4882a593Smuzhiyun /*
1220*4882a593Smuzhiyun * Read and store the RANGE bit for later use
1221*4882a593Smuzhiyun * This must be done before regulator is probed,
1222*4882a593Smuzhiyun * otherwise we error in probe with unsupportable
1223*4882a593Smuzhiyun * ranges. Read the current smps mode for later use.
1224*4882a593Smuzhiyun */
1225*4882a593Smuzhiyun addr = rinfo->vsel_addr;
1226*4882a593Smuzhiyun desc->n_linear_ranges = 3;
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun ret = palmas_smps_read(pmic->palmas, addr, ®);
1229*4882a593Smuzhiyun if (ret)
1230*4882a593Smuzhiyun return ret;
1231*4882a593Smuzhiyun if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
1232*4882a593Smuzhiyun pmic->range[id] = 1;
1233*4882a593Smuzhiyun if (pmic->range[id])
1234*4882a593Smuzhiyun desc->linear_ranges = smps_high_ranges;
1235*4882a593Smuzhiyun else
1236*4882a593Smuzhiyun desc->linear_ranges = smps_low_ranges;
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun if (reg_init && reg_init->roof_floor)
1239*4882a593Smuzhiyun desc->ops = &palmas_ops_ext_control_smps;
1240*4882a593Smuzhiyun else
1241*4882a593Smuzhiyun desc->ops = &palmas_ops_smps;
1242*4882a593Smuzhiyun desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1243*4882a593Smuzhiyun desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1244*4882a593Smuzhiyun rinfo->vsel_addr);
1245*4882a593Smuzhiyun desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun /* Read the smps mode for later use. */
1248*4882a593Smuzhiyun addr = rinfo->ctrl_addr;
1249*4882a593Smuzhiyun ret = palmas_smps_read(pmic->palmas, addr, ®);
1250*4882a593Smuzhiyun if (ret)
1251*4882a593Smuzhiyun return ret;
1252*4882a593Smuzhiyun pmic->current_reg_mode[id] = reg &
1253*4882a593Smuzhiyun PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1256*4882a593Smuzhiyun rinfo->ctrl_addr);
1257*4882a593Smuzhiyun desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1258*4882a593Smuzhiyun /* set_mode overrides this value */
1259*4882a593Smuzhiyun desc->enable_val = SMPS_CTRL_MODE_ON;
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun desc->type = REGULATOR_VOLTAGE;
1263*4882a593Smuzhiyun desc->owner = THIS_MODULE;
1264*4882a593Smuzhiyun
1265*4882a593Smuzhiyun if (pdata)
1266*4882a593Smuzhiyun config.init_data = pdata->reg_data[id];
1267*4882a593Smuzhiyun else
1268*4882a593Smuzhiyun config.init_data = NULL;
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun desc->supply_name = rinfo->sname;
1271*4882a593Smuzhiyun config.of_node = ddata->palmas_matches[id].of_node;
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun rdev = devm_regulator_register(pmic->dev, desc, &config);
1274*4882a593Smuzhiyun if (IS_ERR(rdev)) {
1275*4882a593Smuzhiyun dev_err(pmic->dev,
1276*4882a593Smuzhiyun "failed to register %s regulator\n",
1277*4882a593Smuzhiyun pdev_name);
1278*4882a593Smuzhiyun return PTR_ERR(rdev);
1279*4882a593Smuzhiyun }
1280*4882a593Smuzhiyun }
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun return 0;
1283*4882a593Smuzhiyun }
1284*4882a593Smuzhiyun
tps65917_smps_registration(struct palmas_pmic * pmic,struct palmas_pmic_driver_data * ddata,struct palmas_pmic_platform_data * pdata,const char * pdev_name,struct regulator_config config)1285*4882a593Smuzhiyun static int tps65917_smps_registration(struct palmas_pmic *pmic,
1286*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata,
1287*4882a593Smuzhiyun struct palmas_pmic_platform_data *pdata,
1288*4882a593Smuzhiyun const char *pdev_name,
1289*4882a593Smuzhiyun struct regulator_config config)
1290*4882a593Smuzhiyun {
1291*4882a593Smuzhiyun int id, ret;
1292*4882a593Smuzhiyun unsigned int addr, reg;
1293*4882a593Smuzhiyun struct regulator_dev *rdev;
1294*4882a593Smuzhiyun struct palmas_reg_init *reg_init;
1295*4882a593Smuzhiyun struct palmas_regs_info *rinfo;
1296*4882a593Smuzhiyun struct regulator_desc *desc;
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
1299*4882a593Smuzhiyun /*
1300*4882a593Smuzhiyun * Miss out regulators which are not available due
1301*4882a593Smuzhiyun * to slaving configurations.
1302*4882a593Smuzhiyun */
1303*4882a593Smuzhiyun desc = &pmic->desc[id];
1304*4882a593Smuzhiyun desc->n_linear_ranges = 3;
1305*4882a593Smuzhiyun if ((id == TPS65917_REG_SMPS2 || id == TPS65917_REG_SMPS1) &&
1306*4882a593Smuzhiyun pmic->smps12)
1307*4882a593Smuzhiyun continue;
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun /* Initialise sleep/init values from platform data */
1310*4882a593Smuzhiyun if (pdata && pdata->reg_init[id]) {
1311*4882a593Smuzhiyun reg_init = pdata->reg_init[id];
1312*4882a593Smuzhiyun ret = palmas_smps_init(pmic->palmas, id, reg_init);
1313*4882a593Smuzhiyun if (ret)
1314*4882a593Smuzhiyun return ret;
1315*4882a593Smuzhiyun } else {
1316*4882a593Smuzhiyun reg_init = NULL;
1317*4882a593Smuzhiyun }
1318*4882a593Smuzhiyun rinfo = &ddata->palmas_regs_info[id];
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun /* Register the regulators */
1321*4882a593Smuzhiyun desc->name = rinfo->name;
1322*4882a593Smuzhiyun desc->id = id;
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun /*
1325*4882a593Smuzhiyun * Read and store the RANGE bit for later use
1326*4882a593Smuzhiyun * This must be done before regulator is probed,
1327*4882a593Smuzhiyun * otherwise we error in probe with unsupportable
1328*4882a593Smuzhiyun * ranges. Read the current smps mode for later use.
1329*4882a593Smuzhiyun */
1330*4882a593Smuzhiyun addr = rinfo->vsel_addr;
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun ret = palmas_smps_read(pmic->palmas, addr, ®);
1333*4882a593Smuzhiyun if (ret)
1334*4882a593Smuzhiyun return ret;
1335*4882a593Smuzhiyun if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
1336*4882a593Smuzhiyun pmic->range[id] = 1;
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun if (pmic->range[id])
1339*4882a593Smuzhiyun desc->linear_ranges = smps_high_ranges;
1340*4882a593Smuzhiyun else
1341*4882a593Smuzhiyun desc->linear_ranges = smps_low_ranges;
1342*4882a593Smuzhiyun
1343*4882a593Smuzhiyun if (reg_init && reg_init->roof_floor)
1344*4882a593Smuzhiyun desc->ops = &tps65917_ops_ext_control_smps;
1345*4882a593Smuzhiyun else
1346*4882a593Smuzhiyun desc->ops = &tps65917_ops_smps;
1347*4882a593Smuzhiyun desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1348*4882a593Smuzhiyun desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1349*4882a593Smuzhiyun rinfo->vsel_addr);
1350*4882a593Smuzhiyun desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
1351*4882a593Smuzhiyun desc->ramp_delay = 2500;
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun /* Read the smps mode for later use. */
1354*4882a593Smuzhiyun addr = rinfo->ctrl_addr;
1355*4882a593Smuzhiyun ret = palmas_smps_read(pmic->palmas, addr, ®);
1356*4882a593Smuzhiyun if (ret)
1357*4882a593Smuzhiyun return ret;
1358*4882a593Smuzhiyun pmic->current_reg_mode[id] = reg &
1359*4882a593Smuzhiyun PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1360*4882a593Smuzhiyun desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1361*4882a593Smuzhiyun rinfo->ctrl_addr);
1362*4882a593Smuzhiyun desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1363*4882a593Smuzhiyun /* set_mode overrides this value */
1364*4882a593Smuzhiyun desc->enable_val = SMPS_CTRL_MODE_ON;
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun desc->type = REGULATOR_VOLTAGE;
1367*4882a593Smuzhiyun desc->owner = THIS_MODULE;
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun if (pdata)
1370*4882a593Smuzhiyun config.init_data = pdata->reg_data[id];
1371*4882a593Smuzhiyun else
1372*4882a593Smuzhiyun config.init_data = NULL;
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun desc->supply_name = rinfo->sname;
1375*4882a593Smuzhiyun config.of_node = ddata->palmas_matches[id].of_node;
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun rdev = devm_regulator_register(pmic->dev, desc, &config);
1378*4882a593Smuzhiyun if (IS_ERR(rdev)) {
1379*4882a593Smuzhiyun dev_err(pmic->dev,
1380*4882a593Smuzhiyun "failed to register %s regulator\n",
1381*4882a593Smuzhiyun pdev_name);
1382*4882a593Smuzhiyun return PTR_ERR(rdev);
1383*4882a593Smuzhiyun }
1384*4882a593Smuzhiyun }
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun return 0;
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun static struct of_regulator_match palmas_matches[] = {
1390*4882a593Smuzhiyun { .name = "smps12", },
1391*4882a593Smuzhiyun { .name = "smps123", },
1392*4882a593Smuzhiyun { .name = "smps3", },
1393*4882a593Smuzhiyun { .name = "smps45", },
1394*4882a593Smuzhiyun { .name = "smps457", },
1395*4882a593Smuzhiyun { .name = "smps6", },
1396*4882a593Smuzhiyun { .name = "smps7", },
1397*4882a593Smuzhiyun { .name = "smps8", },
1398*4882a593Smuzhiyun { .name = "smps9", },
1399*4882a593Smuzhiyun { .name = "smps10_out2", },
1400*4882a593Smuzhiyun { .name = "smps10_out1", },
1401*4882a593Smuzhiyun { .name = "ldo1", },
1402*4882a593Smuzhiyun { .name = "ldo2", },
1403*4882a593Smuzhiyun { .name = "ldo3", },
1404*4882a593Smuzhiyun { .name = "ldo4", },
1405*4882a593Smuzhiyun { .name = "ldo5", },
1406*4882a593Smuzhiyun { .name = "ldo6", },
1407*4882a593Smuzhiyun { .name = "ldo7", },
1408*4882a593Smuzhiyun { .name = "ldo8", },
1409*4882a593Smuzhiyun { .name = "ldo9", },
1410*4882a593Smuzhiyun { .name = "ldoln", },
1411*4882a593Smuzhiyun { .name = "ldousb", },
1412*4882a593Smuzhiyun { .name = "regen1", },
1413*4882a593Smuzhiyun { .name = "regen2", },
1414*4882a593Smuzhiyun { .name = "regen3", },
1415*4882a593Smuzhiyun { .name = "sysen1", },
1416*4882a593Smuzhiyun { .name = "sysen2", },
1417*4882a593Smuzhiyun };
1418*4882a593Smuzhiyun
1419*4882a593Smuzhiyun static struct of_regulator_match tps65917_matches[] = {
1420*4882a593Smuzhiyun { .name = "smps1", },
1421*4882a593Smuzhiyun { .name = "smps2", },
1422*4882a593Smuzhiyun { .name = "smps3", },
1423*4882a593Smuzhiyun { .name = "smps4", },
1424*4882a593Smuzhiyun { .name = "smps5", },
1425*4882a593Smuzhiyun { .name = "smps12",},
1426*4882a593Smuzhiyun { .name = "ldo1", },
1427*4882a593Smuzhiyun { .name = "ldo2", },
1428*4882a593Smuzhiyun { .name = "ldo3", },
1429*4882a593Smuzhiyun { .name = "ldo4", },
1430*4882a593Smuzhiyun { .name = "ldo5", },
1431*4882a593Smuzhiyun { .name = "regen1", },
1432*4882a593Smuzhiyun { .name = "regen2", },
1433*4882a593Smuzhiyun { .name = "regen3", },
1434*4882a593Smuzhiyun { .name = "sysen1", },
1435*4882a593Smuzhiyun { .name = "sysen2", },
1436*4882a593Smuzhiyun };
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun static struct palmas_pmic_driver_data palmas_ddata = {
1439*4882a593Smuzhiyun .smps_start = PALMAS_REG_SMPS12,
1440*4882a593Smuzhiyun .smps_end = PALMAS_REG_SMPS10_OUT1,
1441*4882a593Smuzhiyun .ldo_begin = PALMAS_REG_LDO1,
1442*4882a593Smuzhiyun .ldo_end = PALMAS_REG_LDOUSB,
1443*4882a593Smuzhiyun .max_reg = PALMAS_NUM_REGS,
1444*4882a593Smuzhiyun .has_regen3 = true,
1445*4882a593Smuzhiyun .palmas_regs_info = palmas_generic_regs_info,
1446*4882a593Smuzhiyun .palmas_matches = palmas_matches,
1447*4882a593Smuzhiyun .sleep_req_info = palma_sleep_req_info,
1448*4882a593Smuzhiyun .smps_register = palmas_smps_registration,
1449*4882a593Smuzhiyun .ldo_register = palmas_ldo_registration,
1450*4882a593Smuzhiyun };
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun static struct palmas_pmic_driver_data tps65917_ddata = {
1453*4882a593Smuzhiyun .smps_start = TPS65917_REG_SMPS1,
1454*4882a593Smuzhiyun .smps_end = TPS65917_REG_SMPS12,
1455*4882a593Smuzhiyun .ldo_begin = TPS65917_REG_LDO1,
1456*4882a593Smuzhiyun .ldo_end = TPS65917_REG_LDO5,
1457*4882a593Smuzhiyun .max_reg = TPS65917_NUM_REGS,
1458*4882a593Smuzhiyun .has_regen3 = true,
1459*4882a593Smuzhiyun .palmas_regs_info = tps65917_regs_info,
1460*4882a593Smuzhiyun .palmas_matches = tps65917_matches,
1461*4882a593Smuzhiyun .sleep_req_info = tps65917_sleep_req_info,
1462*4882a593Smuzhiyun .smps_register = tps65917_smps_registration,
1463*4882a593Smuzhiyun .ldo_register = tps65917_ldo_registration,
1464*4882a593Smuzhiyun };
1465*4882a593Smuzhiyun
palmas_dt_to_pdata(struct device * dev,struct device_node * node,struct palmas_pmic_platform_data * pdata,struct palmas_pmic_driver_data * ddata)1466*4882a593Smuzhiyun static int palmas_dt_to_pdata(struct device *dev,
1467*4882a593Smuzhiyun struct device_node *node,
1468*4882a593Smuzhiyun struct palmas_pmic_platform_data *pdata,
1469*4882a593Smuzhiyun struct palmas_pmic_driver_data *ddata)
1470*4882a593Smuzhiyun {
1471*4882a593Smuzhiyun struct device_node *regulators;
1472*4882a593Smuzhiyun u32 prop;
1473*4882a593Smuzhiyun int idx, ret;
1474*4882a593Smuzhiyun
1475*4882a593Smuzhiyun regulators = of_get_child_by_name(node, "regulators");
1476*4882a593Smuzhiyun if (!regulators) {
1477*4882a593Smuzhiyun dev_info(dev, "regulator node not found\n");
1478*4882a593Smuzhiyun return 0;
1479*4882a593Smuzhiyun }
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
1482*4882a593Smuzhiyun ddata->max_reg);
1483*4882a593Smuzhiyun of_node_put(regulators);
1484*4882a593Smuzhiyun if (ret < 0) {
1485*4882a593Smuzhiyun dev_err(dev, "Error parsing regulator init data: %d\n", ret);
1486*4882a593Smuzhiyun return 0;
1487*4882a593Smuzhiyun }
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun for (idx = 0; idx < ddata->max_reg; idx++) {
1490*4882a593Smuzhiyun struct of_regulator_match *match;
1491*4882a593Smuzhiyun struct palmas_reg_init *rinit;
1492*4882a593Smuzhiyun struct device_node *np;
1493*4882a593Smuzhiyun
1494*4882a593Smuzhiyun match = &ddata->palmas_matches[idx];
1495*4882a593Smuzhiyun np = match->of_node;
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun if (!match->init_data || !np)
1498*4882a593Smuzhiyun continue;
1499*4882a593Smuzhiyun
1500*4882a593Smuzhiyun rinit = devm_kzalloc(dev, sizeof(*rinit), GFP_KERNEL);
1501*4882a593Smuzhiyun if (!rinit)
1502*4882a593Smuzhiyun return -ENOMEM;
1503*4882a593Smuzhiyun
1504*4882a593Smuzhiyun pdata->reg_data[idx] = match->init_data;
1505*4882a593Smuzhiyun pdata->reg_init[idx] = rinit;
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun rinit->warm_reset = of_property_read_bool(np, "ti,warm-reset");
1508*4882a593Smuzhiyun ret = of_property_read_u32(np, "ti,roof-floor", &prop);
1509*4882a593Smuzhiyun /* EINVAL: Property not found */
1510*4882a593Smuzhiyun if (ret != -EINVAL) {
1511*4882a593Smuzhiyun int econtrol;
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun /* use default value, when no value is specified */
1514*4882a593Smuzhiyun econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1515*4882a593Smuzhiyun if (!ret) {
1516*4882a593Smuzhiyun switch (prop) {
1517*4882a593Smuzhiyun case 1:
1518*4882a593Smuzhiyun econtrol = PALMAS_EXT_CONTROL_ENABLE1;
1519*4882a593Smuzhiyun break;
1520*4882a593Smuzhiyun case 2:
1521*4882a593Smuzhiyun econtrol = PALMAS_EXT_CONTROL_ENABLE2;
1522*4882a593Smuzhiyun break;
1523*4882a593Smuzhiyun case 3:
1524*4882a593Smuzhiyun econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1525*4882a593Smuzhiyun break;
1526*4882a593Smuzhiyun default:
1527*4882a593Smuzhiyun WARN_ON(1);
1528*4882a593Smuzhiyun dev_warn(dev,
1529*4882a593Smuzhiyun "%s: Invalid roof-floor option: %u\n",
1530*4882a593Smuzhiyun match->name, prop);
1531*4882a593Smuzhiyun break;
1532*4882a593Smuzhiyun }
1533*4882a593Smuzhiyun }
1534*4882a593Smuzhiyun rinit->roof_floor = econtrol;
1535*4882a593Smuzhiyun }
1536*4882a593Smuzhiyun
1537*4882a593Smuzhiyun ret = of_property_read_u32(np, "ti,mode-sleep", &prop);
1538*4882a593Smuzhiyun if (!ret)
1539*4882a593Smuzhiyun rinit->mode_sleep = prop;
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun ret = of_property_read_bool(np, "ti,smps-range");
1542*4882a593Smuzhiyun if (ret)
1543*4882a593Smuzhiyun rinit->vsel = PALMAS_SMPS12_VOLTAGE_RANGE;
1544*4882a593Smuzhiyun
1545*4882a593Smuzhiyun if (idx == PALMAS_REG_LDO8)
1546*4882a593Smuzhiyun pdata->enable_ldo8_tracking = of_property_read_bool(
1547*4882a593Smuzhiyun np, "ti,enable-ldo8-tracking");
1548*4882a593Smuzhiyun }
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun return 0;
1553*4882a593Smuzhiyun }
1554*4882a593Smuzhiyun
1555*4882a593Smuzhiyun static const struct of_device_id of_palmas_match_tbl[] = {
1556*4882a593Smuzhiyun {
1557*4882a593Smuzhiyun .compatible = "ti,palmas-pmic",
1558*4882a593Smuzhiyun .data = &palmas_ddata,
1559*4882a593Smuzhiyun },
1560*4882a593Smuzhiyun {
1561*4882a593Smuzhiyun .compatible = "ti,twl6035-pmic",
1562*4882a593Smuzhiyun .data = &palmas_ddata,
1563*4882a593Smuzhiyun },
1564*4882a593Smuzhiyun {
1565*4882a593Smuzhiyun .compatible = "ti,twl6036-pmic",
1566*4882a593Smuzhiyun .data = &palmas_ddata,
1567*4882a593Smuzhiyun },
1568*4882a593Smuzhiyun {
1569*4882a593Smuzhiyun .compatible = "ti,twl6037-pmic",
1570*4882a593Smuzhiyun .data = &palmas_ddata,
1571*4882a593Smuzhiyun },
1572*4882a593Smuzhiyun {
1573*4882a593Smuzhiyun .compatible = "ti,tps65913-pmic",
1574*4882a593Smuzhiyun .data = &palmas_ddata,
1575*4882a593Smuzhiyun },
1576*4882a593Smuzhiyun {
1577*4882a593Smuzhiyun .compatible = "ti,tps65914-pmic",
1578*4882a593Smuzhiyun .data = &palmas_ddata,
1579*4882a593Smuzhiyun },
1580*4882a593Smuzhiyun {
1581*4882a593Smuzhiyun .compatible = "ti,tps80036-pmic",
1582*4882a593Smuzhiyun .data = &palmas_ddata,
1583*4882a593Smuzhiyun },
1584*4882a593Smuzhiyun {
1585*4882a593Smuzhiyun .compatible = "ti,tps659038-pmic",
1586*4882a593Smuzhiyun .data = &palmas_ddata,
1587*4882a593Smuzhiyun },
1588*4882a593Smuzhiyun {
1589*4882a593Smuzhiyun .compatible = "ti,tps65917-pmic",
1590*4882a593Smuzhiyun .data = &tps65917_ddata,
1591*4882a593Smuzhiyun },
1592*4882a593Smuzhiyun { /* end */ }
1593*4882a593Smuzhiyun };
1594*4882a593Smuzhiyun
palmas_regulators_probe(struct platform_device * pdev)1595*4882a593Smuzhiyun static int palmas_regulators_probe(struct platform_device *pdev)
1596*4882a593Smuzhiyun {
1597*4882a593Smuzhiyun struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
1598*4882a593Smuzhiyun struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
1599*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
1600*4882a593Smuzhiyun struct palmas_pmic_driver_data *driver_data;
1601*4882a593Smuzhiyun struct regulator_config config = { };
1602*4882a593Smuzhiyun struct palmas_pmic *pmic;
1603*4882a593Smuzhiyun const char *pdev_name;
1604*4882a593Smuzhiyun const struct of_device_id *match;
1605*4882a593Smuzhiyun int ret = 0;
1606*4882a593Smuzhiyun unsigned int reg;
1607*4882a593Smuzhiyun
1608*4882a593Smuzhiyun match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev);
1609*4882a593Smuzhiyun
1610*4882a593Smuzhiyun if (!match)
1611*4882a593Smuzhiyun return -ENODATA;
1612*4882a593Smuzhiyun
1613*4882a593Smuzhiyun driver_data = (struct palmas_pmic_driver_data *)match->data;
1614*4882a593Smuzhiyun pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1615*4882a593Smuzhiyun if (!pdata)
1616*4882a593Smuzhiyun return -ENOMEM;
1617*4882a593Smuzhiyun
1618*4882a593Smuzhiyun pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1619*4882a593Smuzhiyun if (!pmic)
1620*4882a593Smuzhiyun return -ENOMEM;
1621*4882a593Smuzhiyun
1622*4882a593Smuzhiyun if (of_device_is_compatible(node, "ti,tps659038-pmic")) {
1623*4882a593Smuzhiyun palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr =
1624*4882a593Smuzhiyun TPS659038_REGEN2_CTRL;
1625*4882a593Smuzhiyun palmas_ddata.has_regen3 = false;
1626*4882a593Smuzhiyun }
1627*4882a593Smuzhiyun
1628*4882a593Smuzhiyun pmic->dev = &pdev->dev;
1629*4882a593Smuzhiyun pmic->palmas = palmas;
1630*4882a593Smuzhiyun palmas->pmic = pmic;
1631*4882a593Smuzhiyun platform_set_drvdata(pdev, pmic);
1632*4882a593Smuzhiyun pmic->palmas->pmic_ddata = driver_data;
1633*4882a593Smuzhiyun
1634*4882a593Smuzhiyun ret = palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
1635*4882a593Smuzhiyun if (ret)
1636*4882a593Smuzhiyun return ret;
1637*4882a593Smuzhiyun
1638*4882a593Smuzhiyun ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, ®);
1639*4882a593Smuzhiyun if (ret)
1640*4882a593Smuzhiyun return ret;
1641*4882a593Smuzhiyun
1642*4882a593Smuzhiyun if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) {
1643*4882a593Smuzhiyun pmic->smps123 = 1;
1644*4882a593Smuzhiyun pmic->smps12 = 1;
1645*4882a593Smuzhiyun }
1646*4882a593Smuzhiyun
1647*4882a593Smuzhiyun if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
1648*4882a593Smuzhiyun pmic->smps457 = 1;
1649*4882a593Smuzhiyun
1650*4882a593Smuzhiyun config.regmap = palmas->regmap[REGULATOR_SLAVE];
1651*4882a593Smuzhiyun config.dev = &pdev->dev;
1652*4882a593Smuzhiyun config.driver_data = pmic;
1653*4882a593Smuzhiyun pdev_name = pdev->name;
1654*4882a593Smuzhiyun
1655*4882a593Smuzhiyun ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
1656*4882a593Smuzhiyun config);
1657*4882a593Smuzhiyun if (ret)
1658*4882a593Smuzhiyun return ret;
1659*4882a593Smuzhiyun
1660*4882a593Smuzhiyun ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
1661*4882a593Smuzhiyun config);
1662*4882a593Smuzhiyun
1663*4882a593Smuzhiyun return ret;
1664*4882a593Smuzhiyun }
1665*4882a593Smuzhiyun
1666*4882a593Smuzhiyun static struct platform_driver palmas_driver = {
1667*4882a593Smuzhiyun .driver = {
1668*4882a593Smuzhiyun .name = "palmas-pmic",
1669*4882a593Smuzhiyun .of_match_table = of_palmas_match_tbl,
1670*4882a593Smuzhiyun },
1671*4882a593Smuzhiyun .probe = palmas_regulators_probe,
1672*4882a593Smuzhiyun };
1673*4882a593Smuzhiyun
palmas_init(void)1674*4882a593Smuzhiyun static int __init palmas_init(void)
1675*4882a593Smuzhiyun {
1676*4882a593Smuzhiyun return platform_driver_register(&palmas_driver);
1677*4882a593Smuzhiyun }
1678*4882a593Smuzhiyun subsys_initcall(palmas_init);
1679*4882a593Smuzhiyun
palmas_exit(void)1680*4882a593Smuzhiyun static void __exit palmas_exit(void)
1681*4882a593Smuzhiyun {
1682*4882a593Smuzhiyun platform_driver_unregister(&palmas_driver);
1683*4882a593Smuzhiyun }
1684*4882a593Smuzhiyun module_exit(palmas_exit);
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1687*4882a593Smuzhiyun MODULE_DESCRIPTION("Palmas voltage regulator driver");
1688*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1689*4882a593Smuzhiyun MODULE_ALIAS("platform:palmas-pmic");
1690*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
1691