1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (C) 2020 MediaTek Inc.
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Author: Gene Chen <gene_chen@richtek.com>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/regulator/driver.h>
14*4882a593Smuzhiyun #include <linux/regulator/machine.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun enum {
19*4882a593Smuzhiyun MT6360_REGULATOR_BUCK1 = 0,
20*4882a593Smuzhiyun MT6360_REGULATOR_BUCK2,
21*4882a593Smuzhiyun MT6360_REGULATOR_LDO6,
22*4882a593Smuzhiyun MT6360_REGULATOR_LDO7,
23*4882a593Smuzhiyun MT6360_REGULATOR_LDO1,
24*4882a593Smuzhiyun MT6360_REGULATOR_LDO2,
25*4882a593Smuzhiyun MT6360_REGULATOR_LDO3,
26*4882a593Smuzhiyun MT6360_REGULATOR_LDO5,
27*4882a593Smuzhiyun MT6360_REGULATOR_MAX,
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct mt6360_irq_mapping {
31*4882a593Smuzhiyun const char *name;
32*4882a593Smuzhiyun irq_handler_t handler;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct mt6360_regulator_desc {
36*4882a593Smuzhiyun const struct regulator_desc desc;
37*4882a593Smuzhiyun unsigned int mode_reg;
38*4882a593Smuzhiyun unsigned int mode_mask;
39*4882a593Smuzhiyun unsigned int state_reg;
40*4882a593Smuzhiyun unsigned int state_mask;
41*4882a593Smuzhiyun const struct mt6360_irq_mapping *irq_tables;
42*4882a593Smuzhiyun int irq_table_size;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct mt6360_regulator_data {
46*4882a593Smuzhiyun struct device *dev;
47*4882a593Smuzhiyun struct regmap *regmap;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
mt6360_pgb_event_handler(int irq,void * data)50*4882a593Smuzhiyun static irqreturn_t mt6360_pgb_event_handler(int irq, void *data)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct regulator_dev *rdev = data;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun regulator_notifier_call_chain(rdev, REGULATOR_EVENT_FAIL, NULL);
55*4882a593Smuzhiyun return IRQ_HANDLED;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
mt6360_oc_event_handler(int irq,void * data)58*4882a593Smuzhiyun static irqreturn_t mt6360_oc_event_handler(int irq, void *data)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct regulator_dev *rdev = data;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun regulator_notifier_call_chain(rdev, REGULATOR_EVENT_OVER_CURRENT, NULL);
63*4882a593Smuzhiyun return IRQ_HANDLED;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
mt6360_ov_event_handler(int irq,void * data)66*4882a593Smuzhiyun static irqreturn_t mt6360_ov_event_handler(int irq, void *data)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct regulator_dev *rdev = data;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun regulator_notifier_call_chain(rdev, REGULATOR_EVENT_REGULATION_OUT, NULL);
71*4882a593Smuzhiyun return IRQ_HANDLED;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
mt6360_uv_event_handler(int irq,void * data)74*4882a593Smuzhiyun static irqreturn_t mt6360_uv_event_handler(int irq, void *data)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct regulator_dev *rdev = data;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun regulator_notifier_call_chain(rdev, REGULATOR_EVENT_UNDER_VOLTAGE, NULL);
79*4882a593Smuzhiyun return IRQ_HANDLED;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct mt6360_irq_mapping buck1_irq_tbls[] = {
83*4882a593Smuzhiyun { "buck1_pgb_evt", mt6360_pgb_event_handler },
84*4882a593Smuzhiyun { "buck1_oc_evt", mt6360_oc_event_handler },
85*4882a593Smuzhiyun { "buck1_ov_evt", mt6360_ov_event_handler },
86*4882a593Smuzhiyun { "buck1_uv_evt", mt6360_uv_event_handler },
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const struct mt6360_irq_mapping buck2_irq_tbls[] = {
90*4882a593Smuzhiyun { "buck2_pgb_evt", mt6360_pgb_event_handler },
91*4882a593Smuzhiyun { "buck2_oc_evt", mt6360_oc_event_handler },
92*4882a593Smuzhiyun { "buck2_ov_evt", mt6360_ov_event_handler },
93*4882a593Smuzhiyun { "buck2_uv_evt", mt6360_uv_event_handler },
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct mt6360_irq_mapping ldo6_irq_tbls[] = {
97*4882a593Smuzhiyun { "ldo6_pgb_evt", mt6360_pgb_event_handler },
98*4882a593Smuzhiyun { "ldo6_oc_evt", mt6360_oc_event_handler },
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct mt6360_irq_mapping ldo7_irq_tbls[] = {
102*4882a593Smuzhiyun { "ldo7_pgb_evt", mt6360_pgb_event_handler },
103*4882a593Smuzhiyun { "ldo7_oc_evt", mt6360_oc_event_handler },
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static const struct mt6360_irq_mapping ldo1_irq_tbls[] = {
107*4882a593Smuzhiyun { "ldo1_pgb_evt", mt6360_pgb_event_handler },
108*4882a593Smuzhiyun { "ldo1_oc_evt", mt6360_oc_event_handler },
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun static const struct mt6360_irq_mapping ldo2_irq_tbls[] = {
112*4882a593Smuzhiyun { "ldo2_pgb_evt", mt6360_pgb_event_handler },
113*4882a593Smuzhiyun { "ldo2_oc_evt", mt6360_oc_event_handler },
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static const struct mt6360_irq_mapping ldo3_irq_tbls[] = {
117*4882a593Smuzhiyun { "ldo3_pgb_evt", mt6360_pgb_event_handler },
118*4882a593Smuzhiyun { "ldo3_oc_evt", mt6360_oc_event_handler },
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static const struct mt6360_irq_mapping ldo5_irq_tbls[] = {
122*4882a593Smuzhiyun { "ldo5_pgb_evt", mt6360_pgb_event_handler },
123*4882a593Smuzhiyun { "ldo5_oc_evt", mt6360_oc_event_handler },
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun static const struct linear_range buck_vout_ranges[] = {
127*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(300000, 0x00, 0xc7, 5000),
128*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1300000, 0xc8, 0xff, 0),
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const struct linear_range ldo_vout_ranges1[] = {
132*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(500000, 0x00, 0x09, 10000),
133*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(600000, 0x0a, 0x10, 0),
134*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(610000, 0x11, 0x19, 10000),
135*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(700000, 0x1a, 0x20, 0),
136*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(710000, 0x21, 0x29, 10000),
137*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(800000, 0x2a, 0x30, 0),
138*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(810000, 0x31, 0x39, 10000),
139*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(900000, 0x3a, 0x40, 0),
140*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(910000, 0x41, 0x49, 10000),
141*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1000000, 0x4a, 0x50, 0),
142*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1010000, 0x51, 0x59, 10000),
143*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1100000, 0x5a, 0x60, 0),
144*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1110000, 0x61, 0x69, 10000),
145*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1200000, 0x6a, 0x70, 0),
146*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1210000, 0x71, 0x79, 10000),
147*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1300000, 0x7a, 0x80, 0),
148*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1310000, 0x81, 0x89, 10000),
149*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1400000, 0x8a, 0x90, 0),
150*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1410000, 0x91, 0x99, 10000),
151*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1500000, 0x9a, 0xa0, 0),
152*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1510000, 0xa1, 0xa9, 10000),
153*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1600000, 0xaa, 0xb0, 0),
154*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1610000, 0xb1, 0xb9, 10000),
155*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1700000, 0xba, 0xc0, 0),
156*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1710000, 0xc1, 0xc9, 10000),
157*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1800000, 0xca, 0xd0, 0),
158*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1810000, 0xd1, 0xd9, 10000),
159*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1900000, 0xda, 0xe0, 0),
160*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1910000, 0xe1, 0xe9, 10000),
161*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2000000, 0xea, 0xf0, 0),
162*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2010000, 0xf1, 0xf9, 10000),
163*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2100000, 0xfa, 0xff, 0),
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun static const struct linear_range ldo_vout_ranges2[] = {
167*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1200000, 0x00, 0x09, 10000),
168*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1300000, 0x0a, 0x10, 0),
169*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1310000, 0x11, 0x19, 10000),
170*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1400000, 0x1a, 0x1f, 0),
171*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1500000, 0x20, 0x29, 10000),
172*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1600000, 0x2a, 0x2f, 0),
173*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1700000, 0x30, 0x39, 10000),
174*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1800000, 0x3a, 0x40, 0),
175*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1810000, 0x41, 0x49, 10000),
176*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1900000, 0x4a, 0x4f, 0),
177*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2000000, 0x50, 0x59, 10000),
178*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2100000, 0x5a, 0x60, 0),
179*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2110000, 0x61, 0x69, 10000),
180*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2200000, 0x6a, 0x6f, 0),
181*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2500000, 0x70, 0x79, 10000),
182*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2600000, 0x7a, 0x7f, 0),
183*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2700000, 0x80, 0x89, 10000),
184*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2800000, 0x8a, 0x90, 0),
185*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2810000, 0x91, 0x99, 10000),
186*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2900000, 0x9a, 0xa0, 0),
187*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2910000, 0xa1, 0xa9, 10000),
188*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3000000, 0xaa, 0xb0, 0),
189*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3010000, 0xb1, 0xb9, 10000),
190*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3100000, 0xba, 0xc0, 0),
191*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3110000, 0xc1, 0xc9, 10000),
192*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3200000, 0xca, 0xcf, 0),
193*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3300000, 0xd0, 0xd9, 10000),
194*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3400000, 0xda, 0xe0, 0),
195*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3410000, 0xe1, 0xe9, 10000),
196*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3500000, 0xea, 0xf0, 0),
197*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3510000, 0xf1, 0xf9, 10000),
198*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3600000, 0xfa, 0xff, 0),
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun static const struct linear_range ldo_vout_ranges3[] = {
202*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2700000, 0x00, 0x09, 10000),
203*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2800000, 0x0a, 0x10, 0),
204*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2810000, 0x11, 0x19, 10000),
205*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2900000, 0x1a, 0x20, 0),
206*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2910000, 0x21, 0x29, 10000),
207*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3000000, 0x2a, 0x30, 0),
208*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3010000, 0x31, 0x39, 10000),
209*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3100000, 0x3a, 0x40, 0),
210*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3110000, 0x41, 0x49, 10000),
211*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3200000, 0x4a, 0x4f, 0),
212*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3300000, 0x50, 0x59, 10000),
213*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3400000, 0x5a, 0x60, 0),
214*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3410000, 0x61, 0x69, 10000),
215*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3500000, 0x6a, 0x70, 0),
216*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3510000, 0x71, 0x79, 10000),
217*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3600000, 0x7a, 0x7f, 0),
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun
mt6360_regulator_set_mode(struct regulator_dev * rdev,unsigned int mode)220*4882a593Smuzhiyun static int mt6360_regulator_set_mode(struct regulator_dev *rdev,
221*4882a593Smuzhiyun unsigned int mode)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun const struct mt6360_regulator_desc *rdesc = (struct mt6360_regulator_desc *)rdev->desc;
224*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(rdev);
225*4882a593Smuzhiyun int shift = ffs(rdesc->mode_mask) - 1;
226*4882a593Smuzhiyun unsigned int val;
227*4882a593Smuzhiyun int ret;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun switch (mode) {
230*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
231*4882a593Smuzhiyun val = MT6360_OPMODE_NORMAL;
232*4882a593Smuzhiyun break;
233*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
234*4882a593Smuzhiyun val = MT6360_OPMODE_ULP;
235*4882a593Smuzhiyun break;
236*4882a593Smuzhiyun case REGULATOR_MODE_IDLE:
237*4882a593Smuzhiyun val = MT6360_OPMODE_LP;
238*4882a593Smuzhiyun break;
239*4882a593Smuzhiyun default:
240*4882a593Smuzhiyun return -EINVAL;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun ret = regmap_update_bits(regmap, rdesc->mode_reg, rdesc->mode_mask, val << shift);
244*4882a593Smuzhiyun if (ret) {
245*4882a593Smuzhiyun dev_err(&rdev->dev, "%s: fail (%d)\n", __func__, ret);
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun return 0;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
mt6360_regulator_get_mode(struct regulator_dev * rdev)252*4882a593Smuzhiyun static unsigned int mt6360_regulator_get_mode(struct regulator_dev *rdev)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun const struct mt6360_regulator_desc *rdesc = (struct mt6360_regulator_desc *)rdev->desc;
255*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(rdev);
256*4882a593Smuzhiyun int shift = ffs(rdesc->mode_mask) - 1;
257*4882a593Smuzhiyun unsigned int val;
258*4882a593Smuzhiyun int ret;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun ret = regmap_read(regmap, rdesc->mode_reg, &val);
261*4882a593Smuzhiyun if (ret)
262*4882a593Smuzhiyun return ret;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun val &= rdesc->mode_mask;
265*4882a593Smuzhiyun val >>= shift;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun switch (val) {
268*4882a593Smuzhiyun case MT6360_OPMODE_LP:
269*4882a593Smuzhiyun return REGULATOR_MODE_IDLE;
270*4882a593Smuzhiyun case MT6360_OPMODE_ULP:
271*4882a593Smuzhiyun return REGULATOR_MODE_STANDBY;
272*4882a593Smuzhiyun case MT6360_OPMODE_NORMAL:
273*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
274*4882a593Smuzhiyun default:
275*4882a593Smuzhiyun return -EINVAL;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
mt6360_regulator_get_status(struct regulator_dev * rdev)279*4882a593Smuzhiyun static int mt6360_regulator_get_status(struct regulator_dev *rdev)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun const struct mt6360_regulator_desc *rdesc = (struct mt6360_regulator_desc *)rdev->desc;
282*4882a593Smuzhiyun struct regmap *regmap = rdev_get_regmap(rdev);
283*4882a593Smuzhiyun unsigned int val;
284*4882a593Smuzhiyun int ret;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun ret = regmap_read(regmap, rdesc->state_reg, &val);
287*4882a593Smuzhiyun if (ret)
288*4882a593Smuzhiyun return ret;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun if (val & rdesc->state_mask)
291*4882a593Smuzhiyun return REGULATOR_STATUS_ON;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun return REGULATOR_STATUS_OFF;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun static const struct regulator_ops mt6360_regulator_ops = {
297*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
298*4882a593Smuzhiyun .enable = regulator_enable_regmap,
299*4882a593Smuzhiyun .disable = regulator_disable_regmap,
300*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
301*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
302*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
303*4882a593Smuzhiyun .set_mode = mt6360_regulator_set_mode,
304*4882a593Smuzhiyun .get_mode = mt6360_regulator_get_mode,
305*4882a593Smuzhiyun .get_status = mt6360_regulator_get_status,
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun
mt6360_regulator_of_map_mode(unsigned int hw_mode)308*4882a593Smuzhiyun static unsigned int mt6360_regulator_of_map_mode(unsigned int hw_mode)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun switch (hw_mode) {
311*4882a593Smuzhiyun case MT6360_OPMODE_NORMAL:
312*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
313*4882a593Smuzhiyun case MT6360_OPMODE_LP:
314*4882a593Smuzhiyun return REGULATOR_MODE_IDLE;
315*4882a593Smuzhiyun case MT6360_OPMODE_ULP:
316*4882a593Smuzhiyun return REGULATOR_MODE_STANDBY;
317*4882a593Smuzhiyun default:
318*4882a593Smuzhiyun return REGULATOR_MODE_INVALID;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun #define MT6360_REGULATOR_DESC(_name, _sname, ereg, emask, vreg, vmask, \
323*4882a593Smuzhiyun mreg, mmask, streg, stmask, vranges, \
324*4882a593Smuzhiyun vcnts, offon_delay, irq_tbls) \
325*4882a593Smuzhiyun { \
326*4882a593Smuzhiyun .desc = { \
327*4882a593Smuzhiyun .name = #_name, \
328*4882a593Smuzhiyun .supply_name = #_sname, \
329*4882a593Smuzhiyun .id = MT6360_REGULATOR_##_name, \
330*4882a593Smuzhiyun .of_match = of_match_ptr(#_name), \
331*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulator"), \
332*4882a593Smuzhiyun .of_map_mode = mt6360_regulator_of_map_mode, \
333*4882a593Smuzhiyun .owner = THIS_MODULE, \
334*4882a593Smuzhiyun .ops = &mt6360_regulator_ops, \
335*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
336*4882a593Smuzhiyun .vsel_reg = vreg, \
337*4882a593Smuzhiyun .vsel_mask = vmask, \
338*4882a593Smuzhiyun .enable_reg = ereg, \
339*4882a593Smuzhiyun .enable_mask = emask, \
340*4882a593Smuzhiyun .linear_ranges = vranges, \
341*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(vranges), \
342*4882a593Smuzhiyun .n_voltages = vcnts, \
343*4882a593Smuzhiyun .off_on_delay = offon_delay, \
344*4882a593Smuzhiyun }, \
345*4882a593Smuzhiyun .mode_reg = mreg, \
346*4882a593Smuzhiyun .mode_mask = mmask, \
347*4882a593Smuzhiyun .state_reg = streg, \
348*4882a593Smuzhiyun .state_mask = stmask, \
349*4882a593Smuzhiyun .irq_tables = irq_tbls, \
350*4882a593Smuzhiyun .irq_table_size = ARRAY_SIZE(irq_tbls), \
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun static const struct mt6360_regulator_desc mt6360_regulator_descs[] = {
354*4882a593Smuzhiyun MT6360_REGULATOR_DESC(BUCK1, BUCK1_VIN, 0x117, 0x40, 0x110, 0xff, 0x117, 0x30, 0x117, 0x04,
355*4882a593Smuzhiyun buck_vout_ranges, 256, 0, buck1_irq_tbls),
356*4882a593Smuzhiyun MT6360_REGULATOR_DESC(BUCK2, BUCK2_VIN, 0x127, 0x40, 0x120, 0xff, 0x127, 0x30, 0x127, 0x04,
357*4882a593Smuzhiyun buck_vout_ranges, 256, 0, buck2_irq_tbls),
358*4882a593Smuzhiyun MT6360_REGULATOR_DESC(LDO6, LDO_VIN3, 0x137, 0x40, 0x13B, 0xff, 0x137, 0x30, 0x137, 0x04,
359*4882a593Smuzhiyun ldo_vout_ranges1, 256, 0, ldo6_irq_tbls),
360*4882a593Smuzhiyun MT6360_REGULATOR_DESC(LDO7, LDO_VIN3, 0x131, 0x40, 0x135, 0xff, 0x131, 0x30, 0x131, 0x04,
361*4882a593Smuzhiyun ldo_vout_ranges1, 256, 0, ldo7_irq_tbls),
362*4882a593Smuzhiyun MT6360_REGULATOR_DESC(LDO1, LDO_VIN1, 0x217, 0x40, 0x21B, 0xff, 0x217, 0x30, 0x217, 0x04,
363*4882a593Smuzhiyun ldo_vout_ranges2, 256, 0, ldo1_irq_tbls),
364*4882a593Smuzhiyun MT6360_REGULATOR_DESC(LDO2, LDO_VIN1, 0x211, 0x40, 0x215, 0xff, 0x211, 0x30, 0x211, 0x04,
365*4882a593Smuzhiyun ldo_vout_ranges2, 256, 0, ldo2_irq_tbls),
366*4882a593Smuzhiyun MT6360_REGULATOR_DESC(LDO3, LDO_VIN1, 0x205, 0x40, 0x209, 0xff, 0x205, 0x30, 0x205, 0x04,
367*4882a593Smuzhiyun ldo_vout_ranges2, 256, 100, ldo3_irq_tbls),
368*4882a593Smuzhiyun MT6360_REGULATOR_DESC(LDO5, LDO_VIN2, 0x20B, 0x40, 0x20F, 0x7f, 0x20B, 0x30, 0x20B, 0x04,
369*4882a593Smuzhiyun ldo_vout_ranges3, 128, 100, ldo5_irq_tbls),
370*4882a593Smuzhiyun };
371*4882a593Smuzhiyun
mt6360_regulator_irq_register(struct platform_device * pdev,struct regulator_dev * rdev,const struct mt6360_irq_mapping * tbls,int tbl_size)372*4882a593Smuzhiyun static int mt6360_regulator_irq_register(struct platform_device *pdev,
373*4882a593Smuzhiyun struct regulator_dev *rdev,
374*4882a593Smuzhiyun const struct mt6360_irq_mapping *tbls,
375*4882a593Smuzhiyun int tbl_size)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun int i, irq, ret;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun for (i = 0; i < tbl_size; i++) {
380*4882a593Smuzhiyun const struct mt6360_irq_mapping *irq_desc = tbls + i;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun irq = platform_get_irq_byname(pdev, irq_desc->name);
383*4882a593Smuzhiyun if (irq < 0) {
384*4882a593Smuzhiyun dev_err(&pdev->dev, "Fail to get %s irq\n", irq_desc->name);
385*4882a593Smuzhiyun return irq;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, irq_desc->handler, 0,
389*4882a593Smuzhiyun irq_desc->name, rdev);
390*4882a593Smuzhiyun if (ret) {
391*4882a593Smuzhiyun dev_err(&pdev->dev, "Fail to request %s irq\n", irq_desc->name);
392*4882a593Smuzhiyun return ret;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun return 0;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
mt6360_regulator_probe(struct platform_device * pdev)399*4882a593Smuzhiyun static int mt6360_regulator_probe(struct platform_device *pdev)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun struct mt6360_regulator_data *mrd;
402*4882a593Smuzhiyun struct regulator_config config = {};
403*4882a593Smuzhiyun int i, ret;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun mrd = devm_kzalloc(&pdev->dev, sizeof(*mrd), GFP_KERNEL);
406*4882a593Smuzhiyun if (!mrd)
407*4882a593Smuzhiyun return -ENOMEM;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun mrd->dev = &pdev->dev;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun mrd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
412*4882a593Smuzhiyun if (!mrd->regmap) {
413*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to get parent regmap\n");
414*4882a593Smuzhiyun return -ENODEV;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun config.dev = pdev->dev.parent;
418*4882a593Smuzhiyun config.driver_data = mrd;
419*4882a593Smuzhiyun config.regmap = mrd->regmap;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mt6360_regulator_descs); i++) {
422*4882a593Smuzhiyun const struct mt6360_regulator_desc *rdesc = mt6360_regulator_descs + i;
423*4882a593Smuzhiyun struct regulator_dev *rdev;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev, &rdesc->desc, &config);
426*4882a593Smuzhiyun if (IS_ERR(rdev)) {
427*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register %d regulator\n", i);
428*4882a593Smuzhiyun return PTR_ERR(rdev);
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun ret = mt6360_regulator_irq_register(pdev, rdev, rdesc->irq_tables,
432*4882a593Smuzhiyun rdesc->irq_table_size);
433*4882a593Smuzhiyun if (ret) {
434*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register %d regulator irqs\n", i);
435*4882a593Smuzhiyun return ret;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun return 0;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun static const struct platform_device_id mt6360_regulator_id_table[] = {
443*4882a593Smuzhiyun { "mt6360-regulator", 0 },
444*4882a593Smuzhiyun {},
445*4882a593Smuzhiyun };
446*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, mt6360_regulator_id_table);
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun static struct platform_driver mt6360_regulator_driver = {
449*4882a593Smuzhiyun .driver = {
450*4882a593Smuzhiyun .name = "mt6360-regulator",
451*4882a593Smuzhiyun },
452*4882a593Smuzhiyun .probe = mt6360_regulator_probe,
453*4882a593Smuzhiyun .id_table = mt6360_regulator_id_table,
454*4882a593Smuzhiyun };
455*4882a593Smuzhiyun module_platform_driver(mt6360_regulator_driver);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>");
458*4882a593Smuzhiyun MODULE_DESCRIPTION("MT6360 Regulator Driver");
459*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
460