1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2016 MediaTek Inc.
4*4882a593Smuzhiyun // Author: Chen Zhong <chen.zhong@mediatek.com>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/of.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/mfd/mt6397/core.h>
11*4882a593Smuzhiyun #include <linux/mfd/mt6323/registers.h>
12*4882a593Smuzhiyun #include <linux/regulator/driver.h>
13*4882a593Smuzhiyun #include <linux/regulator/machine.h>
14*4882a593Smuzhiyun #include <linux/regulator/mt6323-regulator.h>
15*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define MT6323_LDO_MODE_NORMAL 0
18*4882a593Smuzhiyun #define MT6323_LDO_MODE_LP 1
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * MT6323 regulators' information
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * @desc: standard fields of regulator description.
24*4882a593Smuzhiyun * @qi: Mask for query enable signal status of regulators
25*4882a593Smuzhiyun * @vselon_reg: Register sections for hardware control mode of bucks
26*4882a593Smuzhiyun * @vselctrl_reg: Register for controlling the buck control mode.
27*4882a593Smuzhiyun * @vselctrl_mask: Mask for query buck's voltage control mode.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun struct mt6323_regulator_info {
30*4882a593Smuzhiyun struct regulator_desc desc;
31*4882a593Smuzhiyun u32 qi;
32*4882a593Smuzhiyun u32 vselon_reg;
33*4882a593Smuzhiyun u32 vselctrl_reg;
34*4882a593Smuzhiyun u32 vselctrl_mask;
35*4882a593Smuzhiyun u32 modeset_reg;
36*4882a593Smuzhiyun u32 modeset_mask;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define MT6323_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
40*4882a593Smuzhiyun vosel, vosel_mask, voselon, vosel_ctrl) \
41*4882a593Smuzhiyun [MT6323_ID_##vreg] = { \
42*4882a593Smuzhiyun .desc = { \
43*4882a593Smuzhiyun .name = #vreg, \
44*4882a593Smuzhiyun .of_match = of_match_ptr(match), \
45*4882a593Smuzhiyun .ops = &mt6323_volt_range_ops, \
46*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
47*4882a593Smuzhiyun .id = MT6323_ID_##vreg, \
48*4882a593Smuzhiyun .owner = THIS_MODULE, \
49*4882a593Smuzhiyun .n_voltages = (max - min)/step + 1, \
50*4882a593Smuzhiyun .linear_ranges = volt_ranges, \
51*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
52*4882a593Smuzhiyun .vsel_reg = vosel, \
53*4882a593Smuzhiyun .vsel_mask = vosel_mask, \
54*4882a593Smuzhiyun .enable_reg = enreg, \
55*4882a593Smuzhiyun .enable_mask = BIT(0), \
56*4882a593Smuzhiyun }, \
57*4882a593Smuzhiyun .qi = BIT(13), \
58*4882a593Smuzhiyun .vselon_reg = voselon, \
59*4882a593Smuzhiyun .vselctrl_reg = vosel_ctrl, \
60*4882a593Smuzhiyun .vselctrl_mask = BIT(1), \
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define MT6323_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
64*4882a593Smuzhiyun vosel_mask, _modeset_reg, _modeset_mask) \
65*4882a593Smuzhiyun [MT6323_ID_##vreg] = { \
66*4882a593Smuzhiyun .desc = { \
67*4882a593Smuzhiyun .name = #vreg, \
68*4882a593Smuzhiyun .of_match = of_match_ptr(match), \
69*4882a593Smuzhiyun .ops = &mt6323_volt_table_ops, \
70*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
71*4882a593Smuzhiyun .id = MT6323_ID_##vreg, \
72*4882a593Smuzhiyun .owner = THIS_MODULE, \
73*4882a593Smuzhiyun .n_voltages = ARRAY_SIZE(ldo_volt_table), \
74*4882a593Smuzhiyun .volt_table = ldo_volt_table, \
75*4882a593Smuzhiyun .vsel_reg = vosel, \
76*4882a593Smuzhiyun .vsel_mask = vosel_mask, \
77*4882a593Smuzhiyun .enable_reg = enreg, \
78*4882a593Smuzhiyun .enable_mask = BIT(enbit), \
79*4882a593Smuzhiyun }, \
80*4882a593Smuzhiyun .qi = BIT(15), \
81*4882a593Smuzhiyun .modeset_reg = _modeset_reg, \
82*4882a593Smuzhiyun .modeset_mask = _modeset_mask, \
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define MT6323_REG_FIXED(match, vreg, enreg, enbit, volt, \
86*4882a593Smuzhiyun _modeset_reg, _modeset_mask) \
87*4882a593Smuzhiyun [MT6323_ID_##vreg] = { \
88*4882a593Smuzhiyun .desc = { \
89*4882a593Smuzhiyun .name = #vreg, \
90*4882a593Smuzhiyun .of_match = of_match_ptr(match), \
91*4882a593Smuzhiyun .ops = &mt6323_volt_fixed_ops, \
92*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
93*4882a593Smuzhiyun .id = MT6323_ID_##vreg, \
94*4882a593Smuzhiyun .owner = THIS_MODULE, \
95*4882a593Smuzhiyun .n_voltages = 1, \
96*4882a593Smuzhiyun .enable_reg = enreg, \
97*4882a593Smuzhiyun .enable_mask = BIT(enbit), \
98*4882a593Smuzhiyun .min_uV = volt, \
99*4882a593Smuzhiyun }, \
100*4882a593Smuzhiyun .qi = BIT(15), \
101*4882a593Smuzhiyun .modeset_reg = _modeset_reg, \
102*4882a593Smuzhiyun .modeset_mask = _modeset_mask, \
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun static const struct linear_range buck_volt_range1[] = {
106*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun static const struct linear_range buck_volt_range2[] = {
110*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500),
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun static const struct linear_range buck_volt_range3[] = {
114*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static const unsigned int ldo_volt_table1[] = {
118*4882a593Smuzhiyun 3300000, 3400000, 3500000, 3600000,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static const unsigned int ldo_volt_table2[] = {
122*4882a593Smuzhiyun 1500000, 1800000, 2500000, 2800000,
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun static const unsigned int ldo_volt_table3[] = {
126*4882a593Smuzhiyun 1800000, 3300000,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static const unsigned int ldo_volt_table4[] = {
130*4882a593Smuzhiyun 3000000, 3300000,
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun static const unsigned int ldo_volt_table5[] = {
134*4882a593Smuzhiyun 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static const unsigned int ldo_volt_table6[] = {
138*4882a593Smuzhiyun 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000,
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun static const unsigned int ldo_volt_table7[] = {
142*4882a593Smuzhiyun 1200000, 1300000, 1500000, 1800000,
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static const unsigned int ldo_volt_table8[] = {
146*4882a593Smuzhiyun 1800000, 3000000,
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun static const unsigned int ldo_volt_table9[] = {
150*4882a593Smuzhiyun 1200000, 1350000, 1500000, 1800000,
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static const unsigned int ldo_volt_table10[] = {
154*4882a593Smuzhiyun 1200000, 1300000, 1500000, 1800000,
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun
mt6323_get_status(struct regulator_dev * rdev)157*4882a593Smuzhiyun static int mt6323_get_status(struct regulator_dev *rdev)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun int ret;
160*4882a593Smuzhiyun u32 regval;
161*4882a593Smuzhiyun struct mt6323_regulator_info *info = rdev_get_drvdata(rdev);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val);
164*4882a593Smuzhiyun if (ret != 0) {
165*4882a593Smuzhiyun dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
166*4882a593Smuzhiyun return ret;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
mt6323_ldo_set_mode(struct regulator_dev * rdev,unsigned int mode)172*4882a593Smuzhiyun static int mt6323_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun int ret, val = 0;
175*4882a593Smuzhiyun struct mt6323_regulator_info *info = rdev_get_drvdata(rdev);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (!info->modeset_mask) {
178*4882a593Smuzhiyun dev_err(&rdev->dev, "regulator %s doesn't support set_mode\n",
179*4882a593Smuzhiyun info->desc.name);
180*4882a593Smuzhiyun return -EINVAL;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun switch (mode) {
184*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
185*4882a593Smuzhiyun val = MT6323_LDO_MODE_LP;
186*4882a593Smuzhiyun break;
187*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
188*4882a593Smuzhiyun val = MT6323_LDO_MODE_NORMAL;
189*4882a593Smuzhiyun break;
190*4882a593Smuzhiyun default:
191*4882a593Smuzhiyun return -EINVAL;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun val <<= ffs(info->modeset_mask) - 1;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
197*4882a593Smuzhiyun info->modeset_mask, val);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun return ret;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
mt6323_ldo_get_mode(struct regulator_dev * rdev)202*4882a593Smuzhiyun static unsigned int mt6323_ldo_get_mode(struct regulator_dev *rdev)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun unsigned int val;
205*4882a593Smuzhiyun unsigned int mode;
206*4882a593Smuzhiyun int ret;
207*4882a593Smuzhiyun struct mt6323_regulator_info *info = rdev_get_drvdata(rdev);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun if (!info->modeset_mask) {
210*4882a593Smuzhiyun dev_err(&rdev->dev, "regulator %s doesn't support get_mode\n",
211*4882a593Smuzhiyun info->desc.name);
212*4882a593Smuzhiyun return -EINVAL;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
216*4882a593Smuzhiyun if (ret < 0)
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun val &= info->modeset_mask;
220*4882a593Smuzhiyun val >>= ffs(info->modeset_mask) - 1;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (val & 0x1)
223*4882a593Smuzhiyun mode = REGULATOR_MODE_STANDBY;
224*4882a593Smuzhiyun else
225*4882a593Smuzhiyun mode = REGULATOR_MODE_NORMAL;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun return mode;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun static const struct regulator_ops mt6323_volt_range_ops = {
231*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
232*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
233*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
234*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
235*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
236*4882a593Smuzhiyun .enable = regulator_enable_regmap,
237*4882a593Smuzhiyun .disable = regulator_disable_regmap,
238*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
239*4882a593Smuzhiyun .get_status = mt6323_get_status,
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static const struct regulator_ops mt6323_volt_table_ops = {
243*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_table,
244*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_iterate,
245*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
246*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
247*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
248*4882a593Smuzhiyun .enable = regulator_enable_regmap,
249*4882a593Smuzhiyun .disable = regulator_disable_regmap,
250*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
251*4882a593Smuzhiyun .get_status = mt6323_get_status,
252*4882a593Smuzhiyun .set_mode = mt6323_ldo_set_mode,
253*4882a593Smuzhiyun .get_mode = mt6323_ldo_get_mode,
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun static const struct regulator_ops mt6323_volt_fixed_ops = {
257*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
258*4882a593Smuzhiyun .enable = regulator_enable_regmap,
259*4882a593Smuzhiyun .disable = regulator_disable_regmap,
260*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
261*4882a593Smuzhiyun .get_status = mt6323_get_status,
262*4882a593Smuzhiyun .set_mode = mt6323_ldo_set_mode,
263*4882a593Smuzhiyun .get_mode = mt6323_ldo_get_mode,
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /* The array is indexed by id(MT6323_ID_XXX) */
267*4882a593Smuzhiyun static struct mt6323_regulator_info mt6323_regulators[] = {
268*4882a593Smuzhiyun MT6323_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250,
269*4882a593Smuzhiyun buck_volt_range1, MT6323_VPROC_CON7, MT6323_VPROC_CON9, 0x7f,
270*4882a593Smuzhiyun MT6323_VPROC_CON10, MT6323_VPROC_CON5),
271*4882a593Smuzhiyun MT6323_BUCK("buck_vsys", VSYS, 1400000, 2987500, 12500,
272*4882a593Smuzhiyun buck_volt_range2, MT6323_VSYS_CON7, MT6323_VSYS_CON9, 0x7f,
273*4882a593Smuzhiyun MT6323_VSYS_CON10, MT6323_VSYS_CON5),
274*4882a593Smuzhiyun MT6323_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
275*4882a593Smuzhiyun buck_volt_range3, MT6323_VPA_CON7, MT6323_VPA_CON9,
276*4882a593Smuzhiyun 0x3f, MT6323_VPA_CON10, MT6323_VPA_CON5),
277*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vtcxo", VTCXO, MT6323_ANALDO_CON1, 10, 2800000,
278*4882a593Smuzhiyun MT6323_ANALDO_CON1, 0x2),
279*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vcn28", VCN28, MT6323_ANALDO_CON19, 12, 2800000,
280*4882a593Smuzhiyun MT6323_ANALDO_CON20, 0x2),
281*4882a593Smuzhiyun MT6323_LDO("ldo_vcn33_bt", VCN33_BT, ldo_volt_table1,
282*4882a593Smuzhiyun MT6323_ANALDO_CON16, 7, MT6323_ANALDO_CON16, 0xC,
283*4882a593Smuzhiyun MT6323_ANALDO_CON21, 0x2),
284*4882a593Smuzhiyun MT6323_LDO("ldo_vcn33_wifi", VCN33_WIFI, ldo_volt_table1,
285*4882a593Smuzhiyun MT6323_ANALDO_CON17, 12, MT6323_ANALDO_CON16, 0xC,
286*4882a593Smuzhiyun MT6323_ANALDO_CON21, 0x2),
287*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_va", VA, MT6323_ANALDO_CON2, 14, 2800000,
288*4882a593Smuzhiyun MT6323_ANALDO_CON2, 0x2),
289*4882a593Smuzhiyun MT6323_LDO("ldo_vcama", VCAMA, ldo_volt_table2,
290*4882a593Smuzhiyun MT6323_ANALDO_CON4, 15, MT6323_ANALDO_CON10, 0x60, -1, 0),
291*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vio28", VIO28, MT6323_DIGLDO_CON0, 14, 2800000,
292*4882a593Smuzhiyun MT6323_DIGLDO_CON0, 0x2),
293*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vusb", VUSB, MT6323_DIGLDO_CON2, 14, 3300000,
294*4882a593Smuzhiyun MT6323_DIGLDO_CON2, 0x2),
295*4882a593Smuzhiyun MT6323_LDO("ldo_vmc", VMC, ldo_volt_table3,
296*4882a593Smuzhiyun MT6323_DIGLDO_CON3, 12, MT6323_DIGLDO_CON24, 0x10,
297*4882a593Smuzhiyun MT6323_DIGLDO_CON3, 0x2),
298*4882a593Smuzhiyun MT6323_LDO("ldo_vmch", VMCH, ldo_volt_table4,
299*4882a593Smuzhiyun MT6323_DIGLDO_CON5, 14, MT6323_DIGLDO_CON26, 0x80,
300*4882a593Smuzhiyun MT6323_DIGLDO_CON5, 0x2),
301*4882a593Smuzhiyun MT6323_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table4,
302*4882a593Smuzhiyun MT6323_DIGLDO_CON6, 14, MT6323_DIGLDO_CON27, 0x80,
303*4882a593Smuzhiyun MT6323_DIGLDO_CON6, 0x2),
304*4882a593Smuzhiyun MT6323_LDO("ldo_vgp1", VGP1, ldo_volt_table5,
305*4882a593Smuzhiyun MT6323_DIGLDO_CON7, 15, MT6323_DIGLDO_CON28, 0xE0,
306*4882a593Smuzhiyun MT6323_DIGLDO_CON7, 0x2),
307*4882a593Smuzhiyun MT6323_LDO("ldo_vgp2", VGP2, ldo_volt_table6,
308*4882a593Smuzhiyun MT6323_DIGLDO_CON8, 15, MT6323_DIGLDO_CON29, 0xE0,
309*4882a593Smuzhiyun MT6323_DIGLDO_CON8, 0x2),
310*4882a593Smuzhiyun MT6323_LDO("ldo_vgp3", VGP3, ldo_volt_table7,
311*4882a593Smuzhiyun MT6323_DIGLDO_CON9, 15, MT6323_DIGLDO_CON30, 0x60,
312*4882a593Smuzhiyun MT6323_DIGLDO_CON9, 0x2),
313*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vcn18", VCN18, MT6323_DIGLDO_CON11, 14, 1800000,
314*4882a593Smuzhiyun MT6323_DIGLDO_CON11, 0x2),
315*4882a593Smuzhiyun MT6323_LDO("ldo_vsim1", VSIM1, ldo_volt_table8,
316*4882a593Smuzhiyun MT6323_DIGLDO_CON13, 15, MT6323_DIGLDO_CON34, 0x20,
317*4882a593Smuzhiyun MT6323_DIGLDO_CON13, 0x2),
318*4882a593Smuzhiyun MT6323_LDO("ldo_vsim2", VSIM2, ldo_volt_table8,
319*4882a593Smuzhiyun MT6323_DIGLDO_CON14, 15, MT6323_DIGLDO_CON35, 0x20,
320*4882a593Smuzhiyun MT6323_DIGLDO_CON14, 0x2),
321*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vrtc", VRTC, MT6323_DIGLDO_CON15, 8, 2800000,
322*4882a593Smuzhiyun -1, 0),
323*4882a593Smuzhiyun MT6323_LDO("ldo_vcamaf", VCAMAF, ldo_volt_table5,
324*4882a593Smuzhiyun MT6323_DIGLDO_CON31, 15, MT6323_DIGLDO_CON32, 0xE0,
325*4882a593Smuzhiyun MT6323_DIGLDO_CON31, 0x2),
326*4882a593Smuzhiyun MT6323_LDO("ldo_vibr", VIBR, ldo_volt_table5,
327*4882a593Smuzhiyun MT6323_DIGLDO_CON39, 15, MT6323_DIGLDO_CON40, 0xE0,
328*4882a593Smuzhiyun MT6323_DIGLDO_CON39, 0x2),
329*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vrf18", VRF18, MT6323_DIGLDO_CON45, 15, 1825000,
330*4882a593Smuzhiyun MT6323_DIGLDO_CON45, 0x2),
331*4882a593Smuzhiyun MT6323_LDO("ldo_vm", VM, ldo_volt_table9,
332*4882a593Smuzhiyun MT6323_DIGLDO_CON47, 14, MT6323_DIGLDO_CON48, 0x30,
333*4882a593Smuzhiyun MT6323_DIGLDO_CON47, 0x2),
334*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vio18", VIO18, MT6323_DIGLDO_CON49, 14, 1800000,
335*4882a593Smuzhiyun MT6323_DIGLDO_CON49, 0x2),
336*4882a593Smuzhiyun MT6323_LDO("ldo_vcamd", VCAMD, ldo_volt_table10,
337*4882a593Smuzhiyun MT6323_DIGLDO_CON51, 14, MT6323_DIGLDO_CON52, 0x60,
338*4882a593Smuzhiyun MT6323_DIGLDO_CON51, 0x2),
339*4882a593Smuzhiyun MT6323_REG_FIXED("ldo_vcamio", VCAMIO, MT6323_DIGLDO_CON53, 14, 1800000,
340*4882a593Smuzhiyun MT6323_DIGLDO_CON53, 0x2),
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun
mt6323_set_buck_vosel_reg(struct platform_device * pdev)343*4882a593Smuzhiyun static int mt6323_set_buck_vosel_reg(struct platform_device *pdev)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun struct mt6397_chip *mt6323 = dev_get_drvdata(pdev->dev.parent);
346*4882a593Smuzhiyun int i;
347*4882a593Smuzhiyun u32 regval;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun for (i = 0; i < MT6323_MAX_REGULATOR; i++) {
350*4882a593Smuzhiyun if (mt6323_regulators[i].vselctrl_reg) {
351*4882a593Smuzhiyun if (regmap_read(mt6323->regmap,
352*4882a593Smuzhiyun mt6323_regulators[i].vselctrl_reg,
353*4882a593Smuzhiyun ®val) < 0) {
354*4882a593Smuzhiyun dev_err(&pdev->dev,
355*4882a593Smuzhiyun "Failed to read buck ctrl\n");
356*4882a593Smuzhiyun return -EIO;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun if (regval & mt6323_regulators[i].vselctrl_mask) {
360*4882a593Smuzhiyun mt6323_regulators[i].desc.vsel_reg =
361*4882a593Smuzhiyun mt6323_regulators[i].vselon_reg;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun return 0;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
mt6323_regulator_probe(struct platform_device * pdev)369*4882a593Smuzhiyun static int mt6323_regulator_probe(struct platform_device *pdev)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun struct mt6397_chip *mt6323 = dev_get_drvdata(pdev->dev.parent);
372*4882a593Smuzhiyun struct regulator_config config = {};
373*4882a593Smuzhiyun struct regulator_dev *rdev;
374*4882a593Smuzhiyun int i;
375*4882a593Smuzhiyun u32 reg_value;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /* Query buck controller to select activated voltage register part */
378*4882a593Smuzhiyun if (mt6323_set_buck_vosel_reg(pdev))
379*4882a593Smuzhiyun return -EIO;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun /* Read PMIC chip revision to update constraints and voltage table */
382*4882a593Smuzhiyun if (regmap_read(mt6323->regmap, MT6323_CID, ®_value) < 0) {
383*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to read Chip ID\n");
384*4882a593Smuzhiyun return -EIO;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun for (i = 0; i < MT6323_MAX_REGULATOR; i++) {
389*4882a593Smuzhiyun config.dev = &pdev->dev;
390*4882a593Smuzhiyun config.driver_data = &mt6323_regulators[i];
391*4882a593Smuzhiyun config.regmap = mt6323->regmap;
392*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev,
393*4882a593Smuzhiyun &mt6323_regulators[i].desc, &config);
394*4882a593Smuzhiyun if (IS_ERR(rdev)) {
395*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to register %s\n",
396*4882a593Smuzhiyun mt6323_regulators[i].desc.name);
397*4882a593Smuzhiyun return PTR_ERR(rdev);
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun return 0;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun static const struct platform_device_id mt6323_platform_ids[] = {
404*4882a593Smuzhiyun {"mt6323-regulator", 0},
405*4882a593Smuzhiyun { /* sentinel */ },
406*4882a593Smuzhiyun };
407*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, mt6323_platform_ids);
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun static struct platform_driver mt6323_regulator_driver = {
410*4882a593Smuzhiyun .driver = {
411*4882a593Smuzhiyun .name = "mt6323-regulator",
412*4882a593Smuzhiyun },
413*4882a593Smuzhiyun .probe = mt6323_regulator_probe,
414*4882a593Smuzhiyun .id_table = mt6323_platform_ids,
415*4882a593Smuzhiyun };
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun module_platform_driver(mt6323_regulator_driver);
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun MODULE_AUTHOR("Chen Zhong <chen.zhong@mediatek.com>");
420*4882a593Smuzhiyun MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6323 PMIC");
421*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
422