1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Henry Chen <henryc.chen@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MT6311_REGULATOR_H__ 8*4882a593Smuzhiyun #define __MT6311_REGULATOR_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MT6311_SWCID 0x01 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MT6311_TOP_INT_CON 0x18 13*4882a593Smuzhiyun #define MT6311_TOP_INT_MON 0x19 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MT6311_VDVFS11_CON0 0x87 16*4882a593Smuzhiyun #define MT6311_VDVFS11_CON7 0x88 17*4882a593Smuzhiyun #define MT6311_VDVFS11_CON8 0x89 18*4882a593Smuzhiyun #define MT6311_VDVFS11_CON9 0x8A 19*4882a593Smuzhiyun #define MT6311_VDVFS11_CON10 0x8B 20*4882a593Smuzhiyun #define MT6311_VDVFS11_CON11 0x8C 21*4882a593Smuzhiyun #define MT6311_VDVFS11_CON12 0x8D 22*4882a593Smuzhiyun #define MT6311_VDVFS11_CON13 0x8E 23*4882a593Smuzhiyun #define MT6311_VDVFS11_CON14 0x8F 24*4882a593Smuzhiyun #define MT6311_VDVFS11_CON15 0x90 25*4882a593Smuzhiyun #define MT6311_VDVFS11_CON16 0x91 26*4882a593Smuzhiyun #define MT6311_VDVFS11_CON17 0x92 27*4882a593Smuzhiyun #define MT6311_VDVFS11_CON18 0x93 28*4882a593Smuzhiyun #define MT6311_VDVFS11_CON19 0x94 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define MT6311_LDO_CON0 0xCC 31*4882a593Smuzhiyun #define MT6311_LDO_OCFB0 0xCD 32*4882a593Smuzhiyun #define MT6311_LDO_CON2 0xCE 33*4882a593Smuzhiyun #define MT6311_LDO_CON3 0xCF 34*4882a593Smuzhiyun #define MT6311_LDO_CON4 0xD0 35*4882a593Smuzhiyun #define MT6311_FQMTR_CON0 0xD1 36*4882a593Smuzhiyun #define MT6311_FQMTR_CON1 0xD2 37*4882a593Smuzhiyun #define MT6311_FQMTR_CON2 0xD3 38*4882a593Smuzhiyun #define MT6311_FQMTR_CON3 0xD4 39*4882a593Smuzhiyun #define MT6311_FQMTR_CON4 0xD5 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MT6311_PMIC_RG_INT_POL_MASK 0x1 42*4882a593Smuzhiyun #define MT6311_PMIC_RG_INT_EN_MASK 0x2 43*4882a593Smuzhiyun #define MT6311_PMIC_RG_BUCK_OC_INT_STATUS_MASK 0x10 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MT6311_PMIC_VDVFS11_EN_CTRL_MASK 0x1 46*4882a593Smuzhiyun #define MT6311_PMIC_VDVFS11_VOSEL_CTRL_MASK 0x2 47*4882a593Smuzhiyun #define MT6311_PMIC_VDVFS11_EN_SEL_MASK 0x3 48*4882a593Smuzhiyun #define MT6311_PMIC_VDVFS11_VOSEL_SEL_MASK 0xc 49*4882a593Smuzhiyun #define MT6311_PMIC_VDVFS11_EN_MASK 0x1 50*4882a593Smuzhiyun #define MT6311_PMIC_VDVFS11_VOSEL_MASK 0x7F 51*4882a593Smuzhiyun #define MT6311_PMIC_VDVFS11_VOSEL_ON_MASK 0x7F 52*4882a593Smuzhiyun #define MT6311_PMIC_VDVFS11_VOSEL_SLEEP_MASK 0x7F 53*4882a593Smuzhiyun #define MT6311_PMIC_NI_VDVFS11_VOSEL_MASK 0x7F 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define MT6311_PMIC_RG_VBIASN_EN_MASK 0x1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif 58