1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mpq7920.h - Regulator definitions for mpq7920 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2019 Monolithic Power Systems, Inc 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MPQ7920_H__ 10*4882a593Smuzhiyun #define __MPQ7920_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MPQ7920_REG_CTL0 0x00 13*4882a593Smuzhiyun #define MPQ7920_REG_CTL1 0x01 14*4882a593Smuzhiyun #define MPQ7920_REG_CTL2 0x02 15*4882a593Smuzhiyun #define MPQ7920_BUCK1_REG_A 0x03 16*4882a593Smuzhiyun #define MPQ7920_BUCK1_REG_B 0x04 17*4882a593Smuzhiyun #define MPQ7920_BUCK1_REG_C 0x05 18*4882a593Smuzhiyun #define MPQ7920_BUCK1_REG_D 0x06 19*4882a593Smuzhiyun #define MPQ7920_BUCK2_REG_A 0x07 20*4882a593Smuzhiyun #define MPQ7920_BUCK2_REG_B 0x08 21*4882a593Smuzhiyun #define MPQ7920_BUCK2_REG_C 0x09 22*4882a593Smuzhiyun #define MPQ7920_BUCK2_REG_D 0x0a 23*4882a593Smuzhiyun #define MPQ7920_BUCK3_REG_A 0x0b 24*4882a593Smuzhiyun #define MPQ7920_BUCK3_REG_B 0x0c 25*4882a593Smuzhiyun #define MPQ7920_BUCK3_REG_C 0x0d 26*4882a593Smuzhiyun #define MPQ7920_BUCK3_REG_D 0x0e 27*4882a593Smuzhiyun #define MPQ7920_BUCK4_REG_A 0x0f 28*4882a593Smuzhiyun #define MPQ7920_BUCK4_REG_B 0x10 29*4882a593Smuzhiyun #define MPQ7920_BUCK4_REG_C 0x11 30*4882a593Smuzhiyun #define MPQ7920_BUCK4_REG_D 0x12 31*4882a593Smuzhiyun #define MPQ7920_LDO1_REG_A 0x13 32*4882a593Smuzhiyun #define MPQ7920_LDO1_REG_B 0x0 33*4882a593Smuzhiyun #define MPQ7920_LDO2_REG_A 0x14 34*4882a593Smuzhiyun #define MPQ7920_LDO2_REG_B 0x15 35*4882a593Smuzhiyun #define MPQ7920_LDO2_REG_C 0x16 36*4882a593Smuzhiyun #define MPQ7920_LDO3_REG_A 0x17 37*4882a593Smuzhiyun #define MPQ7920_LDO3_REG_B 0x18 38*4882a593Smuzhiyun #define MPQ7920_LDO3_REG_C 0x19 39*4882a593Smuzhiyun #define MPQ7920_LDO4_REG_A 0x1a 40*4882a593Smuzhiyun #define MPQ7920_LDO4_REG_B 0x1b 41*4882a593Smuzhiyun #define MPQ7920_LDO4_REG_C 0x1c 42*4882a593Smuzhiyun #define MPQ7920_LDO5_REG_A 0x1d 43*4882a593Smuzhiyun #define MPQ7920_LDO5_REG_B 0x1e 44*4882a593Smuzhiyun #define MPQ7920_LDO5_REG_C 0x1f 45*4882a593Smuzhiyun #define MPQ7920_REG_MODE 0x20 46*4882a593Smuzhiyun #define MPQ7920_REG_REGULATOR_EN 0x22 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define MPQ7920_MASK_VREF 0x7f 49*4882a593Smuzhiyun #define MPQ7920_MASK_BUCK_ILIM 0xc0 50*4882a593Smuzhiyun #define MPQ7920_MASK_LDO_ILIM BIT(6) 51*4882a593Smuzhiyun #define MPQ7920_MASK_DISCHARGE BIT(5) 52*4882a593Smuzhiyun #define MPQ7920_MASK_MODE 0xc0 53*4882a593Smuzhiyun #define MPQ7920_MASK_SOFTSTART 0x0c 54*4882a593Smuzhiyun #define MPQ7920_MASK_SWITCH_FREQ 0x30 55*4882a593Smuzhiyun #define MPQ7920_MASK_BUCK_PHASE_DEALY 0x30 56*4882a593Smuzhiyun #define MPQ7920_MASK_DVS_SLEWRATE 0xc0 57*4882a593Smuzhiyun #define MPQ7920_MASK_OVP 0x40 58*4882a593Smuzhiyun #define MPQ7920_OVP_DISABLE ~(0x40) 59*4882a593Smuzhiyun #define MPQ7920_DISCHARGE_ON BIT(5) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define MPQ7920_REGULATOR_EN_OFFSET 7 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* values in mV */ 64*4882a593Smuzhiyun #define MPQ7920_BUCK_VOLT_MIN 400000 65*4882a593Smuzhiyun #define MPQ7920_LDO_VOLT_MIN 650000 66*4882a593Smuzhiyun #define MPQ7920_VOLT_MAX 3587500 67*4882a593Smuzhiyun #define MPQ7920_VOLT_STEP 12500 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* __MPQ7920_H__ */ 70