1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * max8973-regulator.c -- Maxim max8973
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Regulator driver for MAXIM 8973 DC-DC step-down switching regulator.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (c) 2012, NVIDIA Corporation.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Laxman Dewangan <ldewangan@nvidia.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
11*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
12*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
15*4882a593Smuzhiyun * whether express or implied; without even the implied warranty of
16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17*4882a593Smuzhiyun * General Public License for more details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
20*4882a593Smuzhiyun * along with this program; if not, write to the Free Software
21*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
22*4882a593Smuzhiyun * 02111-1307, USA
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <linux/kernel.h>
26*4882a593Smuzhiyun #include <linux/module.h>
27*4882a593Smuzhiyun #include <linux/init.h>
28*4882a593Smuzhiyun #include <linux/err.h>
29*4882a593Smuzhiyun #include <linux/of.h>
30*4882a593Smuzhiyun #include <linux/of_device.h>
31*4882a593Smuzhiyun #include <linux/platform_device.h>
32*4882a593Smuzhiyun #include <linux/regulator/driver.h>
33*4882a593Smuzhiyun #include <linux/regulator/machine.h>
34*4882a593Smuzhiyun #include <linux/regulator/max8973-regulator.h>
35*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
36*4882a593Smuzhiyun #include <linux/gpio.h>
37*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
38*4882a593Smuzhiyun #include <linux/of_gpio.h>
39*4882a593Smuzhiyun #include <linux/i2c.h>
40*4882a593Smuzhiyun #include <linux/slab.h>
41*4882a593Smuzhiyun #include <linux/regmap.h>
42*4882a593Smuzhiyun #include <linux/thermal.h>
43*4882a593Smuzhiyun #include <linux/irq.h>
44*4882a593Smuzhiyun #include <linux/interrupt.h>
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Register definitions */
47*4882a593Smuzhiyun #define MAX8973_VOUT 0x0
48*4882a593Smuzhiyun #define MAX8973_VOUT_DVS 0x1
49*4882a593Smuzhiyun #define MAX8973_CONTROL1 0x2
50*4882a593Smuzhiyun #define MAX8973_CONTROL2 0x3
51*4882a593Smuzhiyun #define MAX8973_CHIPID1 0x4
52*4882a593Smuzhiyun #define MAX8973_CHIPID2 0x5
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define MAX8973_MAX_VOUT_REG 2
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* MAX8973_VOUT */
57*4882a593Smuzhiyun #define MAX8973_VOUT_ENABLE BIT(7)
58*4882a593Smuzhiyun #define MAX8973_VOUT_MASK 0x7F
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* MAX8973_VOUT_DVS */
61*4882a593Smuzhiyun #define MAX8973_DVS_VOUT_MASK 0x7F
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* MAX8973_CONTROL1 */
64*4882a593Smuzhiyun #define MAX8973_SNS_ENABLE BIT(7)
65*4882a593Smuzhiyun #define MAX8973_FPWM_EN_M BIT(6)
66*4882a593Smuzhiyun #define MAX8973_NFSR_ENABLE BIT(5)
67*4882a593Smuzhiyun #define MAX8973_AD_ENABLE BIT(4)
68*4882a593Smuzhiyun #define MAX8973_BIAS_ENABLE BIT(3)
69*4882a593Smuzhiyun #define MAX8973_FREQSHIFT_9PER BIT(2)
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define MAX8973_RAMP_12mV_PER_US 0x0
72*4882a593Smuzhiyun #define MAX8973_RAMP_25mV_PER_US 0x1
73*4882a593Smuzhiyun #define MAX8973_RAMP_50mV_PER_US 0x2
74*4882a593Smuzhiyun #define MAX8973_RAMP_200mV_PER_US 0x3
75*4882a593Smuzhiyun #define MAX8973_RAMP_MASK 0x3
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* MAX8973_CONTROL2 */
78*4882a593Smuzhiyun #define MAX8973_WDTMR_ENABLE BIT(6)
79*4882a593Smuzhiyun #define MAX8973_DISCH_ENBABLE BIT(5)
80*4882a593Smuzhiyun #define MAX8973_FT_ENABLE BIT(4)
81*4882a593Smuzhiyun #define MAX77621_T_JUNCTION_120 BIT(7)
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define MAX8973_CKKADV_TRIP_MASK 0xC
84*4882a593Smuzhiyun #define MAX8973_CKKADV_TRIP_DISABLE 0xC
85*4882a593Smuzhiyun #define MAX8973_CKKADV_TRIP_75mV_PER_US 0x0
86*4882a593Smuzhiyun #define MAX8973_CKKADV_TRIP_150mV_PER_US 0x4
87*4882a593Smuzhiyun #define MAX8973_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8
88*4882a593Smuzhiyun #define MAX8973_CONTROL_CLKADV_TRIP_MASK 0x00030000
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define MAX8973_INDUCTOR_MIN_30_PER 0x0
91*4882a593Smuzhiyun #define MAX8973_INDUCTOR_NOMINAL 0x1
92*4882a593Smuzhiyun #define MAX8973_INDUCTOR_PLUS_30_PER 0x2
93*4882a593Smuzhiyun #define MAX8973_INDUCTOR_PLUS_60_PER 0x3
94*4882a593Smuzhiyun #define MAX8973_CONTROL_INDUCTOR_VALUE_MASK 0x00300000
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define MAX8973_MIN_VOLATGE 606250
97*4882a593Smuzhiyun #define MAX8973_MAX_VOLATGE 1400000
98*4882a593Smuzhiyun #define MAX8973_VOLATGE_STEP 6250
99*4882a593Smuzhiyun #define MAX8973_BUCK_N_VOLTAGE 0x80
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define MAX77621_CHIPID_TJINT_S BIT(0)
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define MAX77621_NORMAL_OPERATING_TEMP 100000
104*4882a593Smuzhiyun #define MAX77621_TJINT_WARNING_TEMP_120 120000
105*4882a593Smuzhiyun #define MAX77621_TJINT_WARNING_TEMP_140 140000
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun enum device_id {
108*4882a593Smuzhiyun MAX8973,
109*4882a593Smuzhiyun MAX77621
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* Maxim 8973 chip information */
113*4882a593Smuzhiyun struct max8973_chip {
114*4882a593Smuzhiyun struct device *dev;
115*4882a593Smuzhiyun struct regulator_desc desc;
116*4882a593Smuzhiyun struct regmap *regmap;
117*4882a593Smuzhiyun bool enable_external_control;
118*4882a593Smuzhiyun int dvs_gpio;
119*4882a593Smuzhiyun int lru_index[MAX8973_MAX_VOUT_REG];
120*4882a593Smuzhiyun int curr_vout_val[MAX8973_MAX_VOUT_REG];
121*4882a593Smuzhiyun int curr_vout_reg;
122*4882a593Smuzhiyun int curr_gpio_val;
123*4882a593Smuzhiyun struct regulator_ops ops;
124*4882a593Smuzhiyun enum device_id id;
125*4882a593Smuzhiyun int junction_temp_warning;
126*4882a593Smuzhiyun int irq;
127*4882a593Smuzhiyun struct thermal_zone_device *tz_device;
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /*
131*4882a593Smuzhiyun * find_voltage_set_register: Find new voltage configuration register (VOUT).
132*4882a593Smuzhiyun * The finding of the new VOUT register will be based on the LRU mechanism.
133*4882a593Smuzhiyun * Each VOUT register will have different voltage configured . This
134*4882a593Smuzhiyun * Function will look if any of the VOUT register have requested voltage set
135*4882a593Smuzhiyun * or not.
136*4882a593Smuzhiyun * - If it is already there then it will make that register as most
137*4882a593Smuzhiyun * recently used and return as found so that caller need not to set
138*4882a593Smuzhiyun * the VOUT register but need to set the proper gpios to select this
139*4882a593Smuzhiyun * VOUT register.
140*4882a593Smuzhiyun * - If requested voltage is not found then it will use the least
141*4882a593Smuzhiyun * recently mechanism to get new VOUT register for new configuration
142*4882a593Smuzhiyun * and will return not_found so that caller need to set new VOUT
143*4882a593Smuzhiyun * register and then gpios (both).
144*4882a593Smuzhiyun */
find_voltage_set_register(struct max8973_chip * tps,int req_vsel,int * vout_reg,int * gpio_val)145*4882a593Smuzhiyun static bool find_voltage_set_register(struct max8973_chip *tps,
146*4882a593Smuzhiyun int req_vsel, int *vout_reg, int *gpio_val)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun int i;
149*4882a593Smuzhiyun bool found = false;
150*4882a593Smuzhiyun int new_vout_reg = tps->lru_index[MAX8973_MAX_VOUT_REG - 1];
151*4882a593Smuzhiyun int found_index = MAX8973_MAX_VOUT_REG - 1;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun for (i = 0; i < MAX8973_MAX_VOUT_REG; ++i) {
154*4882a593Smuzhiyun if (tps->curr_vout_val[tps->lru_index[i]] == req_vsel) {
155*4882a593Smuzhiyun new_vout_reg = tps->lru_index[i];
156*4882a593Smuzhiyun found_index = i;
157*4882a593Smuzhiyun found = true;
158*4882a593Smuzhiyun goto update_lru_index;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun update_lru_index:
163*4882a593Smuzhiyun for (i = found_index; i > 0; i--)
164*4882a593Smuzhiyun tps->lru_index[i] = tps->lru_index[i - 1];
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun tps->lru_index[0] = new_vout_reg;
167*4882a593Smuzhiyun *gpio_val = new_vout_reg;
168*4882a593Smuzhiyun *vout_reg = MAX8973_VOUT + new_vout_reg;
169*4882a593Smuzhiyun return found;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
max8973_dcdc_get_voltage_sel(struct regulator_dev * rdev)172*4882a593Smuzhiyun static int max8973_dcdc_get_voltage_sel(struct regulator_dev *rdev)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun struct max8973_chip *max = rdev_get_drvdata(rdev);
175*4882a593Smuzhiyun unsigned int data;
176*4882a593Smuzhiyun int ret;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ret = regmap_read(max->regmap, max->curr_vout_reg, &data);
179*4882a593Smuzhiyun if (ret < 0) {
180*4882a593Smuzhiyun dev_err(max->dev, "register %d read failed, err = %d\n",
181*4882a593Smuzhiyun max->curr_vout_reg, ret);
182*4882a593Smuzhiyun return ret;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun return data & MAX8973_VOUT_MASK;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
max8973_dcdc_set_voltage_sel(struct regulator_dev * rdev,unsigned vsel)187*4882a593Smuzhiyun static int max8973_dcdc_set_voltage_sel(struct regulator_dev *rdev,
188*4882a593Smuzhiyun unsigned vsel)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun struct max8973_chip *max = rdev_get_drvdata(rdev);
191*4882a593Smuzhiyun int ret;
192*4882a593Smuzhiyun bool found = false;
193*4882a593Smuzhiyun int vout_reg = max->curr_vout_reg;
194*4882a593Smuzhiyun int gpio_val = max->curr_gpio_val;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /*
197*4882a593Smuzhiyun * If gpios are available to select the VOUT register then least
198*4882a593Smuzhiyun * recently used register for new configuration.
199*4882a593Smuzhiyun */
200*4882a593Smuzhiyun if (gpio_is_valid(max->dvs_gpio))
201*4882a593Smuzhiyun found = find_voltage_set_register(max, vsel,
202*4882a593Smuzhiyun &vout_reg, &gpio_val);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun if (!found) {
205*4882a593Smuzhiyun ret = regmap_update_bits(max->regmap, vout_reg,
206*4882a593Smuzhiyun MAX8973_VOUT_MASK, vsel);
207*4882a593Smuzhiyun if (ret < 0) {
208*4882a593Smuzhiyun dev_err(max->dev, "register %d update failed, err %d\n",
209*4882a593Smuzhiyun vout_reg, ret);
210*4882a593Smuzhiyun return ret;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun max->curr_vout_reg = vout_reg;
213*4882a593Smuzhiyun max->curr_vout_val[gpio_val] = vsel;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun /* Select proper VOUT register vio gpios */
217*4882a593Smuzhiyun if (gpio_is_valid(max->dvs_gpio)) {
218*4882a593Smuzhiyun gpio_set_value_cansleep(max->dvs_gpio, gpio_val & 0x1);
219*4882a593Smuzhiyun max->curr_gpio_val = gpio_val;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun return 0;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
max8973_dcdc_set_mode(struct regulator_dev * rdev,unsigned int mode)224*4882a593Smuzhiyun static int max8973_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun struct max8973_chip *max = rdev_get_drvdata(rdev);
227*4882a593Smuzhiyun int ret;
228*4882a593Smuzhiyun int pwm;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /* Enable force PWM mode in FAST mode only. */
231*4882a593Smuzhiyun switch (mode) {
232*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
233*4882a593Smuzhiyun pwm = MAX8973_FPWM_EN_M;
234*4882a593Smuzhiyun break;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
237*4882a593Smuzhiyun pwm = 0;
238*4882a593Smuzhiyun break;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun default:
241*4882a593Smuzhiyun return -EINVAL;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun ret = regmap_update_bits(max->regmap, MAX8973_CONTROL1,
245*4882a593Smuzhiyun MAX8973_FPWM_EN_M, pwm);
246*4882a593Smuzhiyun if (ret < 0)
247*4882a593Smuzhiyun dev_err(max->dev, "register %d update failed, err %d\n",
248*4882a593Smuzhiyun MAX8973_CONTROL1, ret);
249*4882a593Smuzhiyun return ret;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
max8973_dcdc_get_mode(struct regulator_dev * rdev)252*4882a593Smuzhiyun static unsigned int max8973_dcdc_get_mode(struct regulator_dev *rdev)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun struct max8973_chip *max = rdev_get_drvdata(rdev);
255*4882a593Smuzhiyun unsigned int data;
256*4882a593Smuzhiyun int ret;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun ret = regmap_read(max->regmap, MAX8973_CONTROL1, &data);
259*4882a593Smuzhiyun if (ret < 0) {
260*4882a593Smuzhiyun dev_err(max->dev, "register %d read failed, err %d\n",
261*4882a593Smuzhiyun MAX8973_CONTROL1, ret);
262*4882a593Smuzhiyun return ret;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun return (data & MAX8973_FPWM_EN_M) ?
265*4882a593Smuzhiyun REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
max8973_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)268*4882a593Smuzhiyun static int max8973_set_ramp_delay(struct regulator_dev *rdev,
269*4882a593Smuzhiyun int ramp_delay)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct max8973_chip *max = rdev_get_drvdata(rdev);
272*4882a593Smuzhiyun unsigned int control;
273*4882a593Smuzhiyun int ret;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /* Set ramp delay */
276*4882a593Smuzhiyun if (ramp_delay <= 12000)
277*4882a593Smuzhiyun control = MAX8973_RAMP_12mV_PER_US;
278*4882a593Smuzhiyun else if (ramp_delay <= 25000)
279*4882a593Smuzhiyun control = MAX8973_RAMP_25mV_PER_US;
280*4882a593Smuzhiyun else if (ramp_delay <= 50000)
281*4882a593Smuzhiyun control = MAX8973_RAMP_50mV_PER_US;
282*4882a593Smuzhiyun else if (ramp_delay <= 200000)
283*4882a593Smuzhiyun control = MAX8973_RAMP_200mV_PER_US;
284*4882a593Smuzhiyun else
285*4882a593Smuzhiyun return -EINVAL;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun ret = regmap_update_bits(max->regmap, MAX8973_CONTROL1,
288*4882a593Smuzhiyun MAX8973_RAMP_MASK, control);
289*4882a593Smuzhiyun if (ret < 0)
290*4882a593Smuzhiyun dev_err(max->dev, "register %d update failed, %d",
291*4882a593Smuzhiyun MAX8973_CONTROL1, ret);
292*4882a593Smuzhiyun return ret;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
max8973_set_current_limit(struct regulator_dev * rdev,int min_ua,int max_ua)295*4882a593Smuzhiyun static int max8973_set_current_limit(struct regulator_dev *rdev,
296*4882a593Smuzhiyun int min_ua, int max_ua)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun struct max8973_chip *max = rdev_get_drvdata(rdev);
299*4882a593Smuzhiyun unsigned int val;
300*4882a593Smuzhiyun int ret;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun if (max_ua <= 9000000)
303*4882a593Smuzhiyun val = MAX8973_CKKADV_TRIP_75mV_PER_US;
304*4882a593Smuzhiyun else if (max_ua <= 12000000)
305*4882a593Smuzhiyun val = MAX8973_CKKADV_TRIP_150mV_PER_US;
306*4882a593Smuzhiyun else
307*4882a593Smuzhiyun val = MAX8973_CKKADV_TRIP_DISABLE;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun ret = regmap_update_bits(max->regmap, MAX8973_CONTROL2,
310*4882a593Smuzhiyun MAX8973_CKKADV_TRIP_MASK, val);
311*4882a593Smuzhiyun if (ret < 0) {
312*4882a593Smuzhiyun dev_err(max->dev, "register %d update failed: %d\n",
313*4882a593Smuzhiyun MAX8973_CONTROL2, ret);
314*4882a593Smuzhiyun return ret;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
max8973_get_current_limit(struct regulator_dev * rdev)319*4882a593Smuzhiyun static int max8973_get_current_limit(struct regulator_dev *rdev)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun struct max8973_chip *max = rdev_get_drvdata(rdev);
322*4882a593Smuzhiyun unsigned int control2;
323*4882a593Smuzhiyun int ret;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun ret = regmap_read(max->regmap, MAX8973_CONTROL2, &control2);
326*4882a593Smuzhiyun if (ret < 0) {
327*4882a593Smuzhiyun dev_err(max->dev, "register %d read failed: %d\n",
328*4882a593Smuzhiyun MAX8973_CONTROL2, ret);
329*4882a593Smuzhiyun return ret;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun switch (control2 & MAX8973_CKKADV_TRIP_MASK) {
332*4882a593Smuzhiyun case MAX8973_CKKADV_TRIP_DISABLE:
333*4882a593Smuzhiyun return 15000000;
334*4882a593Smuzhiyun case MAX8973_CKKADV_TRIP_150mV_PER_US:
335*4882a593Smuzhiyun return 12000000;
336*4882a593Smuzhiyun case MAX8973_CKKADV_TRIP_75mV_PER_US:
337*4882a593Smuzhiyun return 9000000;
338*4882a593Smuzhiyun default:
339*4882a593Smuzhiyun break;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun return 9000000;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun static const struct regulator_ops max8973_dcdc_ops = {
345*4882a593Smuzhiyun .get_voltage_sel = max8973_dcdc_get_voltage_sel,
346*4882a593Smuzhiyun .set_voltage_sel = max8973_dcdc_set_voltage_sel,
347*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
348*4882a593Smuzhiyun .set_mode = max8973_dcdc_set_mode,
349*4882a593Smuzhiyun .get_mode = max8973_dcdc_get_mode,
350*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
351*4882a593Smuzhiyun .set_ramp_delay = max8973_set_ramp_delay,
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun
max8973_init_dcdc(struct max8973_chip * max,struct max8973_regulator_platform_data * pdata)354*4882a593Smuzhiyun static int max8973_init_dcdc(struct max8973_chip *max,
355*4882a593Smuzhiyun struct max8973_regulator_platform_data *pdata)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun int ret;
358*4882a593Smuzhiyun uint8_t control1 = 0;
359*4882a593Smuzhiyun uint8_t control2 = 0;
360*4882a593Smuzhiyun unsigned int data;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun ret = regmap_read(max->regmap, MAX8973_CONTROL1, &data);
363*4882a593Smuzhiyun if (ret < 0) {
364*4882a593Smuzhiyun dev_err(max->dev, "register %d read failed, err = %d",
365*4882a593Smuzhiyun MAX8973_CONTROL1, ret);
366*4882a593Smuzhiyun return ret;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun control1 = data & MAX8973_RAMP_MASK;
369*4882a593Smuzhiyun switch (control1) {
370*4882a593Smuzhiyun case MAX8973_RAMP_12mV_PER_US:
371*4882a593Smuzhiyun max->desc.ramp_delay = 12000;
372*4882a593Smuzhiyun break;
373*4882a593Smuzhiyun case MAX8973_RAMP_25mV_PER_US:
374*4882a593Smuzhiyun max->desc.ramp_delay = 25000;
375*4882a593Smuzhiyun break;
376*4882a593Smuzhiyun case MAX8973_RAMP_50mV_PER_US:
377*4882a593Smuzhiyun max->desc.ramp_delay = 50000;
378*4882a593Smuzhiyun break;
379*4882a593Smuzhiyun case MAX8973_RAMP_200mV_PER_US:
380*4882a593Smuzhiyun max->desc.ramp_delay = 200000;
381*4882a593Smuzhiyun break;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun if (pdata->control_flags & MAX8973_CONTROL_REMOTE_SENSE_ENABLE)
385*4882a593Smuzhiyun control1 |= MAX8973_SNS_ENABLE;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun if (!(pdata->control_flags & MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE))
388*4882a593Smuzhiyun control1 |= MAX8973_NFSR_ENABLE;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun if (pdata->control_flags & MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE)
391*4882a593Smuzhiyun control1 |= MAX8973_AD_ENABLE;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun if (pdata->control_flags & MAX8973_CONTROL_BIAS_ENABLE) {
394*4882a593Smuzhiyun control1 |= MAX8973_BIAS_ENABLE;
395*4882a593Smuzhiyun max->desc.enable_time = 20;
396*4882a593Smuzhiyun } else {
397*4882a593Smuzhiyun max->desc.enable_time = 240;
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun if (pdata->control_flags & MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE)
401*4882a593Smuzhiyun control1 |= MAX8973_FREQSHIFT_9PER;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun if ((pdata->junction_temp_warning == MAX77621_TJINT_WARNING_TEMP_120) &&
404*4882a593Smuzhiyun (max->id == MAX77621))
405*4882a593Smuzhiyun control2 |= MAX77621_T_JUNCTION_120;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (!(pdata->control_flags & MAX8973_CONTROL_PULL_DOWN_ENABLE))
408*4882a593Smuzhiyun control2 |= MAX8973_DISCH_ENBABLE;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* Clock advance trip configuration */
411*4882a593Smuzhiyun switch (pdata->control_flags & MAX8973_CONTROL_CLKADV_TRIP_MASK) {
412*4882a593Smuzhiyun case MAX8973_CONTROL_CLKADV_TRIP_DISABLED:
413*4882a593Smuzhiyun control2 |= MAX8973_CKKADV_TRIP_DISABLE;
414*4882a593Smuzhiyun break;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun case MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US:
417*4882a593Smuzhiyun control2 |= MAX8973_CKKADV_TRIP_75mV_PER_US;
418*4882a593Smuzhiyun break;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun case MAX8973_CONTROL_CLKADV_TRIP_150mV_PER_US:
421*4882a593Smuzhiyun control2 |= MAX8973_CKKADV_TRIP_150mV_PER_US;
422*4882a593Smuzhiyun break;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun case MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US_HIST_DIS:
425*4882a593Smuzhiyun control2 |= MAX8973_CKKADV_TRIP_75mV_PER_US_HIST_DIS;
426*4882a593Smuzhiyun break;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* Configure inductor value */
430*4882a593Smuzhiyun switch (pdata->control_flags & MAX8973_CONTROL_INDUCTOR_VALUE_MASK) {
431*4882a593Smuzhiyun case MAX8973_CONTROL_INDUCTOR_VALUE_NOMINAL:
432*4882a593Smuzhiyun control2 |= MAX8973_INDUCTOR_NOMINAL;
433*4882a593Smuzhiyun break;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun case MAX8973_CONTROL_INDUCTOR_VALUE_MINUS_30_PER:
436*4882a593Smuzhiyun control2 |= MAX8973_INDUCTOR_MIN_30_PER;
437*4882a593Smuzhiyun break;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun case MAX8973_CONTROL_INDUCTOR_VALUE_PLUS_30_PER:
440*4882a593Smuzhiyun control2 |= MAX8973_INDUCTOR_PLUS_30_PER;
441*4882a593Smuzhiyun break;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun case MAX8973_CONTROL_INDUCTOR_VALUE_PLUS_60_PER:
444*4882a593Smuzhiyun control2 |= MAX8973_INDUCTOR_PLUS_60_PER;
445*4882a593Smuzhiyun break;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun ret = regmap_write(max->regmap, MAX8973_CONTROL1, control1);
449*4882a593Smuzhiyun if (ret < 0) {
450*4882a593Smuzhiyun dev_err(max->dev, "register %d write failed, err = %d",
451*4882a593Smuzhiyun MAX8973_CONTROL1, ret);
452*4882a593Smuzhiyun return ret;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun ret = regmap_write(max->regmap, MAX8973_CONTROL2, control2);
456*4882a593Smuzhiyun if (ret < 0) {
457*4882a593Smuzhiyun dev_err(max->dev, "register %d write failed, err = %d",
458*4882a593Smuzhiyun MAX8973_CONTROL2, ret);
459*4882a593Smuzhiyun return ret;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /* If external control is enabled then disable EN bit */
463*4882a593Smuzhiyun if (max->enable_external_control && (max->id == MAX8973)) {
464*4882a593Smuzhiyun ret = regmap_update_bits(max->regmap, MAX8973_VOUT,
465*4882a593Smuzhiyun MAX8973_VOUT_ENABLE, 0);
466*4882a593Smuzhiyun if (ret < 0)
467*4882a593Smuzhiyun dev_err(max->dev, "register %d update failed, err = %d",
468*4882a593Smuzhiyun MAX8973_VOUT, ret);
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun return ret;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
max8973_thermal_read_temp(void * data,int * temp)473*4882a593Smuzhiyun static int max8973_thermal_read_temp(void *data, int *temp)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun struct max8973_chip *mchip = data;
476*4882a593Smuzhiyun unsigned int val;
477*4882a593Smuzhiyun int ret;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun ret = regmap_read(mchip->regmap, MAX8973_CHIPID1, &val);
480*4882a593Smuzhiyun if (ret < 0) {
481*4882a593Smuzhiyun dev_err(mchip->dev, "Failed to read register CHIPID1, %d", ret);
482*4882a593Smuzhiyun return ret;
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* +1 degC to trigger cool devive */
486*4882a593Smuzhiyun if (val & MAX77621_CHIPID_TJINT_S)
487*4882a593Smuzhiyun *temp = mchip->junction_temp_warning + 1000;
488*4882a593Smuzhiyun else
489*4882a593Smuzhiyun *temp = MAX77621_NORMAL_OPERATING_TEMP;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun return 0;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
max8973_thermal_irq(int irq,void * data)494*4882a593Smuzhiyun static irqreturn_t max8973_thermal_irq(int irq, void *data)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun struct max8973_chip *mchip = data;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun thermal_zone_device_update(mchip->tz_device,
499*4882a593Smuzhiyun THERMAL_EVENT_UNSPECIFIED);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun return IRQ_HANDLED;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun static const struct thermal_zone_of_device_ops max77621_tz_ops = {
505*4882a593Smuzhiyun .get_temp = max8973_thermal_read_temp,
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun
max8973_thermal_init(struct max8973_chip * mchip)508*4882a593Smuzhiyun static int max8973_thermal_init(struct max8973_chip *mchip)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun struct thermal_zone_device *tzd;
511*4882a593Smuzhiyun struct irq_data *irq_data;
512*4882a593Smuzhiyun unsigned long irq_flags = 0;
513*4882a593Smuzhiyun int ret;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun if (mchip->id != MAX77621)
516*4882a593Smuzhiyun return 0;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun tzd = devm_thermal_zone_of_sensor_register(mchip->dev, 0, mchip,
519*4882a593Smuzhiyun &max77621_tz_ops);
520*4882a593Smuzhiyun if (IS_ERR(tzd)) {
521*4882a593Smuzhiyun ret = PTR_ERR(tzd);
522*4882a593Smuzhiyun dev_err(mchip->dev, "Failed to register thermal sensor: %d\n",
523*4882a593Smuzhiyun ret);
524*4882a593Smuzhiyun return ret;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun if (mchip->irq <= 0)
528*4882a593Smuzhiyun return 0;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun irq_data = irq_get_irq_data(mchip->irq);
531*4882a593Smuzhiyun if (irq_data)
532*4882a593Smuzhiyun irq_flags = irqd_get_trigger_type(irq_data);
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun ret = devm_request_threaded_irq(mchip->dev, mchip->irq, NULL,
535*4882a593Smuzhiyun max8973_thermal_irq,
536*4882a593Smuzhiyun IRQF_ONESHOT | IRQF_SHARED | irq_flags,
537*4882a593Smuzhiyun dev_name(mchip->dev), mchip);
538*4882a593Smuzhiyun if (ret < 0) {
539*4882a593Smuzhiyun dev_err(mchip->dev, "Failed to request irq %d, %d\n",
540*4882a593Smuzhiyun mchip->irq, ret);
541*4882a593Smuzhiyun return ret;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun return 0;
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun static const struct regmap_config max8973_regmap_config = {
548*4882a593Smuzhiyun .reg_bits = 8,
549*4882a593Smuzhiyun .val_bits = 8,
550*4882a593Smuzhiyun .max_register = MAX8973_CHIPID2,
551*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
552*4882a593Smuzhiyun };
553*4882a593Smuzhiyun
max8973_parse_dt(struct device * dev)554*4882a593Smuzhiyun static struct max8973_regulator_platform_data *max8973_parse_dt(
555*4882a593Smuzhiyun struct device *dev)
556*4882a593Smuzhiyun {
557*4882a593Smuzhiyun struct max8973_regulator_platform_data *pdata;
558*4882a593Smuzhiyun struct device_node *np = dev->of_node;
559*4882a593Smuzhiyun int ret;
560*4882a593Smuzhiyun u32 pval;
561*4882a593Smuzhiyun bool etr_enable;
562*4882a593Smuzhiyun bool etr_sensitivity_high;
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
565*4882a593Smuzhiyun if (!pdata)
566*4882a593Smuzhiyun return NULL;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun pdata->enable_ext_control = of_property_read_bool(np,
569*4882a593Smuzhiyun "maxim,externally-enable");
570*4882a593Smuzhiyun pdata->dvs_gpio = of_get_named_gpio(np, "maxim,dvs-gpio", 0);
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun ret = of_property_read_u32(np, "maxim,dvs-default-state", &pval);
573*4882a593Smuzhiyun if (!ret)
574*4882a593Smuzhiyun pdata->dvs_def_state = pval;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun if (of_property_read_bool(np, "maxim,enable-remote-sense"))
577*4882a593Smuzhiyun pdata->control_flags |= MAX8973_CONTROL_REMOTE_SENSE_ENABLE;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun if (of_property_read_bool(np, "maxim,enable-falling-slew-rate"))
580*4882a593Smuzhiyun pdata->control_flags |=
581*4882a593Smuzhiyun MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun if (of_property_read_bool(np, "maxim,enable-active-discharge"))
584*4882a593Smuzhiyun pdata->control_flags |=
585*4882a593Smuzhiyun MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun if (of_property_read_bool(np, "maxim,enable-frequency-shift"))
588*4882a593Smuzhiyun pdata->control_flags |= MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun if (of_property_read_bool(np, "maxim,enable-bias-control"))
591*4882a593Smuzhiyun pdata->control_flags |= MAX8973_CONTROL_BIAS_ENABLE;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun etr_enable = of_property_read_bool(np, "maxim,enable-etr");
594*4882a593Smuzhiyun etr_sensitivity_high = of_property_read_bool(np,
595*4882a593Smuzhiyun "maxim,enable-high-etr-sensitivity");
596*4882a593Smuzhiyun if (etr_sensitivity_high)
597*4882a593Smuzhiyun etr_enable = true;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun if (etr_enable) {
600*4882a593Smuzhiyun if (etr_sensitivity_high)
601*4882a593Smuzhiyun pdata->control_flags |=
602*4882a593Smuzhiyun MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US;
603*4882a593Smuzhiyun else
604*4882a593Smuzhiyun pdata->control_flags |=
605*4882a593Smuzhiyun MAX8973_CONTROL_CLKADV_TRIP_150mV_PER_US;
606*4882a593Smuzhiyun } else {
607*4882a593Smuzhiyun pdata->control_flags |= MAX8973_CONTROL_CLKADV_TRIP_DISABLED;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun pdata->junction_temp_warning = MAX77621_TJINT_WARNING_TEMP_140;
611*4882a593Smuzhiyun ret = of_property_read_u32(np, "junction-warn-millicelsius", &pval);
612*4882a593Smuzhiyun if (!ret && (pval <= MAX77621_TJINT_WARNING_TEMP_120))
613*4882a593Smuzhiyun pdata->junction_temp_warning = MAX77621_TJINT_WARNING_TEMP_120;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun return pdata;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun static const struct of_device_id of_max8973_match_tbl[] = {
619*4882a593Smuzhiyun { .compatible = "maxim,max8973", .data = (void *)MAX8973, },
620*4882a593Smuzhiyun { .compatible = "maxim,max77621", .data = (void *)MAX77621, },
621*4882a593Smuzhiyun { },
622*4882a593Smuzhiyun };
623*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_max8973_match_tbl);
624*4882a593Smuzhiyun
max8973_probe(struct i2c_client * client,const struct i2c_device_id * id)625*4882a593Smuzhiyun static int max8973_probe(struct i2c_client *client,
626*4882a593Smuzhiyun const struct i2c_device_id *id)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun struct max8973_regulator_platform_data *pdata;
629*4882a593Smuzhiyun struct regulator_init_data *ridata;
630*4882a593Smuzhiyun struct regulator_config config = { };
631*4882a593Smuzhiyun struct regulator_dev *rdev;
632*4882a593Smuzhiyun struct max8973_chip *max;
633*4882a593Smuzhiyun bool pdata_from_dt = false;
634*4882a593Smuzhiyun unsigned int chip_id;
635*4882a593Smuzhiyun struct gpio_desc *gpiod;
636*4882a593Smuzhiyun enum gpiod_flags gflags;
637*4882a593Smuzhiyun int ret;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun pdata = dev_get_platdata(&client->dev);
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun if (!pdata && client->dev.of_node) {
642*4882a593Smuzhiyun pdata = max8973_parse_dt(&client->dev);
643*4882a593Smuzhiyun pdata_from_dt = true;
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun if (!pdata) {
647*4882a593Smuzhiyun dev_err(&client->dev, "No Platform data");
648*4882a593Smuzhiyun return -EIO;
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun if (pdata->dvs_gpio == -EPROBE_DEFER)
652*4882a593Smuzhiyun return -EPROBE_DEFER;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun max = devm_kzalloc(&client->dev, sizeof(*max), GFP_KERNEL);
655*4882a593Smuzhiyun if (!max)
656*4882a593Smuzhiyun return -ENOMEM;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun max->regmap = devm_regmap_init_i2c(client, &max8973_regmap_config);
659*4882a593Smuzhiyun if (IS_ERR(max->regmap)) {
660*4882a593Smuzhiyun ret = PTR_ERR(max->regmap);
661*4882a593Smuzhiyun dev_err(&client->dev, "regmap init failed, err %d\n", ret);
662*4882a593Smuzhiyun return ret;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun if (client->dev.of_node) {
666*4882a593Smuzhiyun const struct of_device_id *match;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun match = of_match_device(of_match_ptr(of_max8973_match_tbl),
669*4882a593Smuzhiyun &client->dev);
670*4882a593Smuzhiyun if (!match)
671*4882a593Smuzhiyun return -ENODATA;
672*4882a593Smuzhiyun max->id = (u32)((uintptr_t)match->data);
673*4882a593Smuzhiyun } else {
674*4882a593Smuzhiyun max->id = id->driver_data;
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun ret = regmap_read(max->regmap, MAX8973_CHIPID1, &chip_id);
678*4882a593Smuzhiyun if (ret < 0) {
679*4882a593Smuzhiyun dev_err(&client->dev, "register CHIPID1 read failed, %d", ret);
680*4882a593Smuzhiyun return ret;
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun dev_info(&client->dev, "CHIP-ID OTP: 0x%02x ID_M: 0x%02x\n",
684*4882a593Smuzhiyun (chip_id >> 4) & 0xF, (chip_id >> 1) & 0x7);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun i2c_set_clientdata(client, max);
687*4882a593Smuzhiyun max->ops = max8973_dcdc_ops;
688*4882a593Smuzhiyun max->dev = &client->dev;
689*4882a593Smuzhiyun max->desc.name = id->name;
690*4882a593Smuzhiyun max->desc.id = 0;
691*4882a593Smuzhiyun max->desc.ops = &max->ops;
692*4882a593Smuzhiyun max->desc.type = REGULATOR_VOLTAGE;
693*4882a593Smuzhiyun max->desc.owner = THIS_MODULE;
694*4882a593Smuzhiyun max->desc.min_uV = MAX8973_MIN_VOLATGE;
695*4882a593Smuzhiyun max->desc.uV_step = MAX8973_VOLATGE_STEP;
696*4882a593Smuzhiyun max->desc.n_voltages = MAX8973_BUCK_N_VOLTAGE;
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun max->dvs_gpio = (pdata->dvs_gpio) ? pdata->dvs_gpio : -EINVAL;
699*4882a593Smuzhiyun max->enable_external_control = pdata->enable_ext_control;
700*4882a593Smuzhiyun max->curr_gpio_val = pdata->dvs_def_state;
701*4882a593Smuzhiyun max->curr_vout_reg = MAX8973_VOUT + pdata->dvs_def_state;
702*4882a593Smuzhiyun max->junction_temp_warning = pdata->junction_temp_warning;
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun max->lru_index[0] = max->curr_vout_reg;
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun if (gpio_is_valid(max->dvs_gpio)) {
707*4882a593Smuzhiyun int gpio_flags;
708*4882a593Smuzhiyun int i;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun gpio_flags = (pdata->dvs_def_state) ?
711*4882a593Smuzhiyun GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
712*4882a593Smuzhiyun ret = devm_gpio_request_one(&client->dev, max->dvs_gpio,
713*4882a593Smuzhiyun gpio_flags, "max8973-dvs");
714*4882a593Smuzhiyun if (ret) {
715*4882a593Smuzhiyun dev_err(&client->dev,
716*4882a593Smuzhiyun "gpio_request for gpio %d failed, err = %d\n",
717*4882a593Smuzhiyun max->dvs_gpio, ret);
718*4882a593Smuzhiyun return ret;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun /*
722*4882a593Smuzhiyun * Initialize the lru index with vout_reg id
723*4882a593Smuzhiyun * The index 0 will be most recently used and
724*4882a593Smuzhiyun * set with the max->curr_vout_reg */
725*4882a593Smuzhiyun for (i = 0; i < MAX8973_MAX_VOUT_REG; ++i)
726*4882a593Smuzhiyun max->lru_index[i] = i;
727*4882a593Smuzhiyun max->lru_index[0] = max->curr_vout_reg;
728*4882a593Smuzhiyun max->lru_index[max->curr_vout_reg] = 0;
729*4882a593Smuzhiyun } else {
730*4882a593Smuzhiyun /*
731*4882a593Smuzhiyun * If there is no DVS GPIO, the VOUT register
732*4882a593Smuzhiyun * address is fixed.
733*4882a593Smuzhiyun */
734*4882a593Smuzhiyun max->ops.set_voltage_sel = regulator_set_voltage_sel_regmap;
735*4882a593Smuzhiyun max->ops.get_voltage_sel = regulator_get_voltage_sel_regmap;
736*4882a593Smuzhiyun max->desc.vsel_reg = max->curr_vout_reg;
737*4882a593Smuzhiyun max->desc.vsel_mask = MAX8973_VOUT_MASK;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun if (pdata_from_dt)
741*4882a593Smuzhiyun pdata->reg_init_data = of_get_regulator_init_data(&client->dev,
742*4882a593Smuzhiyun client->dev.of_node, &max->desc);
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun ridata = pdata->reg_init_data;
745*4882a593Smuzhiyun switch (max->id) {
746*4882a593Smuzhiyun case MAX8973:
747*4882a593Smuzhiyun if (!pdata->enable_ext_control) {
748*4882a593Smuzhiyun max->desc.enable_reg = MAX8973_VOUT;
749*4882a593Smuzhiyun max->desc.enable_mask = MAX8973_VOUT_ENABLE;
750*4882a593Smuzhiyun max->ops.enable = regulator_enable_regmap;
751*4882a593Smuzhiyun max->ops.disable = regulator_disable_regmap;
752*4882a593Smuzhiyun max->ops.is_enabled = regulator_is_enabled_regmap;
753*4882a593Smuzhiyun break;
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun if (ridata && (ridata->constraints.always_on ||
757*4882a593Smuzhiyun ridata->constraints.boot_on))
758*4882a593Smuzhiyun gflags = GPIOD_OUT_HIGH;
759*4882a593Smuzhiyun else
760*4882a593Smuzhiyun gflags = GPIOD_OUT_LOW;
761*4882a593Smuzhiyun gflags |= GPIOD_FLAGS_BIT_NONEXCLUSIVE;
762*4882a593Smuzhiyun gpiod = devm_gpiod_get_optional(&client->dev,
763*4882a593Smuzhiyun "maxim,enable",
764*4882a593Smuzhiyun gflags);
765*4882a593Smuzhiyun if (IS_ERR(gpiod))
766*4882a593Smuzhiyun return PTR_ERR(gpiod);
767*4882a593Smuzhiyun if (gpiod) {
768*4882a593Smuzhiyun config.ena_gpiod = gpiod;
769*4882a593Smuzhiyun max->enable_external_control = true;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun break;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun case MAX77621:
775*4882a593Smuzhiyun /*
776*4882a593Smuzhiyun * We do not let the core switch this regulator on/off,
777*4882a593Smuzhiyun * we just leave it on.
778*4882a593Smuzhiyun */
779*4882a593Smuzhiyun gpiod = devm_gpiod_get_optional(&client->dev,
780*4882a593Smuzhiyun "maxim,enable",
781*4882a593Smuzhiyun GPIOD_OUT_HIGH);
782*4882a593Smuzhiyun if (IS_ERR(gpiod))
783*4882a593Smuzhiyun return PTR_ERR(gpiod);
784*4882a593Smuzhiyun if (gpiod)
785*4882a593Smuzhiyun max->enable_external_control = true;
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun max->desc.enable_reg = MAX8973_VOUT;
788*4882a593Smuzhiyun max->desc.enable_mask = MAX8973_VOUT_ENABLE;
789*4882a593Smuzhiyun max->ops.enable = regulator_enable_regmap;
790*4882a593Smuzhiyun max->ops.disable = regulator_disable_regmap;
791*4882a593Smuzhiyun max->ops.is_enabled = regulator_is_enabled_regmap;
792*4882a593Smuzhiyun max->ops.set_current_limit = max8973_set_current_limit;
793*4882a593Smuzhiyun max->ops.get_current_limit = max8973_get_current_limit;
794*4882a593Smuzhiyun break;
795*4882a593Smuzhiyun default:
796*4882a593Smuzhiyun break;
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun ret = max8973_init_dcdc(max, pdata);
800*4882a593Smuzhiyun if (ret < 0) {
801*4882a593Smuzhiyun dev_err(max->dev, "Max8973 Init failed, err = %d\n", ret);
802*4882a593Smuzhiyun return ret;
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun config.dev = &client->dev;
806*4882a593Smuzhiyun config.init_data = pdata->reg_init_data;
807*4882a593Smuzhiyun config.driver_data = max;
808*4882a593Smuzhiyun config.of_node = client->dev.of_node;
809*4882a593Smuzhiyun config.regmap = max->regmap;
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun /*
812*4882a593Smuzhiyun * Register the regulators
813*4882a593Smuzhiyun * Turn the GPIO descriptor over to the regulator core for
814*4882a593Smuzhiyun * lifecycle management if we pass an ena_gpiod.
815*4882a593Smuzhiyun */
816*4882a593Smuzhiyun if (config.ena_gpiod)
817*4882a593Smuzhiyun devm_gpiod_unhinge(&client->dev, config.ena_gpiod);
818*4882a593Smuzhiyun rdev = devm_regulator_register(&client->dev, &max->desc, &config);
819*4882a593Smuzhiyun if (IS_ERR(rdev)) {
820*4882a593Smuzhiyun ret = PTR_ERR(rdev);
821*4882a593Smuzhiyun dev_err(max->dev, "regulator register failed, err %d\n", ret);
822*4882a593Smuzhiyun return ret;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun max8973_thermal_init(max);
826*4882a593Smuzhiyun return 0;
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun static const struct i2c_device_id max8973_id[] = {
830*4882a593Smuzhiyun {.name = "max8973", .driver_data = MAX8973},
831*4882a593Smuzhiyun {.name = "max77621", .driver_data = MAX77621},
832*4882a593Smuzhiyun {},
833*4882a593Smuzhiyun };
834*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max8973_id);
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun static struct i2c_driver max8973_i2c_driver = {
837*4882a593Smuzhiyun .driver = {
838*4882a593Smuzhiyun .name = "max8973",
839*4882a593Smuzhiyun .of_match_table = of_max8973_match_tbl,
840*4882a593Smuzhiyun },
841*4882a593Smuzhiyun .probe = max8973_probe,
842*4882a593Smuzhiyun .id_table = max8973_id,
843*4882a593Smuzhiyun };
844*4882a593Smuzhiyun
max8973_init(void)845*4882a593Smuzhiyun static int __init max8973_init(void)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun return i2c_add_driver(&max8973_i2c_driver);
848*4882a593Smuzhiyun }
849*4882a593Smuzhiyun subsys_initcall(max8973_init);
850*4882a593Smuzhiyun
max8973_cleanup(void)851*4882a593Smuzhiyun static void __exit max8973_cleanup(void)
852*4882a593Smuzhiyun {
853*4882a593Smuzhiyun i2c_del_driver(&max8973_i2c_driver);
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun module_exit(max8973_cleanup);
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
858*4882a593Smuzhiyun MODULE_DESCRIPTION("MAX8973 voltage regulator driver");
859*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
860