xref: /OK3568_Linux_fs/kernel/drivers/regulator/max8649.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Regulators driver for Maxim max8649
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2009-2010 Marvell International Ltd.
6*4882a593Smuzhiyun  *      Haojian Zhuang <haojian.zhuang@marvell.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/regulator/driver.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/regulator/max8649.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define MAX8649_DCDC_VMIN	750000		/* uV */
19*4882a593Smuzhiyun #define MAX8649_DCDC_VMAX	1380000		/* uV */
20*4882a593Smuzhiyun #define MAX8649_DCDC_STEP	10000		/* uV */
21*4882a593Smuzhiyun #define MAX8649_VOL_MASK	0x3f
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /* Registers */
24*4882a593Smuzhiyun #define MAX8649_MODE0		0x00
25*4882a593Smuzhiyun #define MAX8649_MODE1		0x01
26*4882a593Smuzhiyun #define MAX8649_MODE2		0x02
27*4882a593Smuzhiyun #define MAX8649_MODE3		0x03
28*4882a593Smuzhiyun #define MAX8649_CONTROL		0x04
29*4882a593Smuzhiyun #define MAX8649_SYNC		0x05
30*4882a593Smuzhiyun #define MAX8649_RAMP		0x06
31*4882a593Smuzhiyun #define MAX8649_CHIP_ID1	0x08
32*4882a593Smuzhiyun #define MAX8649_CHIP_ID2	0x09
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* Bits */
35*4882a593Smuzhiyun #define MAX8649_EN_PD		(1 << 7)
36*4882a593Smuzhiyun #define MAX8649_VID0_PD		(1 << 6)
37*4882a593Smuzhiyun #define MAX8649_VID1_PD		(1 << 5)
38*4882a593Smuzhiyun #define MAX8649_VID_MASK	(3 << 5)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define MAX8649_FORCE_PWM	(1 << 7)
41*4882a593Smuzhiyun #define MAX8649_SYNC_EXTCLK	(1 << 6)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define MAX8649_EXT_MASK	(3 << 6)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define MAX8649_RAMP_MASK	(7 << 5)
46*4882a593Smuzhiyun #define MAX8649_RAMP_DOWN	(1 << 1)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun struct max8649_regulator_info {
49*4882a593Smuzhiyun 	struct device		*dev;
50*4882a593Smuzhiyun 	struct regmap		*regmap;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	unsigned	mode:2;	/* bit[1:0] = VID1, VID0 */
53*4882a593Smuzhiyun 	unsigned	extclk_freq:2;
54*4882a593Smuzhiyun 	unsigned	extclk:1;
55*4882a593Smuzhiyun 	unsigned	ramp_timing:3;
56*4882a593Smuzhiyun 	unsigned	ramp_down:1;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
max8649_enable_time(struct regulator_dev * rdev)59*4882a593Smuzhiyun static int max8649_enable_time(struct regulator_dev *rdev)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct max8649_regulator_info *info = rdev_get_drvdata(rdev);
62*4882a593Smuzhiyun 	int voltage, rate, ret;
63*4882a593Smuzhiyun 	unsigned int val;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	/* get voltage */
66*4882a593Smuzhiyun 	ret = regmap_read(info->regmap, rdev->desc->vsel_reg, &val);
67*4882a593Smuzhiyun 	if (ret != 0)
68*4882a593Smuzhiyun 		return ret;
69*4882a593Smuzhiyun 	val &= MAX8649_VOL_MASK;
70*4882a593Smuzhiyun 	voltage = regulator_list_voltage_linear(rdev, (unsigned char)val);
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	/* get rate */
73*4882a593Smuzhiyun 	ret = regmap_read(info->regmap, MAX8649_RAMP, &val);
74*4882a593Smuzhiyun 	if (ret != 0)
75*4882a593Smuzhiyun 		return ret;
76*4882a593Smuzhiyun 	ret = (val & MAX8649_RAMP_MASK) >> 5;
77*4882a593Smuzhiyun 	rate = (32 * 1000) >> ret;	/* uV/uS */
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	return DIV_ROUND_UP(voltage, rate);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
max8649_set_mode(struct regulator_dev * rdev,unsigned int mode)82*4882a593Smuzhiyun static int max8649_set_mode(struct regulator_dev *rdev, unsigned int mode)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	struct max8649_regulator_info *info = rdev_get_drvdata(rdev);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	switch (mode) {
87*4882a593Smuzhiyun 	case REGULATOR_MODE_FAST:
88*4882a593Smuzhiyun 		regmap_update_bits(info->regmap, rdev->desc->vsel_reg,
89*4882a593Smuzhiyun 				   MAX8649_FORCE_PWM, MAX8649_FORCE_PWM);
90*4882a593Smuzhiyun 		break;
91*4882a593Smuzhiyun 	case REGULATOR_MODE_NORMAL:
92*4882a593Smuzhiyun 		regmap_update_bits(info->regmap, rdev->desc->vsel_reg,
93*4882a593Smuzhiyun 				   MAX8649_FORCE_PWM, 0);
94*4882a593Smuzhiyun 		break;
95*4882a593Smuzhiyun 	default:
96*4882a593Smuzhiyun 		return -EINVAL;
97*4882a593Smuzhiyun 	}
98*4882a593Smuzhiyun 	return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
max8649_get_mode(struct regulator_dev * rdev)101*4882a593Smuzhiyun static unsigned int max8649_get_mode(struct regulator_dev *rdev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	struct max8649_regulator_info *info = rdev_get_drvdata(rdev);
104*4882a593Smuzhiyun 	unsigned int val;
105*4882a593Smuzhiyun 	int ret;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	ret = regmap_read(info->regmap, rdev->desc->vsel_reg, &val);
108*4882a593Smuzhiyun 	if (ret != 0)
109*4882a593Smuzhiyun 		return ret;
110*4882a593Smuzhiyun 	if (val & MAX8649_FORCE_PWM)
111*4882a593Smuzhiyun 		return REGULATOR_MODE_FAST;
112*4882a593Smuzhiyun 	return REGULATOR_MODE_NORMAL;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static const struct regulator_ops max8649_dcdc_ops = {
116*4882a593Smuzhiyun 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
117*4882a593Smuzhiyun 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
118*4882a593Smuzhiyun 	.list_voltage	= regulator_list_voltage_linear,
119*4882a593Smuzhiyun 	.map_voltage	= regulator_map_voltage_linear,
120*4882a593Smuzhiyun 	.enable		= regulator_enable_regmap,
121*4882a593Smuzhiyun 	.disable	= regulator_disable_regmap,
122*4882a593Smuzhiyun 	.is_enabled	= regulator_is_enabled_regmap,
123*4882a593Smuzhiyun 	.enable_time	= max8649_enable_time,
124*4882a593Smuzhiyun 	.set_mode	= max8649_set_mode,
125*4882a593Smuzhiyun 	.get_mode	= max8649_get_mode,
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static struct regulator_desc dcdc_desc = {
130*4882a593Smuzhiyun 	.name		= "max8649",
131*4882a593Smuzhiyun 	.ops		= &max8649_dcdc_ops,
132*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,
133*4882a593Smuzhiyun 	.n_voltages	= 1 << 6,
134*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
135*4882a593Smuzhiyun 	.vsel_mask	= MAX8649_VOL_MASK,
136*4882a593Smuzhiyun 	.min_uV		= MAX8649_DCDC_VMIN,
137*4882a593Smuzhiyun 	.uV_step	= MAX8649_DCDC_STEP,
138*4882a593Smuzhiyun 	.enable_reg	= MAX8649_CONTROL,
139*4882a593Smuzhiyun 	.enable_mask	= MAX8649_EN_PD,
140*4882a593Smuzhiyun 	.enable_is_inverted = true,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static const struct regmap_config max8649_regmap_config = {
144*4882a593Smuzhiyun 	.reg_bits = 8,
145*4882a593Smuzhiyun 	.val_bits = 8,
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
max8649_regulator_probe(struct i2c_client * client,const struct i2c_device_id * id)148*4882a593Smuzhiyun static int max8649_regulator_probe(struct i2c_client *client,
149*4882a593Smuzhiyun 					     const struct i2c_device_id *id)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	struct max8649_platform_data *pdata = dev_get_platdata(&client->dev);
152*4882a593Smuzhiyun 	struct max8649_regulator_info *info = NULL;
153*4882a593Smuzhiyun 	struct regulator_dev *regulator;
154*4882a593Smuzhiyun 	struct regulator_config config = { };
155*4882a593Smuzhiyun 	unsigned int val;
156*4882a593Smuzhiyun 	unsigned char data;
157*4882a593Smuzhiyun 	int ret;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	info = devm_kzalloc(&client->dev, sizeof(struct max8649_regulator_info),
160*4882a593Smuzhiyun 			    GFP_KERNEL);
161*4882a593Smuzhiyun 	if (!info)
162*4882a593Smuzhiyun 		return -ENOMEM;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	info->regmap = devm_regmap_init_i2c(client, &max8649_regmap_config);
165*4882a593Smuzhiyun 	if (IS_ERR(info->regmap)) {
166*4882a593Smuzhiyun 		ret = PTR_ERR(info->regmap);
167*4882a593Smuzhiyun 		dev_err(&client->dev, "Failed to allocate register map: %d\n", ret);
168*4882a593Smuzhiyun 		return ret;
169*4882a593Smuzhiyun 	}
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	info->dev = &client->dev;
172*4882a593Smuzhiyun 	i2c_set_clientdata(client, info);
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	info->mode = pdata->mode;
175*4882a593Smuzhiyun 	switch (info->mode) {
176*4882a593Smuzhiyun 	case 0:
177*4882a593Smuzhiyun 		dcdc_desc.vsel_reg = MAX8649_MODE0;
178*4882a593Smuzhiyun 		break;
179*4882a593Smuzhiyun 	case 1:
180*4882a593Smuzhiyun 		dcdc_desc.vsel_reg = MAX8649_MODE1;
181*4882a593Smuzhiyun 		break;
182*4882a593Smuzhiyun 	case 2:
183*4882a593Smuzhiyun 		dcdc_desc.vsel_reg = MAX8649_MODE2;
184*4882a593Smuzhiyun 		break;
185*4882a593Smuzhiyun 	case 3:
186*4882a593Smuzhiyun 		dcdc_desc.vsel_reg = MAX8649_MODE3;
187*4882a593Smuzhiyun 		break;
188*4882a593Smuzhiyun 	default:
189*4882a593Smuzhiyun 		break;
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	ret = regmap_read(info->regmap, MAX8649_CHIP_ID1, &val);
193*4882a593Smuzhiyun 	if (ret != 0) {
194*4882a593Smuzhiyun 		dev_err(info->dev, "Failed to detect ID of MAX8649:%d\n",
195*4882a593Smuzhiyun 			ret);
196*4882a593Smuzhiyun 		return ret;
197*4882a593Smuzhiyun 	}
198*4882a593Smuzhiyun 	dev_info(info->dev, "Detected MAX8649 (ID:%x)\n", val);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* enable VID0 & VID1 */
201*4882a593Smuzhiyun 	regmap_update_bits(info->regmap, MAX8649_CONTROL, MAX8649_VID_MASK, 0);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	/* enable/disable external clock synchronization */
204*4882a593Smuzhiyun 	info->extclk = pdata->extclk;
205*4882a593Smuzhiyun 	data = (info->extclk) ? MAX8649_SYNC_EXTCLK : 0;
206*4882a593Smuzhiyun 	regmap_update_bits(info->regmap, dcdc_desc.vsel_reg,
207*4882a593Smuzhiyun 			   MAX8649_SYNC_EXTCLK, data);
208*4882a593Smuzhiyun 	if (info->extclk) {
209*4882a593Smuzhiyun 		/* set external clock frequency */
210*4882a593Smuzhiyun 		info->extclk_freq = pdata->extclk_freq;
211*4882a593Smuzhiyun 		regmap_update_bits(info->regmap, MAX8649_SYNC, MAX8649_EXT_MASK,
212*4882a593Smuzhiyun 				   info->extclk_freq << 6);
213*4882a593Smuzhiyun 	}
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	if (pdata->ramp_timing) {
216*4882a593Smuzhiyun 		info->ramp_timing = pdata->ramp_timing;
217*4882a593Smuzhiyun 		regmap_update_bits(info->regmap, MAX8649_RAMP, MAX8649_RAMP_MASK,
218*4882a593Smuzhiyun 				   info->ramp_timing << 5);
219*4882a593Smuzhiyun 	}
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	info->ramp_down = pdata->ramp_down;
222*4882a593Smuzhiyun 	if (info->ramp_down) {
223*4882a593Smuzhiyun 		regmap_update_bits(info->regmap, MAX8649_RAMP, MAX8649_RAMP_DOWN,
224*4882a593Smuzhiyun 				   MAX8649_RAMP_DOWN);
225*4882a593Smuzhiyun 	}
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	config.dev = &client->dev;
228*4882a593Smuzhiyun 	config.init_data = pdata->regulator;
229*4882a593Smuzhiyun 	config.driver_data = info;
230*4882a593Smuzhiyun 	config.regmap = info->regmap;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	regulator = devm_regulator_register(&client->dev, &dcdc_desc,
233*4882a593Smuzhiyun 						  &config);
234*4882a593Smuzhiyun 	if (IS_ERR(regulator)) {
235*4882a593Smuzhiyun 		dev_err(info->dev, "failed to register regulator %s\n",
236*4882a593Smuzhiyun 			dcdc_desc.name);
237*4882a593Smuzhiyun 		return PTR_ERR(regulator);
238*4882a593Smuzhiyun 	}
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	return 0;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun static const struct i2c_device_id max8649_id[] = {
244*4882a593Smuzhiyun 	{ "max8649", 0 },
245*4882a593Smuzhiyun 	{ }
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max8649_id);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun static struct i2c_driver max8649_driver = {
250*4882a593Smuzhiyun 	.probe		= max8649_regulator_probe,
251*4882a593Smuzhiyun 	.driver		= {
252*4882a593Smuzhiyun 		.name	= "max8649",
253*4882a593Smuzhiyun 	},
254*4882a593Smuzhiyun 	.id_table	= max8649_id,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
max8649_init(void)257*4882a593Smuzhiyun static int __init max8649_init(void)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	return i2c_add_driver(&max8649_driver);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun subsys_initcall(max8649_init);
262*4882a593Smuzhiyun 
max8649_exit(void)263*4882a593Smuzhiyun static void __exit max8649_exit(void)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun 	i2c_del_driver(&max8649_driver);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun module_exit(max8649_exit);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun /* Module information */
270*4882a593Smuzhiyun MODULE_DESCRIPTION("MAXIM 8649 voltage regulator driver");
271*4882a593Smuzhiyun MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com>");
272*4882a593Smuzhiyun MODULE_LICENSE("GPL");
273