xref: /OK3568_Linux_fs/kernel/drivers/regulator/ltc3589.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Linear Technology LTC3589,LTC3589-1 regulator support
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (c) 2014 Philipp Zabel <p.zabel@pengutronix.de>, Pengutronix
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/i2c.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/regulator/driver.h>
16*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define DRIVER_NAME		"ltc3589"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define LTC3589_IRQSTAT		0x02
21*4882a593Smuzhiyun #define LTC3589_SCR1		0x07
22*4882a593Smuzhiyun #define LTC3589_OVEN		0x10
23*4882a593Smuzhiyun #define LTC3589_SCR2		0x12
24*4882a593Smuzhiyun #define LTC3589_PGSTAT		0x13
25*4882a593Smuzhiyun #define LTC3589_VCCR		0x20
26*4882a593Smuzhiyun #define LTC3589_CLIRQ		0x21
27*4882a593Smuzhiyun #define LTC3589_B1DTV1		0x23
28*4882a593Smuzhiyun #define LTC3589_B1DTV2		0x24
29*4882a593Smuzhiyun #define LTC3589_VRRCR		0x25
30*4882a593Smuzhiyun #define LTC3589_B2DTV1		0x26
31*4882a593Smuzhiyun #define LTC3589_B2DTV2		0x27
32*4882a593Smuzhiyun #define LTC3589_B3DTV1		0x29
33*4882a593Smuzhiyun #define LTC3589_B3DTV2		0x2a
34*4882a593Smuzhiyun #define LTC3589_L2DTV1		0x32
35*4882a593Smuzhiyun #define LTC3589_L2DTV2		0x33
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define LTC3589_IRQSTAT_PGOOD_TIMEOUT	BIT(3)
38*4882a593Smuzhiyun #define LTC3589_IRQSTAT_UNDERVOLT_WARN	BIT(4)
39*4882a593Smuzhiyun #define LTC3589_IRQSTAT_UNDERVOLT_FAULT	BIT(5)
40*4882a593Smuzhiyun #define LTC3589_IRQSTAT_THERMAL_WARN	BIT(6)
41*4882a593Smuzhiyun #define LTC3589_IRQSTAT_THERMAL_FAULT	BIT(7)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define LTC3589_OVEN_SW1		BIT(0)
44*4882a593Smuzhiyun #define LTC3589_OVEN_SW2		BIT(1)
45*4882a593Smuzhiyun #define LTC3589_OVEN_SW3		BIT(2)
46*4882a593Smuzhiyun #define LTC3589_OVEN_BB_OUT		BIT(3)
47*4882a593Smuzhiyun #define LTC3589_OVEN_LDO2		BIT(4)
48*4882a593Smuzhiyun #define LTC3589_OVEN_LDO3		BIT(5)
49*4882a593Smuzhiyun #define LTC3589_OVEN_LDO4		BIT(6)
50*4882a593Smuzhiyun #define LTC3589_OVEN_SW_CTRL		BIT(7)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define LTC3589_VCCR_SW1_GO		BIT(0)
53*4882a593Smuzhiyun #define LTC3589_VCCR_SW2_GO		BIT(2)
54*4882a593Smuzhiyun #define LTC3589_VCCR_SW3_GO		BIT(4)
55*4882a593Smuzhiyun #define LTC3589_VCCR_LDO2_GO		BIT(6)
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun enum ltc3589_variant {
58*4882a593Smuzhiyun 	LTC3589,
59*4882a593Smuzhiyun 	LTC3589_1,
60*4882a593Smuzhiyun 	LTC3589_2,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun enum ltc3589_reg {
64*4882a593Smuzhiyun 	LTC3589_SW1,
65*4882a593Smuzhiyun 	LTC3589_SW2,
66*4882a593Smuzhiyun 	LTC3589_SW3,
67*4882a593Smuzhiyun 	LTC3589_BB_OUT,
68*4882a593Smuzhiyun 	LTC3589_LDO1,
69*4882a593Smuzhiyun 	LTC3589_LDO2,
70*4882a593Smuzhiyun 	LTC3589_LDO3,
71*4882a593Smuzhiyun 	LTC3589_LDO4,
72*4882a593Smuzhiyun 	LTC3589_NUM_REGULATORS,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun struct ltc3589 {
76*4882a593Smuzhiyun 	struct regmap *regmap;
77*4882a593Smuzhiyun 	struct device *dev;
78*4882a593Smuzhiyun 	enum ltc3589_variant variant;
79*4882a593Smuzhiyun 	struct regulator_desc regulator_descs[LTC3589_NUM_REGULATORS];
80*4882a593Smuzhiyun 	struct regulator_dev *regulators[LTC3589_NUM_REGULATORS];
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun static const int ltc3589_ldo4[] = {
84*4882a593Smuzhiyun 	2800000, 2500000, 1800000, 3300000,
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun static const int ltc3589_12_ldo4[] = {
88*4882a593Smuzhiyun 	1200000, 1800000, 2500000, 3200000,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
ltc3589_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)91*4882a593Smuzhiyun static int ltc3589_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
94*4882a593Smuzhiyun 	int sel, shift;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	if (unlikely(ramp_delay <= 0))
97*4882a593Smuzhiyun 		return -EINVAL;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	/* VRRCR slew rate offsets are the same as VCCR go bit offsets */
100*4882a593Smuzhiyun 	shift = ffs(rdev->desc->apply_bit) - 1;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	/* The slew rate can be set to 0.88, 1.75, 3.5, or 7 mV/uS */
103*4882a593Smuzhiyun 	for (sel = 0; sel < 4; sel++) {
104*4882a593Smuzhiyun 		if ((880 << sel) >= ramp_delay) {
105*4882a593Smuzhiyun 			return regmap_update_bits(ltc3589->regmap,
106*4882a593Smuzhiyun 						  LTC3589_VRRCR,
107*4882a593Smuzhiyun 						  0x3 << shift, sel << shift);
108*4882a593Smuzhiyun 		}
109*4882a593Smuzhiyun 	}
110*4882a593Smuzhiyun 	return -EINVAL;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
ltc3589_set_suspend_voltage(struct regulator_dev * rdev,int uV)113*4882a593Smuzhiyun static int ltc3589_set_suspend_voltage(struct regulator_dev *rdev, int uV)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
116*4882a593Smuzhiyun 	int sel;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	sel = regulator_map_voltage_linear(rdev, uV, uV);
119*4882a593Smuzhiyun 	if (sel < 0)
120*4882a593Smuzhiyun 		return sel;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	/* DTV2 register follows right after the corresponding DTV1 register */
123*4882a593Smuzhiyun 	return regmap_update_bits(ltc3589->regmap, rdev->desc->vsel_reg + 1,
124*4882a593Smuzhiyun 				  rdev->desc->vsel_mask, sel);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun 
ltc3589_set_suspend_mode(struct regulator_dev * rdev,unsigned int mode)127*4882a593Smuzhiyun static int ltc3589_set_suspend_mode(struct regulator_dev *rdev,
128*4882a593Smuzhiyun 				    unsigned int mode)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
131*4882a593Smuzhiyun 	int mask, bit = 0;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	/* VCCR reference selects are right next to the VCCR go bits */
134*4882a593Smuzhiyun 	mask = rdev->desc->apply_bit << 1;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	if (mode == REGULATOR_MODE_STANDBY)
137*4882a593Smuzhiyun 		bit = mask;	/* Select DTV2 */
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	mask |= rdev->desc->apply_bit;
140*4882a593Smuzhiyun 	bit |= rdev->desc->apply_bit;
141*4882a593Smuzhiyun 	return regmap_update_bits(ltc3589->regmap, LTC3589_VCCR, mask, bit);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun /* SW1, SW2, SW3, LDO2 */
145*4882a593Smuzhiyun static const struct regulator_ops ltc3589_linear_regulator_ops = {
146*4882a593Smuzhiyun 	.enable = regulator_enable_regmap,
147*4882a593Smuzhiyun 	.disable = regulator_disable_regmap,
148*4882a593Smuzhiyun 	.is_enabled = regulator_is_enabled_regmap,
149*4882a593Smuzhiyun 	.list_voltage = regulator_list_voltage_linear,
150*4882a593Smuzhiyun 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
151*4882a593Smuzhiyun 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
152*4882a593Smuzhiyun 	.set_ramp_delay = ltc3589_set_ramp_delay,
153*4882a593Smuzhiyun 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
154*4882a593Smuzhiyun 	.set_suspend_voltage = ltc3589_set_suspend_voltage,
155*4882a593Smuzhiyun 	.set_suspend_mode = ltc3589_set_suspend_mode,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun /* BB_OUT, LDO3 */
159*4882a593Smuzhiyun static const struct regulator_ops ltc3589_fixed_regulator_ops = {
160*4882a593Smuzhiyun 	.enable = regulator_enable_regmap,
161*4882a593Smuzhiyun 	.disable = regulator_disable_regmap,
162*4882a593Smuzhiyun 	.is_enabled = regulator_is_enabled_regmap,
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /* LDO1 */
166*4882a593Smuzhiyun static const struct regulator_ops ltc3589_fixed_standby_regulator_ops = {
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /* LDO4 */
170*4882a593Smuzhiyun static const struct regulator_ops ltc3589_table_regulator_ops = {
171*4882a593Smuzhiyun 	.enable = regulator_enable_regmap,
172*4882a593Smuzhiyun 	.disable = regulator_disable_regmap,
173*4882a593Smuzhiyun 	.is_enabled = regulator_is_enabled_regmap,
174*4882a593Smuzhiyun 	.list_voltage = regulator_list_voltage_table,
175*4882a593Smuzhiyun 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
176*4882a593Smuzhiyun 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
ltc3589_scale(unsigned int uV,u32 r1,u32 r2)179*4882a593Smuzhiyun static inline unsigned int ltc3589_scale(unsigned int uV, u32 r1, u32 r2)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	uint64_t tmp;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	if (uV == 0)
184*4882a593Smuzhiyun 		return 0;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	tmp = (uint64_t)uV * r1;
187*4882a593Smuzhiyun 	do_div(tmp, r2);
188*4882a593Smuzhiyun 	return uV + (unsigned int)tmp;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
ltc3589_of_parse_cb(struct device_node * np,const struct regulator_desc * desc,struct regulator_config * config)191*4882a593Smuzhiyun static int ltc3589_of_parse_cb(struct device_node *np,
192*4882a593Smuzhiyun 			       const struct regulator_desc *desc,
193*4882a593Smuzhiyun 			       struct regulator_config *config)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	struct ltc3589 *ltc3589 = config->driver_data;
196*4882a593Smuzhiyun 	struct regulator_desc *rdesc = &ltc3589->regulator_descs[desc->id];
197*4882a593Smuzhiyun 	u32 r[2];
198*4882a593Smuzhiyun 	int ret;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* Parse feedback voltage dividers. LDO3 and LDO4 don't have them */
201*4882a593Smuzhiyun 	if (desc->id >= LTC3589_LDO3)
202*4882a593Smuzhiyun 		return 0;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	ret = of_property_read_u32_array(np, "lltc,fb-voltage-divider", r, 2);
205*4882a593Smuzhiyun 	if (ret) {
206*4882a593Smuzhiyun 		dev_err(ltc3589->dev, "Failed to parse voltage divider: %d\n",
207*4882a593Smuzhiyun 			ret);
208*4882a593Smuzhiyun 		return ret;
209*4882a593Smuzhiyun 	}
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	if (!r[0] || !r[1])
212*4882a593Smuzhiyun 		return 0;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	rdesc->min_uV = ltc3589_scale(desc->min_uV, r[0], r[1]);
215*4882a593Smuzhiyun 	rdesc->uV_step = ltc3589_scale(desc->uV_step, r[0], r[1]);
216*4882a593Smuzhiyun 	rdesc->fixed_uV = ltc3589_scale(desc->fixed_uV, r[0], r[1]);
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	return 0;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun #define LTC3589_REG(_name, _of_name, _ops, en_bit, dtv1_reg, dtv_mask, go_bit)\
222*4882a593Smuzhiyun 	[LTC3589_ ## _name] = {						\
223*4882a593Smuzhiyun 		.name = #_name,						\
224*4882a593Smuzhiyun 		.of_match = of_match_ptr(#_of_name),			\
225*4882a593Smuzhiyun 		.regulators_node = of_match_ptr("regulators"),		\
226*4882a593Smuzhiyun 		.of_parse_cb = ltc3589_of_parse_cb,			\
227*4882a593Smuzhiyun 		.n_voltages = (dtv_mask) + 1,				\
228*4882a593Smuzhiyun 		.min_uV = (go_bit) ? 362500 : 0,			\
229*4882a593Smuzhiyun 		.uV_step = (go_bit) ? 12500 : 0,			\
230*4882a593Smuzhiyun 		.ramp_delay = (go_bit) ? 1750 : 0,			\
231*4882a593Smuzhiyun 		.fixed_uV = (dtv_mask) ? 0 : 800000,			\
232*4882a593Smuzhiyun 		.ops = &ltc3589_ ## _ops ## _regulator_ops,		\
233*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,				\
234*4882a593Smuzhiyun 		.id = LTC3589_ ## _name,				\
235*4882a593Smuzhiyun 		.owner = THIS_MODULE,					\
236*4882a593Smuzhiyun 		.vsel_reg = (dtv1_reg),					\
237*4882a593Smuzhiyun 		.vsel_mask = (dtv_mask),				\
238*4882a593Smuzhiyun 		.apply_reg = (go_bit) ? LTC3589_VCCR : 0,		\
239*4882a593Smuzhiyun 		.apply_bit = (go_bit),					\
240*4882a593Smuzhiyun 		.enable_reg = (en_bit) ? LTC3589_OVEN : 0,		\
241*4882a593Smuzhiyun 		.enable_mask = (en_bit),				\
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun #define LTC3589_LINEAR_REG(_name, _of_name, _dtv1)			\
245*4882a593Smuzhiyun 	LTC3589_REG(_name, _of_name, linear, LTC3589_OVEN_ ## _name,	\
246*4882a593Smuzhiyun 		    LTC3589_ ## _dtv1, 0x1f,				\
247*4882a593Smuzhiyun 		    LTC3589_VCCR_ ## _name ## _GO)
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun #define LTC3589_FIXED_REG(_name, _of_name)				\
250*4882a593Smuzhiyun 	LTC3589_REG(_name, _of_name, fixed, LTC3589_OVEN_ ## _name, 0, 0, 0)
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun static const struct regulator_desc ltc3589_regulators[] = {
253*4882a593Smuzhiyun 	LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
254*4882a593Smuzhiyun 	LTC3589_LINEAR_REG(SW2, sw2, B2DTV1),
255*4882a593Smuzhiyun 	LTC3589_LINEAR_REG(SW3, sw3, B3DTV1),
256*4882a593Smuzhiyun 	LTC3589_FIXED_REG(BB_OUT, bb-out),
257*4882a593Smuzhiyun 	LTC3589_REG(LDO1, ldo1, fixed_standby, 0, 0, 0, 0),
258*4882a593Smuzhiyun 	LTC3589_LINEAR_REG(LDO2, ldo2, L2DTV1),
259*4882a593Smuzhiyun 	LTC3589_FIXED_REG(LDO3, ldo3),
260*4882a593Smuzhiyun 	LTC3589_REG(LDO4, ldo4, table, LTC3589_OVEN_LDO4, LTC3589_L2DTV2,
261*4882a593Smuzhiyun 		    0x60, 0),
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun 
ltc3589_writeable_reg(struct device * dev,unsigned int reg)264*4882a593Smuzhiyun static bool ltc3589_writeable_reg(struct device *dev, unsigned int reg)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	switch (reg) {
267*4882a593Smuzhiyun 	case LTC3589_IRQSTAT:
268*4882a593Smuzhiyun 	case LTC3589_SCR1:
269*4882a593Smuzhiyun 	case LTC3589_OVEN:
270*4882a593Smuzhiyun 	case LTC3589_SCR2:
271*4882a593Smuzhiyun 	case LTC3589_VCCR:
272*4882a593Smuzhiyun 	case LTC3589_CLIRQ:
273*4882a593Smuzhiyun 	case LTC3589_B1DTV1:
274*4882a593Smuzhiyun 	case LTC3589_B1DTV2:
275*4882a593Smuzhiyun 	case LTC3589_VRRCR:
276*4882a593Smuzhiyun 	case LTC3589_B2DTV1:
277*4882a593Smuzhiyun 	case LTC3589_B2DTV2:
278*4882a593Smuzhiyun 	case LTC3589_B3DTV1:
279*4882a593Smuzhiyun 	case LTC3589_B3DTV2:
280*4882a593Smuzhiyun 	case LTC3589_L2DTV1:
281*4882a593Smuzhiyun 	case LTC3589_L2DTV2:
282*4882a593Smuzhiyun 		return true;
283*4882a593Smuzhiyun 	}
284*4882a593Smuzhiyun 	return false;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
ltc3589_readable_reg(struct device * dev,unsigned int reg)287*4882a593Smuzhiyun static bool ltc3589_readable_reg(struct device *dev, unsigned int reg)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun 	switch (reg) {
290*4882a593Smuzhiyun 	case LTC3589_IRQSTAT:
291*4882a593Smuzhiyun 	case LTC3589_SCR1:
292*4882a593Smuzhiyun 	case LTC3589_OVEN:
293*4882a593Smuzhiyun 	case LTC3589_SCR2:
294*4882a593Smuzhiyun 	case LTC3589_PGSTAT:
295*4882a593Smuzhiyun 	case LTC3589_VCCR:
296*4882a593Smuzhiyun 	case LTC3589_B1DTV1:
297*4882a593Smuzhiyun 	case LTC3589_B1DTV2:
298*4882a593Smuzhiyun 	case LTC3589_VRRCR:
299*4882a593Smuzhiyun 	case LTC3589_B2DTV1:
300*4882a593Smuzhiyun 	case LTC3589_B2DTV2:
301*4882a593Smuzhiyun 	case LTC3589_B3DTV1:
302*4882a593Smuzhiyun 	case LTC3589_B3DTV2:
303*4882a593Smuzhiyun 	case LTC3589_L2DTV1:
304*4882a593Smuzhiyun 	case LTC3589_L2DTV2:
305*4882a593Smuzhiyun 		return true;
306*4882a593Smuzhiyun 	}
307*4882a593Smuzhiyun 	return false;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun 
ltc3589_volatile_reg(struct device * dev,unsigned int reg)310*4882a593Smuzhiyun static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun 	switch (reg) {
313*4882a593Smuzhiyun 	case LTC3589_IRQSTAT:
314*4882a593Smuzhiyun 	case LTC3589_PGSTAT:
315*4882a593Smuzhiyun 	case LTC3589_VCCR:
316*4882a593Smuzhiyun 		return true;
317*4882a593Smuzhiyun 	}
318*4882a593Smuzhiyun 	return false;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun static const struct reg_default ltc3589_reg_defaults[] = {
322*4882a593Smuzhiyun 	{ LTC3589_SCR1,   0x00 },
323*4882a593Smuzhiyun 	{ LTC3589_OVEN,   0x00 },
324*4882a593Smuzhiyun 	{ LTC3589_SCR2,   0x00 },
325*4882a593Smuzhiyun 	{ LTC3589_VCCR,   0x00 },
326*4882a593Smuzhiyun 	{ LTC3589_B1DTV1, 0x19 },
327*4882a593Smuzhiyun 	{ LTC3589_B1DTV2, 0x19 },
328*4882a593Smuzhiyun 	{ LTC3589_VRRCR,  0xff },
329*4882a593Smuzhiyun 	{ LTC3589_B2DTV1, 0x19 },
330*4882a593Smuzhiyun 	{ LTC3589_B2DTV2, 0x19 },
331*4882a593Smuzhiyun 	{ LTC3589_B3DTV1, 0x19 },
332*4882a593Smuzhiyun 	{ LTC3589_B3DTV2, 0x19 },
333*4882a593Smuzhiyun 	{ LTC3589_L2DTV1, 0x19 },
334*4882a593Smuzhiyun 	{ LTC3589_L2DTV2, 0x19 },
335*4882a593Smuzhiyun };
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun static const struct regmap_config ltc3589_regmap_config = {
338*4882a593Smuzhiyun 	.reg_bits = 8,
339*4882a593Smuzhiyun 	.val_bits = 8,
340*4882a593Smuzhiyun 	.writeable_reg = ltc3589_writeable_reg,
341*4882a593Smuzhiyun 	.readable_reg = ltc3589_readable_reg,
342*4882a593Smuzhiyun 	.volatile_reg = ltc3589_volatile_reg,
343*4882a593Smuzhiyun 	.max_register = LTC3589_L2DTV2,
344*4882a593Smuzhiyun 	.reg_defaults = ltc3589_reg_defaults,
345*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(ltc3589_reg_defaults),
346*4882a593Smuzhiyun 	.use_single_read = true,
347*4882a593Smuzhiyun 	.use_single_write = true,
348*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun 
ltc3589_isr(int irq,void * dev_id)351*4882a593Smuzhiyun static irqreturn_t ltc3589_isr(int irq, void *dev_id)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	struct ltc3589 *ltc3589 = dev_id;
354*4882a593Smuzhiyun 	unsigned int i, irqstat, event;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	regmap_read(ltc3589->regmap, LTC3589_IRQSTAT, &irqstat);
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	if (irqstat & LTC3589_IRQSTAT_THERMAL_WARN) {
359*4882a593Smuzhiyun 		event = REGULATOR_EVENT_OVER_TEMP;
360*4882a593Smuzhiyun 		for (i = 0; i < LTC3589_NUM_REGULATORS; i++)
361*4882a593Smuzhiyun 			regulator_notifier_call_chain(ltc3589->regulators[i],
362*4882a593Smuzhiyun 						      event, NULL);
363*4882a593Smuzhiyun 	}
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	if (irqstat & LTC3589_IRQSTAT_UNDERVOLT_WARN) {
366*4882a593Smuzhiyun 		event = REGULATOR_EVENT_UNDER_VOLTAGE;
367*4882a593Smuzhiyun 		for (i = 0; i < LTC3589_NUM_REGULATORS; i++)
368*4882a593Smuzhiyun 			regulator_notifier_call_chain(ltc3589->regulators[i],
369*4882a593Smuzhiyun 						      event, NULL);
370*4882a593Smuzhiyun 	}
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	/* Clear warning condition */
373*4882a593Smuzhiyun 	regmap_write(ltc3589->regmap, LTC3589_CLIRQ, 0);
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	return IRQ_HANDLED;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
ltc3589_probe(struct i2c_client * client,const struct i2c_device_id * id)378*4882a593Smuzhiyun static int ltc3589_probe(struct i2c_client *client,
379*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun 	struct device *dev = &client->dev;
382*4882a593Smuzhiyun 	struct regulator_desc *descs;
383*4882a593Smuzhiyun 	struct ltc3589 *ltc3589;
384*4882a593Smuzhiyun 	int i, ret;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	ltc3589 = devm_kzalloc(dev, sizeof(*ltc3589), GFP_KERNEL);
387*4882a593Smuzhiyun 	if (!ltc3589)
388*4882a593Smuzhiyun 		return -ENOMEM;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	i2c_set_clientdata(client, ltc3589);
391*4882a593Smuzhiyun 	if (client->dev.of_node)
392*4882a593Smuzhiyun 		ltc3589->variant = (enum ltc3589_variant)
393*4882a593Smuzhiyun 			of_device_get_match_data(&client->dev);
394*4882a593Smuzhiyun 	else
395*4882a593Smuzhiyun 		ltc3589->variant = id->driver_data;
396*4882a593Smuzhiyun 	ltc3589->dev = dev;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	descs = ltc3589->regulator_descs;
399*4882a593Smuzhiyun 	memcpy(descs, ltc3589_regulators, sizeof(ltc3589_regulators));
400*4882a593Smuzhiyun 	if (ltc3589->variant == LTC3589) {
401*4882a593Smuzhiyun 		descs[LTC3589_LDO3].fixed_uV = 1800000;
402*4882a593Smuzhiyun 		descs[LTC3589_LDO4].volt_table = ltc3589_ldo4;
403*4882a593Smuzhiyun 	} else {
404*4882a593Smuzhiyun 		descs[LTC3589_LDO3].fixed_uV = 2800000;
405*4882a593Smuzhiyun 		descs[LTC3589_LDO4].volt_table = ltc3589_12_ldo4;
406*4882a593Smuzhiyun 	}
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	ltc3589->regmap = devm_regmap_init_i2c(client, &ltc3589_regmap_config);
409*4882a593Smuzhiyun 	if (IS_ERR(ltc3589->regmap)) {
410*4882a593Smuzhiyun 		ret = PTR_ERR(ltc3589->regmap);
411*4882a593Smuzhiyun 		dev_err(dev, "failed to initialize regmap: %d\n", ret);
412*4882a593Smuzhiyun 		return ret;
413*4882a593Smuzhiyun 	}
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
416*4882a593Smuzhiyun 		struct regulator_desc *desc = &ltc3589->regulator_descs[i];
417*4882a593Smuzhiyun 		struct regulator_config config = { };
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 		config.dev = dev;
420*4882a593Smuzhiyun 		config.driver_data = ltc3589;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 		ltc3589->regulators[i] = devm_regulator_register(dev, desc,
423*4882a593Smuzhiyun 								 &config);
424*4882a593Smuzhiyun 		if (IS_ERR(ltc3589->regulators[i])) {
425*4882a593Smuzhiyun 			ret = PTR_ERR(ltc3589->regulators[i]);
426*4882a593Smuzhiyun 			dev_err(dev, "failed to register regulator %s: %d\n",
427*4882a593Smuzhiyun 				desc->name, ret);
428*4882a593Smuzhiyun 			return ret;
429*4882a593Smuzhiyun 		}
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	if (client->irq) {
433*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(dev, client->irq, NULL,
434*4882a593Smuzhiyun 						ltc3589_isr,
435*4882a593Smuzhiyun 						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
436*4882a593Smuzhiyun 						client->name, ltc3589);
437*4882a593Smuzhiyun 		if (ret) {
438*4882a593Smuzhiyun 			dev_err(dev, "Failed to request IRQ: %d\n", ret);
439*4882a593Smuzhiyun 			return ret;
440*4882a593Smuzhiyun 		}
441*4882a593Smuzhiyun 	}
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	return 0;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun static const struct i2c_device_id ltc3589_i2c_id[] = {
447*4882a593Smuzhiyun 	{ "ltc3589",   LTC3589   },
448*4882a593Smuzhiyun 	{ "ltc3589-1", LTC3589_1 },
449*4882a593Smuzhiyun 	{ "ltc3589-2", LTC3589_2 },
450*4882a593Smuzhiyun 	{ }
451*4882a593Smuzhiyun };
452*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ltc3589_i2c_id);
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun static const struct of_device_id __maybe_unused ltc3589_of_match[] = {
455*4882a593Smuzhiyun 	{
456*4882a593Smuzhiyun 		.compatible = "lltc,ltc3589",
457*4882a593Smuzhiyun 		.data = (void *)LTC3589,
458*4882a593Smuzhiyun 	},
459*4882a593Smuzhiyun 	{
460*4882a593Smuzhiyun 		.compatible = "lltc,ltc3589-1",
461*4882a593Smuzhiyun 		.data = (void *)LTC3589_1,
462*4882a593Smuzhiyun 	},
463*4882a593Smuzhiyun 	{
464*4882a593Smuzhiyun 		.compatible = "lltc,ltc3589-2",
465*4882a593Smuzhiyun 		.data = (void *)LTC3589_2,
466*4882a593Smuzhiyun 	},
467*4882a593Smuzhiyun 	{ },
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ltc3589_of_match);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun static struct i2c_driver ltc3589_driver = {
472*4882a593Smuzhiyun 	.driver = {
473*4882a593Smuzhiyun 		.name = DRIVER_NAME,
474*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(ltc3589_of_match),
475*4882a593Smuzhiyun 	},
476*4882a593Smuzhiyun 	.probe = ltc3589_probe,
477*4882a593Smuzhiyun 	.id_table = ltc3589_i2c_id,
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun module_i2c_driver(ltc3589_driver);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
482*4882a593Smuzhiyun MODULE_DESCRIPTION("Regulator driver for Linear Technology LTC3589(-1,2)");
483*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
484