1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * TI LP8788 MFD - buck regulator driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2012 Texas Instruments
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/regulator/driver.h>
15*4882a593Smuzhiyun #include <linux/mfd/lp8788.h>
16*4882a593Smuzhiyun #include <linux/gpio.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* register address */
19*4882a593Smuzhiyun #define LP8788_EN_BUCK 0x0C
20*4882a593Smuzhiyun #define LP8788_BUCK_DVS_SEL 0x1D
21*4882a593Smuzhiyun #define LP8788_BUCK1_VOUT0 0x1E
22*4882a593Smuzhiyun #define LP8788_BUCK1_VOUT1 0x1F
23*4882a593Smuzhiyun #define LP8788_BUCK1_VOUT2 0x20
24*4882a593Smuzhiyun #define LP8788_BUCK1_VOUT3 0x21
25*4882a593Smuzhiyun #define LP8788_BUCK2_VOUT0 0x22
26*4882a593Smuzhiyun #define LP8788_BUCK2_VOUT1 0x23
27*4882a593Smuzhiyun #define LP8788_BUCK2_VOUT2 0x24
28*4882a593Smuzhiyun #define LP8788_BUCK2_VOUT3 0x25
29*4882a593Smuzhiyun #define LP8788_BUCK3_VOUT 0x26
30*4882a593Smuzhiyun #define LP8788_BUCK4_VOUT 0x27
31*4882a593Smuzhiyun #define LP8788_BUCK1_TIMESTEP 0x28
32*4882a593Smuzhiyun #define LP8788_BUCK_PWM 0x2D
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* mask/shift bits */
35*4882a593Smuzhiyun #define LP8788_EN_BUCK1_M BIT(0) /* Addr 0Ch */
36*4882a593Smuzhiyun #define LP8788_EN_BUCK2_M BIT(1)
37*4882a593Smuzhiyun #define LP8788_EN_BUCK3_M BIT(2)
38*4882a593Smuzhiyun #define LP8788_EN_BUCK4_M BIT(3)
39*4882a593Smuzhiyun #define LP8788_BUCK1_DVS_SEL_M 0x04 /* Addr 1Dh */
40*4882a593Smuzhiyun #define LP8788_BUCK1_DVS_M 0x03
41*4882a593Smuzhiyun #define LP8788_BUCK1_DVS_S 0
42*4882a593Smuzhiyun #define LP8788_BUCK2_DVS_SEL_M 0x40
43*4882a593Smuzhiyun #define LP8788_BUCK2_DVS_M 0x30
44*4882a593Smuzhiyun #define LP8788_BUCK2_DVS_S 4
45*4882a593Smuzhiyun #define LP8788_BUCK1_DVS_I2C BIT(2)
46*4882a593Smuzhiyun #define LP8788_BUCK2_DVS_I2C BIT(6)
47*4882a593Smuzhiyun #define LP8788_BUCK1_DVS_PIN (0 << 2)
48*4882a593Smuzhiyun #define LP8788_BUCK2_DVS_PIN (0 << 6)
49*4882a593Smuzhiyun #define LP8788_VOUT_M 0x1F /* Addr 1Eh ~ 27h */
50*4882a593Smuzhiyun #define LP8788_STARTUP_TIME_M 0xF8 /* Addr 28h ~ 2Bh */
51*4882a593Smuzhiyun #define LP8788_STARTUP_TIME_S 3
52*4882a593Smuzhiyun #define LP8788_FPWM_BUCK1_M BIT(0) /* Addr 2Dh */
53*4882a593Smuzhiyun #define LP8788_FPWM_BUCK1_S 0
54*4882a593Smuzhiyun #define LP8788_FPWM_BUCK2_M BIT(1)
55*4882a593Smuzhiyun #define LP8788_FPWM_BUCK2_S 1
56*4882a593Smuzhiyun #define LP8788_FPWM_BUCK3_M BIT(2)
57*4882a593Smuzhiyun #define LP8788_FPWM_BUCK3_S 2
58*4882a593Smuzhiyun #define LP8788_FPWM_BUCK4_M BIT(3)
59*4882a593Smuzhiyun #define LP8788_FPWM_BUCK4_S 3
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define INVALID_ADDR 0xFF
62*4882a593Smuzhiyun #define LP8788_FORCE_PWM 1
63*4882a593Smuzhiyun #define LP8788_AUTO_PWM 0
64*4882a593Smuzhiyun #define PIN_LOW 0
65*4882a593Smuzhiyun #define PIN_HIGH 1
66*4882a593Smuzhiyun #define ENABLE_TIME_USEC 32
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define BUCK_FPWM_MASK(x) (1 << (x))
69*4882a593Smuzhiyun #define BUCK_FPWM_SHIFT(x) (x)
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun enum lp8788_dvs_state {
72*4882a593Smuzhiyun DVS_LOW = GPIOF_OUT_INIT_LOW,
73*4882a593Smuzhiyun DVS_HIGH = GPIOF_OUT_INIT_HIGH,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun enum lp8788_dvs_mode {
77*4882a593Smuzhiyun REGISTER,
78*4882a593Smuzhiyun EXTPIN,
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun enum lp8788_buck_id {
82*4882a593Smuzhiyun BUCK1,
83*4882a593Smuzhiyun BUCK2,
84*4882a593Smuzhiyun BUCK3,
85*4882a593Smuzhiyun BUCK4,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun struct lp8788_buck {
89*4882a593Smuzhiyun struct lp8788 *lp;
90*4882a593Smuzhiyun struct regulator_dev *regulator;
91*4882a593Smuzhiyun void *dvs;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* BUCK 1 ~ 4 voltage ranges */
95*4882a593Smuzhiyun static const struct linear_range buck_volt_ranges[] = {
96*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(500000, 0, 0, 0),
97*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(800000, 1, 25, 50000),
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
lp8788_buck1_set_dvs(struct lp8788_buck * buck)100*4882a593Smuzhiyun static void lp8788_buck1_set_dvs(struct lp8788_buck *buck)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct lp8788_buck1_dvs *dvs = (struct lp8788_buck1_dvs *)buck->dvs;
103*4882a593Smuzhiyun enum lp8788_dvs_state pinstate;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (!dvs)
106*4882a593Smuzhiyun return;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun pinstate = dvs->vsel == DVS_SEL_V0 ? DVS_LOW : DVS_HIGH;
109*4882a593Smuzhiyun if (gpio_is_valid(dvs->gpio))
110*4882a593Smuzhiyun gpio_set_value(dvs->gpio, pinstate);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
lp8788_buck2_set_dvs(struct lp8788_buck * buck)113*4882a593Smuzhiyun static void lp8788_buck2_set_dvs(struct lp8788_buck *buck)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct lp8788_buck2_dvs *dvs = (struct lp8788_buck2_dvs *)buck->dvs;
116*4882a593Smuzhiyun enum lp8788_dvs_state pin1, pin2;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (!dvs)
119*4882a593Smuzhiyun return;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun switch (dvs->vsel) {
122*4882a593Smuzhiyun case DVS_SEL_V0:
123*4882a593Smuzhiyun pin1 = DVS_LOW;
124*4882a593Smuzhiyun pin2 = DVS_LOW;
125*4882a593Smuzhiyun break;
126*4882a593Smuzhiyun case DVS_SEL_V1:
127*4882a593Smuzhiyun pin1 = DVS_HIGH;
128*4882a593Smuzhiyun pin2 = DVS_LOW;
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun case DVS_SEL_V2:
131*4882a593Smuzhiyun pin1 = DVS_LOW;
132*4882a593Smuzhiyun pin2 = DVS_HIGH;
133*4882a593Smuzhiyun break;
134*4882a593Smuzhiyun case DVS_SEL_V3:
135*4882a593Smuzhiyun pin1 = DVS_HIGH;
136*4882a593Smuzhiyun pin2 = DVS_HIGH;
137*4882a593Smuzhiyun break;
138*4882a593Smuzhiyun default:
139*4882a593Smuzhiyun return;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if (gpio_is_valid(dvs->gpio[0]))
143*4882a593Smuzhiyun gpio_set_value(dvs->gpio[0], pin1);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (gpio_is_valid(dvs->gpio[1]))
146*4882a593Smuzhiyun gpio_set_value(dvs->gpio[1], pin2);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
lp8788_set_dvs(struct lp8788_buck * buck,enum lp8788_buck_id id)149*4882a593Smuzhiyun static void lp8788_set_dvs(struct lp8788_buck *buck, enum lp8788_buck_id id)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun switch (id) {
152*4882a593Smuzhiyun case BUCK1:
153*4882a593Smuzhiyun lp8788_buck1_set_dvs(buck);
154*4882a593Smuzhiyun break;
155*4882a593Smuzhiyun case BUCK2:
156*4882a593Smuzhiyun lp8788_buck2_set_dvs(buck);
157*4882a593Smuzhiyun break;
158*4882a593Smuzhiyun default:
159*4882a593Smuzhiyun break;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static enum lp8788_dvs_mode
lp8788_get_buck_dvs_ctrl_mode(struct lp8788_buck * buck,enum lp8788_buck_id id)164*4882a593Smuzhiyun lp8788_get_buck_dvs_ctrl_mode(struct lp8788_buck *buck, enum lp8788_buck_id id)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun u8 val, mask;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun switch (id) {
169*4882a593Smuzhiyun case BUCK1:
170*4882a593Smuzhiyun mask = LP8788_BUCK1_DVS_SEL_M;
171*4882a593Smuzhiyun break;
172*4882a593Smuzhiyun case BUCK2:
173*4882a593Smuzhiyun mask = LP8788_BUCK2_DVS_SEL_M;
174*4882a593Smuzhiyun break;
175*4882a593Smuzhiyun default:
176*4882a593Smuzhiyun return REGISTER;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun return val & mask ? REGISTER : EXTPIN;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
lp8788_is_valid_buck_addr(u8 addr)184*4882a593Smuzhiyun static bool lp8788_is_valid_buck_addr(u8 addr)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun switch (addr) {
187*4882a593Smuzhiyun case LP8788_BUCK1_VOUT0:
188*4882a593Smuzhiyun case LP8788_BUCK1_VOUT1:
189*4882a593Smuzhiyun case LP8788_BUCK1_VOUT2:
190*4882a593Smuzhiyun case LP8788_BUCK1_VOUT3:
191*4882a593Smuzhiyun case LP8788_BUCK2_VOUT0:
192*4882a593Smuzhiyun case LP8788_BUCK2_VOUT1:
193*4882a593Smuzhiyun case LP8788_BUCK2_VOUT2:
194*4882a593Smuzhiyun case LP8788_BUCK2_VOUT3:
195*4882a593Smuzhiyun return true;
196*4882a593Smuzhiyun default:
197*4882a593Smuzhiyun return false;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
lp8788_select_buck_vout_addr(struct lp8788_buck * buck,enum lp8788_buck_id id)201*4882a593Smuzhiyun static u8 lp8788_select_buck_vout_addr(struct lp8788_buck *buck,
202*4882a593Smuzhiyun enum lp8788_buck_id id)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun enum lp8788_dvs_mode mode = lp8788_get_buck_dvs_ctrl_mode(buck, id);
205*4882a593Smuzhiyun struct lp8788_buck1_dvs *b1_dvs;
206*4882a593Smuzhiyun struct lp8788_buck2_dvs *b2_dvs;
207*4882a593Smuzhiyun u8 val, idx, addr;
208*4882a593Smuzhiyun int pin1, pin2;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun switch (id) {
211*4882a593Smuzhiyun case BUCK1:
212*4882a593Smuzhiyun if (mode == EXTPIN) {
213*4882a593Smuzhiyun b1_dvs = (struct lp8788_buck1_dvs *)buck->dvs;
214*4882a593Smuzhiyun if (!b1_dvs)
215*4882a593Smuzhiyun goto err;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun idx = gpio_get_value(b1_dvs->gpio) ? 1 : 0;
218*4882a593Smuzhiyun } else {
219*4882a593Smuzhiyun lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val);
220*4882a593Smuzhiyun idx = (val & LP8788_BUCK1_DVS_M) >> LP8788_BUCK1_DVS_S;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun addr = LP8788_BUCK1_VOUT0 + idx;
223*4882a593Smuzhiyun break;
224*4882a593Smuzhiyun case BUCK2:
225*4882a593Smuzhiyun if (mode == EXTPIN) {
226*4882a593Smuzhiyun b2_dvs = (struct lp8788_buck2_dvs *)buck->dvs;
227*4882a593Smuzhiyun if (!b2_dvs)
228*4882a593Smuzhiyun goto err;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun pin1 = gpio_get_value(b2_dvs->gpio[0]);
231*4882a593Smuzhiyun pin2 = gpio_get_value(b2_dvs->gpio[1]);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun if (pin1 == PIN_LOW && pin2 == PIN_LOW)
234*4882a593Smuzhiyun idx = 0;
235*4882a593Smuzhiyun else if (pin1 == PIN_LOW && pin2 == PIN_HIGH)
236*4882a593Smuzhiyun idx = 2;
237*4882a593Smuzhiyun else if (pin1 == PIN_HIGH && pin2 == PIN_LOW)
238*4882a593Smuzhiyun idx = 1;
239*4882a593Smuzhiyun else
240*4882a593Smuzhiyun idx = 3;
241*4882a593Smuzhiyun } else {
242*4882a593Smuzhiyun lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val);
243*4882a593Smuzhiyun idx = (val & LP8788_BUCK2_DVS_M) >> LP8788_BUCK2_DVS_S;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun addr = LP8788_BUCK2_VOUT0 + idx;
246*4882a593Smuzhiyun break;
247*4882a593Smuzhiyun default:
248*4882a593Smuzhiyun goto err;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun return addr;
252*4882a593Smuzhiyun err:
253*4882a593Smuzhiyun return INVALID_ADDR;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
lp8788_buck12_set_voltage_sel(struct regulator_dev * rdev,unsigned selector)256*4882a593Smuzhiyun static int lp8788_buck12_set_voltage_sel(struct regulator_dev *rdev,
257*4882a593Smuzhiyun unsigned selector)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun struct lp8788_buck *buck = rdev_get_drvdata(rdev);
260*4882a593Smuzhiyun enum lp8788_buck_id id = rdev_get_id(rdev);
261*4882a593Smuzhiyun u8 addr;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun if (buck->dvs)
264*4882a593Smuzhiyun lp8788_set_dvs(buck, id);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun addr = lp8788_select_buck_vout_addr(buck, id);
267*4882a593Smuzhiyun if (!lp8788_is_valid_buck_addr(addr))
268*4882a593Smuzhiyun return -EINVAL;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun return lp8788_update_bits(buck->lp, addr, LP8788_VOUT_M, selector);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
lp8788_buck12_get_voltage_sel(struct regulator_dev * rdev)273*4882a593Smuzhiyun static int lp8788_buck12_get_voltage_sel(struct regulator_dev *rdev)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun struct lp8788_buck *buck = rdev_get_drvdata(rdev);
276*4882a593Smuzhiyun enum lp8788_buck_id id = rdev_get_id(rdev);
277*4882a593Smuzhiyun int ret;
278*4882a593Smuzhiyun u8 val, addr;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun addr = lp8788_select_buck_vout_addr(buck, id);
281*4882a593Smuzhiyun if (!lp8788_is_valid_buck_addr(addr))
282*4882a593Smuzhiyun return -EINVAL;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun ret = lp8788_read_byte(buck->lp, addr, &val);
285*4882a593Smuzhiyun if (ret)
286*4882a593Smuzhiyun return ret;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return val & LP8788_VOUT_M;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
lp8788_buck_enable_time(struct regulator_dev * rdev)291*4882a593Smuzhiyun static int lp8788_buck_enable_time(struct regulator_dev *rdev)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun struct lp8788_buck *buck = rdev_get_drvdata(rdev);
294*4882a593Smuzhiyun enum lp8788_buck_id id = rdev_get_id(rdev);
295*4882a593Smuzhiyun u8 val, addr = LP8788_BUCK1_TIMESTEP + id;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun if (lp8788_read_byte(buck->lp, addr, &val))
298*4882a593Smuzhiyun return -EINVAL;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun return ENABLE_TIME_USEC * val;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
lp8788_buck_set_mode(struct regulator_dev * rdev,unsigned int mode)305*4882a593Smuzhiyun static int lp8788_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun struct lp8788_buck *buck = rdev_get_drvdata(rdev);
308*4882a593Smuzhiyun enum lp8788_buck_id id = rdev_get_id(rdev);
309*4882a593Smuzhiyun u8 mask, val;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun mask = BUCK_FPWM_MASK(id);
312*4882a593Smuzhiyun switch (mode) {
313*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
314*4882a593Smuzhiyun val = LP8788_FORCE_PWM << BUCK_FPWM_SHIFT(id);
315*4882a593Smuzhiyun break;
316*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
317*4882a593Smuzhiyun val = LP8788_AUTO_PWM << BUCK_FPWM_SHIFT(id);
318*4882a593Smuzhiyun break;
319*4882a593Smuzhiyun default:
320*4882a593Smuzhiyun return -EINVAL;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun return lp8788_update_bits(buck->lp, LP8788_BUCK_PWM, mask, val);
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
lp8788_buck_get_mode(struct regulator_dev * rdev)326*4882a593Smuzhiyun static unsigned int lp8788_buck_get_mode(struct regulator_dev *rdev)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun struct lp8788_buck *buck = rdev_get_drvdata(rdev);
329*4882a593Smuzhiyun enum lp8788_buck_id id = rdev_get_id(rdev);
330*4882a593Smuzhiyun u8 val;
331*4882a593Smuzhiyun int ret;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun ret = lp8788_read_byte(buck->lp, LP8788_BUCK_PWM, &val);
334*4882a593Smuzhiyun if (ret)
335*4882a593Smuzhiyun return ret;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun return val & BUCK_FPWM_MASK(id) ?
338*4882a593Smuzhiyun REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun static const struct regulator_ops lp8788_buck12_ops = {
342*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
343*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
344*4882a593Smuzhiyun .set_voltage_sel = lp8788_buck12_set_voltage_sel,
345*4882a593Smuzhiyun .get_voltage_sel = lp8788_buck12_get_voltage_sel,
346*4882a593Smuzhiyun .enable = regulator_enable_regmap,
347*4882a593Smuzhiyun .disable = regulator_disable_regmap,
348*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
349*4882a593Smuzhiyun .enable_time = lp8788_buck_enable_time,
350*4882a593Smuzhiyun .set_mode = lp8788_buck_set_mode,
351*4882a593Smuzhiyun .get_mode = lp8788_buck_get_mode,
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun static const struct regulator_ops lp8788_buck34_ops = {
355*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
356*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
357*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
358*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
359*4882a593Smuzhiyun .enable = regulator_enable_regmap,
360*4882a593Smuzhiyun .disable = regulator_disable_regmap,
361*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
362*4882a593Smuzhiyun .enable_time = lp8788_buck_enable_time,
363*4882a593Smuzhiyun .set_mode = lp8788_buck_set_mode,
364*4882a593Smuzhiyun .get_mode = lp8788_buck_get_mode,
365*4882a593Smuzhiyun };
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun static const struct regulator_desc lp8788_buck_desc[] = {
368*4882a593Smuzhiyun {
369*4882a593Smuzhiyun .name = "buck1",
370*4882a593Smuzhiyun .id = BUCK1,
371*4882a593Smuzhiyun .ops = &lp8788_buck12_ops,
372*4882a593Smuzhiyun .n_voltages = 26,
373*4882a593Smuzhiyun .linear_ranges = buck_volt_ranges,
374*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(buck_volt_ranges),
375*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
376*4882a593Smuzhiyun .owner = THIS_MODULE,
377*4882a593Smuzhiyun .enable_reg = LP8788_EN_BUCK,
378*4882a593Smuzhiyun .enable_mask = LP8788_EN_BUCK1_M,
379*4882a593Smuzhiyun },
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun .name = "buck2",
382*4882a593Smuzhiyun .id = BUCK2,
383*4882a593Smuzhiyun .ops = &lp8788_buck12_ops,
384*4882a593Smuzhiyun .n_voltages = 26,
385*4882a593Smuzhiyun .linear_ranges = buck_volt_ranges,
386*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(buck_volt_ranges),
387*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
388*4882a593Smuzhiyun .owner = THIS_MODULE,
389*4882a593Smuzhiyun .enable_reg = LP8788_EN_BUCK,
390*4882a593Smuzhiyun .enable_mask = LP8788_EN_BUCK2_M,
391*4882a593Smuzhiyun },
392*4882a593Smuzhiyun {
393*4882a593Smuzhiyun .name = "buck3",
394*4882a593Smuzhiyun .id = BUCK3,
395*4882a593Smuzhiyun .ops = &lp8788_buck34_ops,
396*4882a593Smuzhiyun .n_voltages = 26,
397*4882a593Smuzhiyun .linear_ranges = buck_volt_ranges,
398*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(buck_volt_ranges),
399*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
400*4882a593Smuzhiyun .owner = THIS_MODULE,
401*4882a593Smuzhiyun .vsel_reg = LP8788_BUCK3_VOUT,
402*4882a593Smuzhiyun .vsel_mask = LP8788_VOUT_M,
403*4882a593Smuzhiyun .enable_reg = LP8788_EN_BUCK,
404*4882a593Smuzhiyun .enable_mask = LP8788_EN_BUCK3_M,
405*4882a593Smuzhiyun },
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun .name = "buck4",
408*4882a593Smuzhiyun .id = BUCK4,
409*4882a593Smuzhiyun .ops = &lp8788_buck34_ops,
410*4882a593Smuzhiyun .n_voltages = 26,
411*4882a593Smuzhiyun .linear_ranges = buck_volt_ranges,
412*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(buck_volt_ranges),
413*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
414*4882a593Smuzhiyun .owner = THIS_MODULE,
415*4882a593Smuzhiyun .vsel_reg = LP8788_BUCK4_VOUT,
416*4882a593Smuzhiyun .vsel_mask = LP8788_VOUT_M,
417*4882a593Smuzhiyun .enable_reg = LP8788_EN_BUCK,
418*4882a593Smuzhiyun .enable_mask = LP8788_EN_BUCK4_M,
419*4882a593Smuzhiyun },
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun
lp8788_dvs_gpio_request(struct platform_device * pdev,struct lp8788_buck * buck,enum lp8788_buck_id id)422*4882a593Smuzhiyun static int lp8788_dvs_gpio_request(struct platform_device *pdev,
423*4882a593Smuzhiyun struct lp8788_buck *buck,
424*4882a593Smuzhiyun enum lp8788_buck_id id)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun struct lp8788_platform_data *pdata = buck->lp->pdata;
427*4882a593Smuzhiyun char *b1_name = "LP8788_B1_DVS";
428*4882a593Smuzhiyun char *b2_name[] = { "LP8788_B2_DVS1", "LP8788_B2_DVS2" };
429*4882a593Smuzhiyun int i, gpio, ret;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun switch (id) {
432*4882a593Smuzhiyun case BUCK1:
433*4882a593Smuzhiyun gpio = pdata->buck1_dvs->gpio;
434*4882a593Smuzhiyun ret = devm_gpio_request_one(&pdev->dev, gpio, DVS_LOW,
435*4882a593Smuzhiyun b1_name);
436*4882a593Smuzhiyun if (ret)
437*4882a593Smuzhiyun return ret;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun buck->dvs = pdata->buck1_dvs;
440*4882a593Smuzhiyun break;
441*4882a593Smuzhiyun case BUCK2:
442*4882a593Smuzhiyun for (i = 0; i < LP8788_NUM_BUCK2_DVS; i++) {
443*4882a593Smuzhiyun gpio = pdata->buck2_dvs->gpio[i];
444*4882a593Smuzhiyun ret = devm_gpio_request_one(&pdev->dev, gpio,
445*4882a593Smuzhiyun DVS_LOW, b2_name[i]);
446*4882a593Smuzhiyun if (ret)
447*4882a593Smuzhiyun return ret;
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun buck->dvs = pdata->buck2_dvs;
450*4882a593Smuzhiyun break;
451*4882a593Smuzhiyun default:
452*4882a593Smuzhiyun break;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun return 0;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun
lp8788_init_dvs(struct platform_device * pdev,struct lp8788_buck * buck,enum lp8788_buck_id id)458*4882a593Smuzhiyun static int lp8788_init_dvs(struct platform_device *pdev,
459*4882a593Smuzhiyun struct lp8788_buck *buck, enum lp8788_buck_id id)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun struct lp8788_platform_data *pdata = buck->lp->pdata;
462*4882a593Smuzhiyun u8 mask[] = { LP8788_BUCK1_DVS_SEL_M, LP8788_BUCK2_DVS_SEL_M };
463*4882a593Smuzhiyun u8 val[] = { LP8788_BUCK1_DVS_PIN, LP8788_BUCK2_DVS_PIN };
464*4882a593Smuzhiyun u8 default_dvs_mode[] = { LP8788_BUCK1_DVS_I2C, LP8788_BUCK2_DVS_I2C };
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun /* no dvs for buck3, 4 */
467*4882a593Smuzhiyun if (id > BUCK2)
468*4882a593Smuzhiyun return 0;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun /* no dvs platform data, then dvs will be selected by I2C registers */
471*4882a593Smuzhiyun if (!pdata)
472*4882a593Smuzhiyun goto set_default_dvs_mode;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun if ((id == BUCK1 && !pdata->buck1_dvs) ||
475*4882a593Smuzhiyun (id == BUCK2 && !pdata->buck2_dvs))
476*4882a593Smuzhiyun goto set_default_dvs_mode;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun if (lp8788_dvs_gpio_request(pdev, buck, id))
479*4882a593Smuzhiyun goto set_default_dvs_mode;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun return lp8788_update_bits(buck->lp, LP8788_BUCK_DVS_SEL, mask[id],
482*4882a593Smuzhiyun val[id]);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun set_default_dvs_mode:
485*4882a593Smuzhiyun return lp8788_update_bits(buck->lp, LP8788_BUCK_DVS_SEL, mask[id],
486*4882a593Smuzhiyun default_dvs_mode[id]);
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
lp8788_buck_probe(struct platform_device * pdev)489*4882a593Smuzhiyun static int lp8788_buck_probe(struct platform_device *pdev)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
492*4882a593Smuzhiyun int id = pdev->id;
493*4882a593Smuzhiyun struct lp8788_buck *buck;
494*4882a593Smuzhiyun struct regulator_config cfg = { };
495*4882a593Smuzhiyun struct regulator_dev *rdev;
496*4882a593Smuzhiyun int ret;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun if (id >= LP8788_NUM_BUCKS)
499*4882a593Smuzhiyun return -EINVAL;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun buck = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_buck), GFP_KERNEL);
502*4882a593Smuzhiyun if (!buck)
503*4882a593Smuzhiyun return -ENOMEM;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun buck->lp = lp;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun ret = lp8788_init_dvs(pdev, buck, id);
508*4882a593Smuzhiyun if (ret)
509*4882a593Smuzhiyun return ret;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun cfg.dev = pdev->dev.parent;
512*4882a593Smuzhiyun cfg.init_data = lp->pdata ? lp->pdata->buck_data[id] : NULL;
513*4882a593Smuzhiyun cfg.driver_data = buck;
514*4882a593Smuzhiyun cfg.regmap = lp->regmap;
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev, &lp8788_buck_desc[id], &cfg);
517*4882a593Smuzhiyun if (IS_ERR(rdev)) {
518*4882a593Smuzhiyun ret = PTR_ERR(rdev);
519*4882a593Smuzhiyun dev_err(&pdev->dev, "BUCK%d regulator register err = %d\n",
520*4882a593Smuzhiyun id + 1, ret);
521*4882a593Smuzhiyun return ret;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun buck->regulator = rdev;
525*4882a593Smuzhiyun platform_set_drvdata(pdev, buck);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun return 0;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun static struct platform_driver lp8788_buck_driver = {
531*4882a593Smuzhiyun .probe = lp8788_buck_probe,
532*4882a593Smuzhiyun .driver = {
533*4882a593Smuzhiyun .name = LP8788_DEV_BUCK,
534*4882a593Smuzhiyun },
535*4882a593Smuzhiyun };
536*4882a593Smuzhiyun
lp8788_buck_init(void)537*4882a593Smuzhiyun static int __init lp8788_buck_init(void)
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun return platform_driver_register(&lp8788_buck_driver);
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun subsys_initcall(lp8788_buck_init);
542*4882a593Smuzhiyun
lp8788_buck_exit(void)543*4882a593Smuzhiyun static void __exit lp8788_buck_exit(void)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun platform_driver_unregister(&lp8788_buck_driver);
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun module_exit(lp8788_buck_exit);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun MODULE_DESCRIPTION("TI LP8788 BUCK Driver");
550*4882a593Smuzhiyun MODULE_AUTHOR("Milo Kim");
551*4882a593Smuzhiyun MODULE_LICENSE("GPL");
552*4882a593Smuzhiyun MODULE_ALIAS("platform:lp8788-buck");
553