xref: /OK3568_Linux_fs/kernel/drivers/regulator/lp3971.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Regulator driver for National Semiconductors LP3971 PMIC chip
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 2009 Samsung Electronics
6*4882a593Smuzhiyun  *  Author: Marek Szyprowski <m.szyprowski@samsung.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Based on wm8350.c
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/bug.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/regulator/driver.h>
17*4882a593Smuzhiyun #include <linux/regulator/lp3971.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun struct lp3971 {
21*4882a593Smuzhiyun 	struct device *dev;
22*4882a593Smuzhiyun 	struct mutex io_lock;
23*4882a593Smuzhiyun 	struct i2c_client *i2c;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun static u8 lp3971_reg_read(struct lp3971 *lp3971, u8 reg);
27*4882a593Smuzhiyun static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val);
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define LP3971_SYS_CONTROL1_REG 0x07
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /* System control register 1 initial value,
32*4882a593Smuzhiyun    bits 4 and 5 are EPROM programmable */
33*4882a593Smuzhiyun #define SYS_CONTROL1_INIT_VAL 0x40
34*4882a593Smuzhiyun #define SYS_CONTROL1_INIT_MASK 0xCF
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define LP3971_BUCK_VOL_ENABLE_REG 0x10
37*4882a593Smuzhiyun #define LP3971_BUCK_VOL_CHANGE_REG 0x20
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /*	Voltage control registers shift:
40*4882a593Smuzhiyun 	LP3971_BUCK1 -> 0
41*4882a593Smuzhiyun 	LP3971_BUCK2 -> 4
42*4882a593Smuzhiyun 	LP3971_BUCK3 -> 6
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun #define BUCK_VOL_CHANGE_SHIFT(x) (((!!x) << 2) | (x & ~0x01))
45*4882a593Smuzhiyun #define BUCK_VOL_CHANGE_FLAG_GO 0x01
46*4882a593Smuzhiyun #define BUCK_VOL_CHANGE_FLAG_TARGET 0x02
47*4882a593Smuzhiyun #define BUCK_VOL_CHANGE_FLAG_MASK 0x03
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define LP3971_BUCK1_BASE 0x23
50*4882a593Smuzhiyun #define LP3971_BUCK2_BASE 0x29
51*4882a593Smuzhiyun #define LP3971_BUCK3_BASE 0x32
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun static const int buck_base_addr[] = {
54*4882a593Smuzhiyun 	LP3971_BUCK1_BASE,
55*4882a593Smuzhiyun 	LP3971_BUCK2_BASE,
56*4882a593Smuzhiyun 	LP3971_BUCK3_BASE,
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define LP3971_BUCK_TARGET_VOL1_REG(x) (buck_base_addr[x])
60*4882a593Smuzhiyun #define LP3971_BUCK_TARGET_VOL2_REG(x) (buck_base_addr[x]+1)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun static const unsigned int buck_voltage_map[] = {
63*4882a593Smuzhiyun 	      0,  800000,  850000,  900000,  950000, 1000000, 1050000, 1100000,
64*4882a593Smuzhiyun 	1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000,
65*4882a593Smuzhiyun 	1550000, 1600000, 1650000, 1700000, 1800000, 1900000, 2500000, 2800000,
66*4882a593Smuzhiyun 	3000000, 3300000,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define BUCK_TARGET_VOL_MASK 0x3f
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define LP3971_BUCK_RAMP_REG(x)	(buck_base_addr[x]+2)
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define LP3971_LDO_ENABLE_REG 0x12
74*4882a593Smuzhiyun #define LP3971_LDO_VOL_CONTR_BASE 0x39
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /*	Voltage control registers:
77*4882a593Smuzhiyun 	LP3971_LDO1 -> LP3971_LDO_VOL_CONTR_BASE + 0
78*4882a593Smuzhiyun 	LP3971_LDO2 -> LP3971_LDO_VOL_CONTR_BASE + 0
79*4882a593Smuzhiyun 	LP3971_LDO3 -> LP3971_LDO_VOL_CONTR_BASE + 1
80*4882a593Smuzhiyun 	LP3971_LDO4 -> LP3971_LDO_VOL_CONTR_BASE + 1
81*4882a593Smuzhiyun 	LP3971_LDO5 -> LP3971_LDO_VOL_CONTR_BASE + 2
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun #define LP3971_LDO_VOL_CONTR_REG(x)	(LP3971_LDO_VOL_CONTR_BASE + (x >> 1))
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /*	Voltage control registers shift:
86*4882a593Smuzhiyun 	LP3971_LDO1 -> 0, LP3971_LDO2 -> 4
87*4882a593Smuzhiyun 	LP3971_LDO3 -> 0, LP3971_LDO4 -> 4
88*4882a593Smuzhiyun 	LP3971_LDO5 -> 0
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun #define LDO_VOL_CONTR_SHIFT(x) ((x & 1) << 2)
91*4882a593Smuzhiyun #define LDO_VOL_CONTR_MASK 0x0f
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun static const unsigned int ldo45_voltage_map[] = {
94*4882a593Smuzhiyun 	1000000, 1050000, 1100000, 1150000, 1200000, 1250000, 1300000, 1350000,
95*4882a593Smuzhiyun 	1400000, 1500000, 1800000, 1900000, 2500000, 2800000, 3000000, 3300000,
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun static const unsigned int ldo123_voltage_map[] = {
99*4882a593Smuzhiyun 	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
100*4882a593Smuzhiyun 	2600000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun #define LDO_VOL_MIN_IDX 0x00
104*4882a593Smuzhiyun #define LDO_VOL_MAX_IDX 0x0f
105*4882a593Smuzhiyun 
lp3971_ldo_is_enabled(struct regulator_dev * dev)106*4882a593Smuzhiyun static int lp3971_ldo_is_enabled(struct regulator_dev *dev)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
109*4882a593Smuzhiyun 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
110*4882a593Smuzhiyun 	u16 mask = 1 << (1 + ldo);
111*4882a593Smuzhiyun 	u16 val;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	val = lp3971_reg_read(lp3971, LP3971_LDO_ENABLE_REG);
114*4882a593Smuzhiyun 	return (val & mask) != 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
lp3971_ldo_enable(struct regulator_dev * dev)117*4882a593Smuzhiyun static int lp3971_ldo_enable(struct regulator_dev *dev)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
120*4882a593Smuzhiyun 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
121*4882a593Smuzhiyun 	u16 mask = 1 << (1 + ldo);
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, mask);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
lp3971_ldo_disable(struct regulator_dev * dev)126*4882a593Smuzhiyun static int lp3971_ldo_disable(struct regulator_dev *dev)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
129*4882a593Smuzhiyun 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
130*4882a593Smuzhiyun 	u16 mask = 1 << (1 + ldo);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, 0);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
lp3971_ldo_get_voltage_sel(struct regulator_dev * dev)135*4882a593Smuzhiyun static int lp3971_ldo_get_voltage_sel(struct regulator_dev *dev)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
138*4882a593Smuzhiyun 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
139*4882a593Smuzhiyun 	u16 val, reg;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	reg = lp3971_reg_read(lp3971, LP3971_LDO_VOL_CONTR_REG(ldo));
142*4882a593Smuzhiyun 	val = (reg >> LDO_VOL_CONTR_SHIFT(ldo)) & LDO_VOL_CONTR_MASK;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	return val;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
lp3971_ldo_set_voltage_sel(struct regulator_dev * dev,unsigned int selector)147*4882a593Smuzhiyun static int lp3971_ldo_set_voltage_sel(struct regulator_dev *dev,
148*4882a593Smuzhiyun 				      unsigned int selector)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
151*4882a593Smuzhiyun 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	return lp3971_set_bits(lp3971, LP3971_LDO_VOL_CONTR_REG(ldo),
154*4882a593Smuzhiyun 			LDO_VOL_CONTR_MASK << LDO_VOL_CONTR_SHIFT(ldo),
155*4882a593Smuzhiyun 			selector << LDO_VOL_CONTR_SHIFT(ldo));
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun static const struct regulator_ops lp3971_ldo_ops = {
159*4882a593Smuzhiyun 	.list_voltage = regulator_list_voltage_table,
160*4882a593Smuzhiyun 	.map_voltage = regulator_map_voltage_ascend,
161*4882a593Smuzhiyun 	.is_enabled = lp3971_ldo_is_enabled,
162*4882a593Smuzhiyun 	.enable = lp3971_ldo_enable,
163*4882a593Smuzhiyun 	.disable = lp3971_ldo_disable,
164*4882a593Smuzhiyun 	.get_voltage_sel = lp3971_ldo_get_voltage_sel,
165*4882a593Smuzhiyun 	.set_voltage_sel = lp3971_ldo_set_voltage_sel,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
lp3971_dcdc_is_enabled(struct regulator_dev * dev)168*4882a593Smuzhiyun static int lp3971_dcdc_is_enabled(struct regulator_dev *dev)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
171*4882a593Smuzhiyun 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
172*4882a593Smuzhiyun 	u16 mask = 1 << (buck * 2);
173*4882a593Smuzhiyun 	u16 val;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	val = lp3971_reg_read(lp3971, LP3971_BUCK_VOL_ENABLE_REG);
176*4882a593Smuzhiyun 	return (val & mask) != 0;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun 
lp3971_dcdc_enable(struct regulator_dev * dev)179*4882a593Smuzhiyun static int lp3971_dcdc_enable(struct regulator_dev *dev)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
182*4882a593Smuzhiyun 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
183*4882a593Smuzhiyun 	u16 mask = 1 << (buck * 2);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_ENABLE_REG, mask, mask);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
lp3971_dcdc_disable(struct regulator_dev * dev)188*4882a593Smuzhiyun static int lp3971_dcdc_disable(struct regulator_dev *dev)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
191*4882a593Smuzhiyun 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
192*4882a593Smuzhiyun 	u16 mask = 1 << (buck * 2);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_ENABLE_REG, mask, 0);
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun 
lp3971_dcdc_get_voltage_sel(struct regulator_dev * dev)197*4882a593Smuzhiyun static int lp3971_dcdc_get_voltage_sel(struct regulator_dev *dev)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
200*4882a593Smuzhiyun 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
201*4882a593Smuzhiyun 	u16 reg;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	reg = lp3971_reg_read(lp3971, LP3971_BUCK_TARGET_VOL1_REG(buck));
204*4882a593Smuzhiyun 	reg &= BUCK_TARGET_VOL_MASK;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	return reg;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
lp3971_dcdc_set_voltage_sel(struct regulator_dev * dev,unsigned int selector)209*4882a593Smuzhiyun static int lp3971_dcdc_set_voltage_sel(struct regulator_dev *dev,
210*4882a593Smuzhiyun 				       unsigned int selector)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
213*4882a593Smuzhiyun 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
214*4882a593Smuzhiyun 	int ret;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	ret = lp3971_set_bits(lp3971, LP3971_BUCK_TARGET_VOL1_REG(buck),
217*4882a593Smuzhiyun 	       BUCK_TARGET_VOL_MASK, selector);
218*4882a593Smuzhiyun 	if (ret)
219*4882a593Smuzhiyun 		return ret;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	ret = lp3971_set_bits(lp3971, LP3971_BUCK_VOL_CHANGE_REG,
222*4882a593Smuzhiyun 	       BUCK_VOL_CHANGE_FLAG_MASK << BUCK_VOL_CHANGE_SHIFT(buck),
223*4882a593Smuzhiyun 	       BUCK_VOL_CHANGE_FLAG_GO << BUCK_VOL_CHANGE_SHIFT(buck));
224*4882a593Smuzhiyun 	if (ret)
225*4882a593Smuzhiyun 		return ret;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_CHANGE_REG,
228*4882a593Smuzhiyun 	       BUCK_VOL_CHANGE_FLAG_MASK << BUCK_VOL_CHANGE_SHIFT(buck),
229*4882a593Smuzhiyun 	       0 << BUCK_VOL_CHANGE_SHIFT(buck));
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun static const struct regulator_ops lp3971_dcdc_ops = {
233*4882a593Smuzhiyun 	.list_voltage = regulator_list_voltage_table,
234*4882a593Smuzhiyun 	.map_voltage = regulator_map_voltage_ascend,
235*4882a593Smuzhiyun 	.is_enabled = lp3971_dcdc_is_enabled,
236*4882a593Smuzhiyun 	.enable = lp3971_dcdc_enable,
237*4882a593Smuzhiyun 	.disable = lp3971_dcdc_disable,
238*4882a593Smuzhiyun 	.get_voltage_sel = lp3971_dcdc_get_voltage_sel,
239*4882a593Smuzhiyun 	.set_voltage_sel = lp3971_dcdc_set_voltage_sel,
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun static const struct regulator_desc regulators[] = {
243*4882a593Smuzhiyun 	{
244*4882a593Smuzhiyun 		.name = "LDO1",
245*4882a593Smuzhiyun 		.id = LP3971_LDO1,
246*4882a593Smuzhiyun 		.ops = &lp3971_ldo_ops,
247*4882a593Smuzhiyun 		.n_voltages = ARRAY_SIZE(ldo123_voltage_map),
248*4882a593Smuzhiyun 		.volt_table = ldo123_voltage_map,
249*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,
250*4882a593Smuzhiyun 		.owner = THIS_MODULE,
251*4882a593Smuzhiyun 	},
252*4882a593Smuzhiyun 	{
253*4882a593Smuzhiyun 		.name = "LDO2",
254*4882a593Smuzhiyun 		.id = LP3971_LDO2,
255*4882a593Smuzhiyun 		.ops = &lp3971_ldo_ops,
256*4882a593Smuzhiyun 		.n_voltages = ARRAY_SIZE(ldo123_voltage_map),
257*4882a593Smuzhiyun 		.volt_table = ldo123_voltage_map,
258*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,
259*4882a593Smuzhiyun 		.owner = THIS_MODULE,
260*4882a593Smuzhiyun 	},
261*4882a593Smuzhiyun 	{
262*4882a593Smuzhiyun 		.name = "LDO3",
263*4882a593Smuzhiyun 		.id = LP3971_LDO3,
264*4882a593Smuzhiyun 		.ops = &lp3971_ldo_ops,
265*4882a593Smuzhiyun 		.n_voltages = ARRAY_SIZE(ldo123_voltage_map),
266*4882a593Smuzhiyun 		.volt_table = ldo123_voltage_map,
267*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,
268*4882a593Smuzhiyun 		.owner = THIS_MODULE,
269*4882a593Smuzhiyun 	},
270*4882a593Smuzhiyun 	{
271*4882a593Smuzhiyun 		.name = "LDO4",
272*4882a593Smuzhiyun 		.id = LP3971_LDO4,
273*4882a593Smuzhiyun 		.ops = &lp3971_ldo_ops,
274*4882a593Smuzhiyun 		.n_voltages = ARRAY_SIZE(ldo45_voltage_map),
275*4882a593Smuzhiyun 		.volt_table = ldo45_voltage_map,
276*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,
277*4882a593Smuzhiyun 		.owner = THIS_MODULE,
278*4882a593Smuzhiyun 	},
279*4882a593Smuzhiyun 	{
280*4882a593Smuzhiyun 		.name = "LDO5",
281*4882a593Smuzhiyun 		.id = LP3971_LDO5,
282*4882a593Smuzhiyun 		.ops = &lp3971_ldo_ops,
283*4882a593Smuzhiyun 		.n_voltages = ARRAY_SIZE(ldo45_voltage_map),
284*4882a593Smuzhiyun 		.volt_table = ldo45_voltage_map,
285*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,
286*4882a593Smuzhiyun 		.owner = THIS_MODULE,
287*4882a593Smuzhiyun 	},
288*4882a593Smuzhiyun 	{
289*4882a593Smuzhiyun 		.name = "DCDC1",
290*4882a593Smuzhiyun 		.id = LP3971_DCDC1,
291*4882a593Smuzhiyun 		.ops = &lp3971_dcdc_ops,
292*4882a593Smuzhiyun 		.n_voltages = ARRAY_SIZE(buck_voltage_map),
293*4882a593Smuzhiyun 		.volt_table = buck_voltage_map,
294*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,
295*4882a593Smuzhiyun 		.owner = THIS_MODULE,
296*4882a593Smuzhiyun 	},
297*4882a593Smuzhiyun 	{
298*4882a593Smuzhiyun 		.name = "DCDC2",
299*4882a593Smuzhiyun 		.id = LP3971_DCDC2,
300*4882a593Smuzhiyun 		.ops = &lp3971_dcdc_ops,
301*4882a593Smuzhiyun 		.n_voltages = ARRAY_SIZE(buck_voltage_map),
302*4882a593Smuzhiyun 		.volt_table = buck_voltage_map,
303*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,
304*4882a593Smuzhiyun 		.owner = THIS_MODULE,
305*4882a593Smuzhiyun 	},
306*4882a593Smuzhiyun 	{
307*4882a593Smuzhiyun 		.name = "DCDC3",
308*4882a593Smuzhiyun 		.id = LP3971_DCDC3,
309*4882a593Smuzhiyun 		.ops = &lp3971_dcdc_ops,
310*4882a593Smuzhiyun 		.n_voltages = ARRAY_SIZE(buck_voltage_map),
311*4882a593Smuzhiyun 		.volt_table = buck_voltage_map,
312*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,
313*4882a593Smuzhiyun 		.owner = THIS_MODULE,
314*4882a593Smuzhiyun 	},
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun 
lp3971_i2c_read(struct i2c_client * i2c,char reg,int count,u16 * dest)317*4882a593Smuzhiyun static int lp3971_i2c_read(struct i2c_client *i2c, char reg, int count,
318*4882a593Smuzhiyun 	u16 *dest)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun 	int ret;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	if (count != 1)
323*4882a593Smuzhiyun 		return -EIO;
324*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(i2c, reg);
325*4882a593Smuzhiyun 	if (ret < 0)
326*4882a593Smuzhiyun 		return ret;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	*dest = ret;
329*4882a593Smuzhiyun 	return 0;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun 
lp3971_i2c_write(struct i2c_client * i2c,char reg,int count,const u16 * src)332*4882a593Smuzhiyun static int lp3971_i2c_write(struct i2c_client *i2c, char reg, int count,
333*4882a593Smuzhiyun 	const u16 *src)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun 	if (count != 1)
336*4882a593Smuzhiyun 		return -EIO;
337*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(i2c, reg, *src);
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun 
lp3971_reg_read(struct lp3971 * lp3971,u8 reg)340*4882a593Smuzhiyun static u8 lp3971_reg_read(struct lp3971 *lp3971, u8 reg)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun 	u16 val = 0;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	mutex_lock(&lp3971->io_lock);
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	lp3971_i2c_read(lp3971->i2c, reg, 1, &val);
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	dev_dbg(lp3971->dev, "reg read 0x%02x -> 0x%02x\n", (int)reg,
349*4882a593Smuzhiyun 		(unsigned)val&0xff);
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	mutex_unlock(&lp3971->io_lock);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	return val & 0xff;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun 
lp3971_set_bits(struct lp3971 * lp3971,u8 reg,u16 mask,u16 val)356*4882a593Smuzhiyun static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	u16 tmp;
359*4882a593Smuzhiyun 	int ret;
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	mutex_lock(&lp3971->io_lock);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	ret = lp3971_i2c_read(lp3971->i2c, reg, 1, &tmp);
364*4882a593Smuzhiyun 	if (ret == 0) {
365*4882a593Smuzhiyun 		tmp = (tmp & ~mask) | val;
366*4882a593Smuzhiyun 		ret = lp3971_i2c_write(lp3971->i2c, reg, 1, &tmp);
367*4882a593Smuzhiyun 		dev_dbg(lp3971->dev, "reg write 0x%02x -> 0x%02x\n", (int)reg,
368*4882a593Smuzhiyun 			(unsigned)val&0xff);
369*4882a593Smuzhiyun 	}
370*4882a593Smuzhiyun 	mutex_unlock(&lp3971->io_lock);
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	return ret;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun 
setup_regulators(struct lp3971 * lp3971,struct lp3971_platform_data * pdata)375*4882a593Smuzhiyun static int setup_regulators(struct lp3971 *lp3971,
376*4882a593Smuzhiyun 				      struct lp3971_platform_data *pdata)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun 	int i, err;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	/* Instantiate the regulators */
381*4882a593Smuzhiyun 	for (i = 0; i < pdata->num_regulators; i++) {
382*4882a593Smuzhiyun 		struct regulator_config config = { };
383*4882a593Smuzhiyun 		struct lp3971_regulator_subdev *reg = &pdata->regulators[i];
384*4882a593Smuzhiyun 		struct regulator_dev *rdev;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 		config.dev = lp3971->dev;
387*4882a593Smuzhiyun 		config.init_data = reg->initdata;
388*4882a593Smuzhiyun 		config.driver_data = lp3971;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 		rdev = devm_regulator_register(lp3971->dev,
391*4882a593Smuzhiyun 					       &regulators[reg->id], &config);
392*4882a593Smuzhiyun 		if (IS_ERR(rdev)) {
393*4882a593Smuzhiyun 			err = PTR_ERR(rdev);
394*4882a593Smuzhiyun 			dev_err(lp3971->dev, "regulator init failed: %d\n",
395*4882a593Smuzhiyun 				err);
396*4882a593Smuzhiyun 			return err;
397*4882a593Smuzhiyun 		}
398*4882a593Smuzhiyun 	}
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	return 0;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun 
lp3971_i2c_probe(struct i2c_client * i2c)403*4882a593Smuzhiyun static int lp3971_i2c_probe(struct i2c_client *i2c)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct lp3971 *lp3971;
406*4882a593Smuzhiyun 	struct lp3971_platform_data *pdata = dev_get_platdata(&i2c->dev);
407*4882a593Smuzhiyun 	int ret;
408*4882a593Smuzhiyun 	u16 val;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	if (!pdata) {
411*4882a593Smuzhiyun 		dev_dbg(&i2c->dev, "No platform init data supplied\n");
412*4882a593Smuzhiyun 		return -ENODEV;
413*4882a593Smuzhiyun 	}
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	lp3971 = devm_kzalloc(&i2c->dev, sizeof(struct lp3971), GFP_KERNEL);
416*4882a593Smuzhiyun 	if (lp3971 == NULL)
417*4882a593Smuzhiyun 		return -ENOMEM;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	lp3971->i2c = i2c;
420*4882a593Smuzhiyun 	lp3971->dev = &i2c->dev;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	mutex_init(&lp3971->io_lock);
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	/* Detect LP3971 */
425*4882a593Smuzhiyun 	ret = lp3971_i2c_read(i2c, LP3971_SYS_CONTROL1_REG, 1, &val);
426*4882a593Smuzhiyun 	if (ret == 0 && (val & SYS_CONTROL1_INIT_MASK) != SYS_CONTROL1_INIT_VAL)
427*4882a593Smuzhiyun 		ret = -ENODEV;
428*4882a593Smuzhiyun 	if (ret < 0) {
429*4882a593Smuzhiyun 		dev_err(&i2c->dev, "failed to detect device\n");
430*4882a593Smuzhiyun 		return ret;
431*4882a593Smuzhiyun 	}
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	ret = setup_regulators(lp3971, pdata);
434*4882a593Smuzhiyun 	if (ret < 0)
435*4882a593Smuzhiyun 		return ret;
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, lp3971);
438*4882a593Smuzhiyun 	return 0;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun static const struct i2c_device_id lp3971_i2c_id[] = {
442*4882a593Smuzhiyun 	{ "lp3971", 0 },
443*4882a593Smuzhiyun 	{ }
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, lp3971_i2c_id);
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun static struct i2c_driver lp3971_i2c_driver = {
448*4882a593Smuzhiyun 	.driver = {
449*4882a593Smuzhiyun 		.name = "LP3971",
450*4882a593Smuzhiyun 	},
451*4882a593Smuzhiyun 	.probe_new = lp3971_i2c_probe,
452*4882a593Smuzhiyun 	.id_table = lp3971_i2c_id,
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun module_i2c_driver(lp3971_i2c_driver);
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun MODULE_LICENSE("GPL");
458*4882a593Smuzhiyun MODULE_AUTHOR("Marek Szyprowski <m.szyprowski@samsung.com>");
459*4882a593Smuzhiyun MODULE_DESCRIPTION("LP3971 PMIC driver");
460