1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * isl9305 - Intersil ISL9305 DCDC regulator
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2014 Linaro Ltd
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Mark Brown <broonie@kernel.org>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/platform_data/isl9305.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/regulator/driver.h>
17*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Registers
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun #define ISL9305_DCD1OUT 0x0
24*4882a593Smuzhiyun #define ISL9305_DCD2OUT 0x1
25*4882a593Smuzhiyun #define ISL9305_LDO1OUT 0x2
26*4882a593Smuzhiyun #define ISL9305_LDO2OUT 0x3
27*4882a593Smuzhiyun #define ISL9305_DCD_PARAMETER 0x4
28*4882a593Smuzhiyun #define ISL9305_SYSTEM_PARAMETER 0x5
29*4882a593Smuzhiyun #define ISL9305_DCD_SRCTL 0x6
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define ISL9305_MAX_REG ISL9305_DCD_SRCTL
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * DCD_PARAMETER
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun #define ISL9305_DCD_PHASE 0x40
37*4882a593Smuzhiyun #define ISL9305_DCD2_ULTRA 0x20
38*4882a593Smuzhiyun #define ISL9305_DCD1_ULTRA 0x10
39*4882a593Smuzhiyun #define ISL9305_DCD2_BLD 0x08
40*4882a593Smuzhiyun #define ISL9305_DCD1_BLD 0x04
41*4882a593Smuzhiyun #define ISL9305_DCD2_MODE 0x02
42*4882a593Smuzhiyun #define ISL9305_DCD1_MODE 0x01
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * SYSTEM_PARAMETER
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun #define ISL9305_I2C_EN 0x40
48*4882a593Smuzhiyun #define ISL9305_DCDPOR_MASK 0x30
49*4882a593Smuzhiyun #define ISL9305_LDO2_EN 0x08
50*4882a593Smuzhiyun #define ISL9305_LDO1_EN 0x04
51*4882a593Smuzhiyun #define ISL9305_DCD2_EN 0x02
52*4882a593Smuzhiyun #define ISL9305_DCD1_EN 0x01
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * DCD_SRCTL
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun #define ISL9305_DCD2SR_MASK 0xc0
58*4882a593Smuzhiyun #define ISL9305_DCD1SR_MASK 0x07
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct regulator_ops isl9305_ops = {
61*4882a593Smuzhiyun .enable = regulator_enable_regmap,
62*4882a593Smuzhiyun .disable = regulator_disable_regmap,
63*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
64*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
65*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
66*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static const struct regulator_desc isl9305_regulators[] = {
70*4882a593Smuzhiyun [ISL9305_DCD1] = {
71*4882a593Smuzhiyun .name = "DCD1",
72*4882a593Smuzhiyun .of_match = of_match_ptr("dcd1"),
73*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
74*4882a593Smuzhiyun .n_voltages = 0x70,
75*4882a593Smuzhiyun .min_uV = 825000,
76*4882a593Smuzhiyun .uV_step = 25000,
77*4882a593Smuzhiyun .vsel_reg = ISL9305_DCD1OUT,
78*4882a593Smuzhiyun .vsel_mask = 0x7f,
79*4882a593Smuzhiyun .enable_reg = ISL9305_SYSTEM_PARAMETER,
80*4882a593Smuzhiyun .enable_mask = ISL9305_DCD1_EN,
81*4882a593Smuzhiyun .supply_name = "VINDCD1",
82*4882a593Smuzhiyun .ops = &isl9305_ops,
83*4882a593Smuzhiyun .owner = THIS_MODULE,
84*4882a593Smuzhiyun },
85*4882a593Smuzhiyun [ISL9305_DCD2] = {
86*4882a593Smuzhiyun .name = "DCD2",
87*4882a593Smuzhiyun .of_match = of_match_ptr("dcd2"),
88*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
89*4882a593Smuzhiyun .n_voltages = 0x70,
90*4882a593Smuzhiyun .min_uV = 825000,
91*4882a593Smuzhiyun .uV_step = 25000,
92*4882a593Smuzhiyun .vsel_reg = ISL9305_DCD2OUT,
93*4882a593Smuzhiyun .vsel_mask = 0x7f,
94*4882a593Smuzhiyun .enable_reg = ISL9305_SYSTEM_PARAMETER,
95*4882a593Smuzhiyun .enable_mask = ISL9305_DCD2_EN,
96*4882a593Smuzhiyun .supply_name = "VINDCD2",
97*4882a593Smuzhiyun .ops = &isl9305_ops,
98*4882a593Smuzhiyun .owner = THIS_MODULE,
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun [ISL9305_LDO1] = {
101*4882a593Smuzhiyun .name = "LDO1",
102*4882a593Smuzhiyun .of_match = of_match_ptr("ldo1"),
103*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
104*4882a593Smuzhiyun .n_voltages = 0x37,
105*4882a593Smuzhiyun .min_uV = 900000,
106*4882a593Smuzhiyun .uV_step = 50000,
107*4882a593Smuzhiyun .vsel_reg = ISL9305_LDO1OUT,
108*4882a593Smuzhiyun .vsel_mask = 0x3f,
109*4882a593Smuzhiyun .enable_reg = ISL9305_SYSTEM_PARAMETER,
110*4882a593Smuzhiyun .enable_mask = ISL9305_LDO1_EN,
111*4882a593Smuzhiyun .supply_name = "VINLDO1",
112*4882a593Smuzhiyun .ops = &isl9305_ops,
113*4882a593Smuzhiyun .owner = THIS_MODULE,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun [ISL9305_LDO2] = {
116*4882a593Smuzhiyun .name = "LDO2",
117*4882a593Smuzhiyun .of_match = of_match_ptr("ldo2"),
118*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
119*4882a593Smuzhiyun .n_voltages = 0x37,
120*4882a593Smuzhiyun .min_uV = 900000,
121*4882a593Smuzhiyun .uV_step = 50000,
122*4882a593Smuzhiyun .vsel_reg = ISL9305_LDO2OUT,
123*4882a593Smuzhiyun .vsel_mask = 0x3f,
124*4882a593Smuzhiyun .enable_reg = ISL9305_SYSTEM_PARAMETER,
125*4882a593Smuzhiyun .enable_mask = ISL9305_LDO2_EN,
126*4882a593Smuzhiyun .supply_name = "VINLDO2",
127*4882a593Smuzhiyun .ops = &isl9305_ops,
128*4882a593Smuzhiyun .owner = THIS_MODULE,
129*4882a593Smuzhiyun },
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun static const struct regmap_config isl9305_regmap = {
133*4882a593Smuzhiyun .reg_bits = 8,
134*4882a593Smuzhiyun .val_bits = 8,
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun .max_register = ISL9305_MAX_REG,
137*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
isl9305_i2c_probe(struct i2c_client * i2c)140*4882a593Smuzhiyun static int isl9305_i2c_probe(struct i2c_client *i2c)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun struct regulator_config config = { };
143*4882a593Smuzhiyun struct isl9305_pdata *pdata = i2c->dev.platform_data;
144*4882a593Smuzhiyun struct regulator_dev *rdev;
145*4882a593Smuzhiyun struct regmap *regmap;
146*4882a593Smuzhiyun int i, ret;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun regmap = devm_regmap_init_i2c(i2c, &isl9305_regmap);
149*4882a593Smuzhiyun if (IS_ERR(regmap)) {
150*4882a593Smuzhiyun ret = PTR_ERR(regmap);
151*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
152*4882a593Smuzhiyun return ret;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun config.dev = &i2c->dev;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(isl9305_regulators); i++) {
158*4882a593Smuzhiyun if (pdata)
159*4882a593Smuzhiyun config.init_data = pdata->init_data[i];
160*4882a593Smuzhiyun else
161*4882a593Smuzhiyun config.init_data = NULL;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun rdev = devm_regulator_register(&i2c->dev,
164*4882a593Smuzhiyun &isl9305_regulators[i],
165*4882a593Smuzhiyun &config);
166*4882a593Smuzhiyun if (IS_ERR(rdev)) {
167*4882a593Smuzhiyun ret = PTR_ERR(rdev);
168*4882a593Smuzhiyun dev_err(&i2c->dev, "Failed to register %s: %d\n",
169*4882a593Smuzhiyun isl9305_regulators[i].name, ret);
170*4882a593Smuzhiyun return ret;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun return 0;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun #ifdef CONFIG_OF
178*4882a593Smuzhiyun static const struct of_device_id isl9305_dt_ids[] = {
179*4882a593Smuzhiyun { .compatible = "isl,isl9305" }, /* for backward compat., don't use */
180*4882a593Smuzhiyun { .compatible = "isil,isl9305" },
181*4882a593Smuzhiyun { .compatible = "isl,isl9305h" }, /* for backward compat., don't use */
182*4882a593Smuzhiyun { .compatible = "isil,isl9305h" },
183*4882a593Smuzhiyun {},
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, isl9305_dt_ids);
186*4882a593Smuzhiyun #endif
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun static const struct i2c_device_id isl9305_i2c_id[] = {
189*4882a593Smuzhiyun { "isl9305", },
190*4882a593Smuzhiyun { "isl9305h", },
191*4882a593Smuzhiyun { }
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, isl9305_i2c_id);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static struct i2c_driver isl9305_regulator_driver = {
196*4882a593Smuzhiyun .driver = {
197*4882a593Smuzhiyun .name = "isl9305",
198*4882a593Smuzhiyun .of_match_table = of_match_ptr(isl9305_dt_ids),
199*4882a593Smuzhiyun },
200*4882a593Smuzhiyun .probe_new = isl9305_i2c_probe,
201*4882a593Smuzhiyun .id_table = isl9305_i2c_id,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun module_i2c_driver(isl9305_regulator_driver);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun MODULE_AUTHOR("Mark Brown");
207*4882a593Smuzhiyun MODULE_DESCRIPTION("Intersil ISL9305 DCDC regulator");
208*4882a593Smuzhiyun MODULE_LICENSE("GPL");
209