1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * da9211-regulator.h - Regulator definitions for DA9211/DA9212 4*4882a593Smuzhiyun * /DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 5*4882a593Smuzhiyun * Copyright (C) 2015 Dialog Semiconductor Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DA9211_REGISTERS_H__ 9*4882a593Smuzhiyun #define __DA9211_REGISTERS_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Page selection */ 12*4882a593Smuzhiyun #define DA9211_REG_PAGE_CON 0x00 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* System Control and Event Registers */ 15*4882a593Smuzhiyun #define DA9211_REG_STATUS_A 0x50 16*4882a593Smuzhiyun #define DA9211_REG_STATUS_B 0x51 17*4882a593Smuzhiyun #define DA9211_REG_EVENT_A 0x52 18*4882a593Smuzhiyun #define DA9211_REG_EVENT_B 0x53 19*4882a593Smuzhiyun #define DA9211_REG_MASK_A 0x54 20*4882a593Smuzhiyun #define DA9211_REG_MASK_B 0x55 21*4882a593Smuzhiyun #define DA9211_REG_CONTROL_A 0x56 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* GPIO Control Registers */ 24*4882a593Smuzhiyun #define DA9211_REG_GPIO_0_1 0x58 25*4882a593Smuzhiyun #define DA9211_REG_GPIO_2_3 0x59 26*4882a593Smuzhiyun #define DA9211_REG_GPIO_4 0x5A 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Regulator Registers */ 29*4882a593Smuzhiyun #define DA9211_REG_BUCKA_CONT 0x5D 30*4882a593Smuzhiyun #define DA9211_REG_BUCKB_CONT 0x5E 31*4882a593Smuzhiyun #define DA9211_REG_BUCK_ILIM 0xD0 32*4882a593Smuzhiyun #define DA9211_REG_BUCKA_CONF 0xD1 33*4882a593Smuzhiyun #define DA9211_REG_BUCKB_CONF 0xD2 34*4882a593Smuzhiyun #define DA9211_REG_BUCK_CONF 0xD3 35*4882a593Smuzhiyun #define DA9211_REG_VBACKA_MAX 0xD5 36*4882a593Smuzhiyun #define DA9211_REG_VBACKB_MAX 0xD6 37*4882a593Smuzhiyun #define DA9211_REG_VBUCKA_A 0xD7 38*4882a593Smuzhiyun #define DA9211_REG_VBUCKA_B 0xD8 39*4882a593Smuzhiyun #define DA9211_REG_VBUCKB_A 0xD9 40*4882a593Smuzhiyun #define DA9211_REG_VBUCKB_B 0xDA 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* I2C Interface Settings */ 43*4882a593Smuzhiyun #define DA9211_REG_INTERFACE 0x105 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* BUCK Phase Selection*/ 46*4882a593Smuzhiyun #define DA9211_REG_CONFIG_E 0x147 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Device ID */ 49*4882a593Smuzhiyun #define DA9211_REG_DEVICE_ID 0x201 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Registers bits 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun /* DA9211_REG_PAGE_CON (addr=0x00) */ 55*4882a593Smuzhiyun #define DA9211_REG_PAGE_SHIFT 1 56*4882a593Smuzhiyun #define DA9211_REG_PAGE_MASK 0x06 57*4882a593Smuzhiyun /* On I2C registers 0x00 - 0xFF */ 58*4882a593Smuzhiyun #define DA9211_REG_PAGE0 0 59*4882a593Smuzhiyun /* On I2C registers 0x100 - 0x1FF */ 60*4882a593Smuzhiyun #define DA9211_REG_PAGE2 2 61*4882a593Smuzhiyun #define DA9211_PAGE_WRITE_MODE 0x00 62*4882a593Smuzhiyun #define DA9211_REPEAT_WRITE_MODE 0x40 63*4882a593Smuzhiyun #define DA9211_PAGE_REVERT 0x80 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* DA9211_REG_STATUS_A (addr=0x50) */ 66*4882a593Smuzhiyun #define DA9211_GPI0 0x01 67*4882a593Smuzhiyun #define DA9211_GPI1 0x02 68*4882a593Smuzhiyun #define DA9211_GPI2 0x04 69*4882a593Smuzhiyun #define DA9211_GPI3 0x08 70*4882a593Smuzhiyun #define DA9211_GPI4 0x10 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* DA9211_REG_EVENT_A (addr=0x52) */ 73*4882a593Smuzhiyun #define DA9211_E_GPI0 0x01 74*4882a593Smuzhiyun #define DA9211_E_GPI1 0x02 75*4882a593Smuzhiyun #define DA9211_E_GPI2 0x04 76*4882a593Smuzhiyun #define DA9211_E_GPI3 0x08 77*4882a593Smuzhiyun #define DA9211_E_GPI4 0x10 78*4882a593Smuzhiyun #define DA9211_E_UVLO_IO 0x40 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* DA9211_REG_EVENT_B (addr=0x53) */ 81*4882a593Smuzhiyun #define DA9211_E_PWRGOOD_A 0x01 82*4882a593Smuzhiyun #define DA9211_E_PWRGOOD_B 0x02 83*4882a593Smuzhiyun #define DA9211_E_TEMP_WARN 0x04 84*4882a593Smuzhiyun #define DA9211_E_TEMP_CRIT 0x08 85*4882a593Smuzhiyun #define DA9211_E_OV_CURR_A 0x10 86*4882a593Smuzhiyun #define DA9211_E_OV_CURR_B 0x20 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* DA9211_REG_MASK_A (addr=0x54) */ 89*4882a593Smuzhiyun #define DA9211_M_GPI0 0x01 90*4882a593Smuzhiyun #define DA9211_M_GPI1 0x02 91*4882a593Smuzhiyun #define DA9211_M_GPI2 0x04 92*4882a593Smuzhiyun #define DA9211_M_GPI3 0x08 93*4882a593Smuzhiyun #define DA9211_M_GPI4 0x10 94*4882a593Smuzhiyun #define DA9211_M_UVLO_IO 0x40 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* DA9211_REG_MASK_B (addr=0x55) */ 97*4882a593Smuzhiyun #define DA9211_M_PWRGOOD_A 0x01 98*4882a593Smuzhiyun #define DA9211_M_PWRGOOD_B 0x02 99*4882a593Smuzhiyun #define DA9211_M_TEMP_WARN 0x04 100*4882a593Smuzhiyun #define DA9211_M_TEMP_CRIT 0x08 101*4882a593Smuzhiyun #define DA9211_M_OV_CURR_A 0x10 102*4882a593Smuzhiyun #define DA9211_M_OV_CURR_B 0x20 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* DA9211_REG_CONTROL_A (addr=0x56) */ 105*4882a593Smuzhiyun #define DA9211_DEBOUNCING_SHIFT 0 106*4882a593Smuzhiyun #define DA9211_DEBOUNCING_MASK 0x07 107*4882a593Smuzhiyun #define DA9211_SLEW_RATE_SHIFT 3 108*4882a593Smuzhiyun #define DA9211_SLEW_RATE_A_MASK 0x18 109*4882a593Smuzhiyun #define DA9211_SLEW_RATE_B_SHIFT 5 110*4882a593Smuzhiyun #define DA9211_SLEW_RATE_B_MASK 0x60 111*4882a593Smuzhiyun #define DA9211_V_LOCK 0x80 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* DA9211_REG_GPIO_0_1 (addr=0x58) */ 114*4882a593Smuzhiyun #define DA9211_GPIO0_PIN_SHIFT 0 115*4882a593Smuzhiyun #define DA9211_GPIO0_PIN_MASK 0x03 116*4882a593Smuzhiyun #define DA9211_GPIO0_PIN_GPI 0x00 117*4882a593Smuzhiyun #define DA9211_GPIO0_PIN_GPO_OD 0x02 118*4882a593Smuzhiyun #define DA9211_GPIO0_PIN_GPO 0x03 119*4882a593Smuzhiyun #define DA9211_GPIO0_TYPE 0x04 120*4882a593Smuzhiyun #define DA9211_GPIO0_TYPE_GPI 0x00 121*4882a593Smuzhiyun #define DA9211_GPIO0_TYPE_GPO 0x04 122*4882a593Smuzhiyun #define DA9211_GPIO0_MODE 0x08 123*4882a593Smuzhiyun #define DA9211_GPIO1_PIN_SHIFT 4 124*4882a593Smuzhiyun #define DA9211_GPIO1_PIN_MASK 0x30 125*4882a593Smuzhiyun #define DA9211_GPIO1_PIN_GPI 0x00 126*4882a593Smuzhiyun #define DA9211_GPIO1_PIN_VERROR 0x10 127*4882a593Smuzhiyun #define DA9211_GPIO1_PIN_GPO_OD 0x20 128*4882a593Smuzhiyun #define DA9211_GPIO1_PIN_GPO 0x30 129*4882a593Smuzhiyun #define DA9211_GPIO1_TYPE_SHIFT 0x40 130*4882a593Smuzhiyun #define DA9211_GPIO1_TYPE_GPI 0x00 131*4882a593Smuzhiyun #define DA9211_GPIO1_TYPE_GPO 0x40 132*4882a593Smuzhiyun #define DA9211_GPIO1_MODE 0x80 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* DA9211_REG_GPIO_2_3 (addr=0x59) */ 135*4882a593Smuzhiyun #define DA9211_GPIO2_PIN_SHIFT 0 136*4882a593Smuzhiyun #define DA9211_GPIO2_PIN_MASK 0x03 137*4882a593Smuzhiyun #define DA9211_GPIO2_PIN_GPI 0x00 138*4882a593Smuzhiyun #define DA9211_GPIO5_PIN_BUCK_CLK 0x10 139*4882a593Smuzhiyun #define DA9211_GPIO2_PIN_GPO_OD 0x02 140*4882a593Smuzhiyun #define DA9211_GPIO2_PIN_GPO 0x03 141*4882a593Smuzhiyun #define DA9211_GPIO2_TYPE 0x04 142*4882a593Smuzhiyun #define DA9211_GPIO2_TYPE_GPI 0x00 143*4882a593Smuzhiyun #define DA9211_GPIO2_TYPE_GPO 0x04 144*4882a593Smuzhiyun #define DA9211_GPIO2_MODE 0x08 145*4882a593Smuzhiyun #define DA9211_GPIO3_PIN_SHIFT 4 146*4882a593Smuzhiyun #define DA9211_GPIO3_PIN_MASK 0x30 147*4882a593Smuzhiyun #define DA9211_GPIO3_PIN_GPI 0x00 148*4882a593Smuzhiyun #define DA9211_GPIO3_PIN_IERROR 0x10 149*4882a593Smuzhiyun #define DA9211_GPIO3_PIN_GPO_OD 0x20 150*4882a593Smuzhiyun #define DA9211_GPIO3_PIN_GPO 0x30 151*4882a593Smuzhiyun #define DA9211_GPIO3_TYPE_SHIFT 0x40 152*4882a593Smuzhiyun #define DA9211_GPIO3_TYPE_GPI 0x00 153*4882a593Smuzhiyun #define DA9211_GPIO3_TYPE_GPO 0x40 154*4882a593Smuzhiyun #define DA9211_GPIO3_MODE 0x80 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* DA9211_REG_GPIO_4 (addr=0x5A) */ 157*4882a593Smuzhiyun #define DA9211_GPIO4_PIN_SHIFT 0 158*4882a593Smuzhiyun #define DA9211_GPIO4_PIN_MASK 0x03 159*4882a593Smuzhiyun #define DA9211_GPIO4_PIN_GPI 0x00 160*4882a593Smuzhiyun #define DA9211_GPIO4_PIN_GPO_OD 0x02 161*4882a593Smuzhiyun #define DA9211_GPIO4_PIN_GPO 0x03 162*4882a593Smuzhiyun #define DA9211_GPIO4_TYPE 0x04 163*4882a593Smuzhiyun #define DA9211_GPIO4_TYPE_GPI 0x00 164*4882a593Smuzhiyun #define DA9211_GPIO4_TYPE_GPO 0x04 165*4882a593Smuzhiyun #define DA9211_GPIO4_MODE 0x08 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* DA9211_REG_BUCKA_CONT (addr=0x5D) */ 168*4882a593Smuzhiyun #define DA9211_BUCKA_EN 0x01 169*4882a593Smuzhiyun #define DA9211_BUCKA_GPI_SHIFT 1 170*4882a593Smuzhiyun #define DA9211_BUCKA_GPI_MASK 0x06 171*4882a593Smuzhiyun #define DA9211_BUCKA_GPI_OFF 0x00 172*4882a593Smuzhiyun #define DA9211_BUCKA_GPI_GPIO0 0x02 173*4882a593Smuzhiyun #define DA9211_BUCKA_GPI_GPIO1 0x04 174*4882a593Smuzhiyun #define DA9211_BUCKA_GPI_GPIO3 0x06 175*4882a593Smuzhiyun #define DA9211_BUCKA_PD_DIS 0x08 176*4882a593Smuzhiyun #define DA9211_VBUCKA_SEL 0x10 177*4882a593Smuzhiyun #define DA9211_VBUCKA_SEL_A 0x00 178*4882a593Smuzhiyun #define DA9211_VBUCKA_SEL_B 0x10 179*4882a593Smuzhiyun #define DA9211_VBUCKA_GPI_SHIFT 5 180*4882a593Smuzhiyun #define DA9211_VBUCKA_GPI_MASK 0x60 181*4882a593Smuzhiyun #define DA9211_VBUCKA_GPI_OFF 0x00 182*4882a593Smuzhiyun #define DA9211_VBUCKA_GPI_GPIO1 0x20 183*4882a593Smuzhiyun #define DA9211_VBUCKA_GPI_GPIO2 0x40 184*4882a593Smuzhiyun #define DA9211_VBUCKA_GPI_GPIO4 0x60 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* DA9211_REG_BUCKB_CONT (addr=0x5E) */ 187*4882a593Smuzhiyun #define DA9211_BUCKB_EN 0x01 188*4882a593Smuzhiyun #define DA9211_BUCKB_GPI_SHIFT 1 189*4882a593Smuzhiyun #define DA9211_BUCKB_GPI_MASK 0x06 190*4882a593Smuzhiyun #define DA9211_BUCKB_GPI_OFF 0x00 191*4882a593Smuzhiyun #define DA9211_BUCKB_GPI_GPIO0 0x02 192*4882a593Smuzhiyun #define DA9211_BUCKB_GPI_GPIO1 0x04 193*4882a593Smuzhiyun #define DA9211_BUCKB_GPI_GPIO3 0x06 194*4882a593Smuzhiyun #define DA9211_BUCKB_PD_DIS 0x08 195*4882a593Smuzhiyun #define DA9211_VBUCKB_SEL 0x10 196*4882a593Smuzhiyun #define DA9211_VBUCKB_SEL_A 0x00 197*4882a593Smuzhiyun #define DA9211_VBUCKB_SEL_B 0x10 198*4882a593Smuzhiyun #define DA9211_VBUCKB_GPI_SHIFT 5 199*4882a593Smuzhiyun #define DA9211_VBUCKB_GPI_MASK 0x60 200*4882a593Smuzhiyun #define DA9211_VBUCKB_GPI_OFF 0x00 201*4882a593Smuzhiyun #define DA9211_VBUCKB_GPI_GPIO1 0x20 202*4882a593Smuzhiyun #define DA9211_VBUCKB_GPI_GPIO2 0x40 203*4882a593Smuzhiyun #define DA9211_VBUCKB_GPI_GPIO4 0x60 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* DA9211_REG_BUCK_ILIM (addr=0xD0) */ 206*4882a593Smuzhiyun #define DA9211_BUCKA_ILIM_SHIFT 0 207*4882a593Smuzhiyun #define DA9211_BUCKA_ILIM_MASK 0x0F 208*4882a593Smuzhiyun #define DA9211_BUCKB_ILIM_SHIFT 4 209*4882a593Smuzhiyun #define DA9211_BUCKB_ILIM_MASK 0xF0 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* DA9211_REG_BUCKA_CONF (addr=0xD1) */ 212*4882a593Smuzhiyun #define DA9211_BUCKA_MODE_SHIFT 0 213*4882a593Smuzhiyun #define DA9211_BUCKA_MODE_MASK 0x03 214*4882a593Smuzhiyun #define DA9211_BUCKA_MODE_MANUAL 0x00 215*4882a593Smuzhiyun #define DA9211_BUCKA_MODE_SLEEP 0x01 216*4882a593Smuzhiyun #define DA9211_BUCKA_MODE_SYNC 0x02 217*4882a593Smuzhiyun #define DA9211_BUCKA_MODE_AUTO 0x03 218*4882a593Smuzhiyun #define DA9211_BUCKA_UP_CTRL_SHIFT 2 219*4882a593Smuzhiyun #define DA9211_BUCKA_UP_CTRL_MASK 0x1C 220*4882a593Smuzhiyun #define DA9211_BUCKA_DOWN_CTRL_SHIFT 5 221*4882a593Smuzhiyun #define DA9211_BUCKA_DOWN_CTRL_MASK 0xE0 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* DA9211_REG_BUCKB_CONF (addr=0xD2) */ 224*4882a593Smuzhiyun #define DA9211_BUCKB_MODE_SHIFT 0 225*4882a593Smuzhiyun #define DA9211_BUCKB_MODE_MASK 0x03 226*4882a593Smuzhiyun #define DA9211_BUCKB_MODE_MANUAL 0x00 227*4882a593Smuzhiyun #define DA9211_BUCKB_MODE_SLEEP 0x01 228*4882a593Smuzhiyun #define DA9211_BUCKB_MODE_SYNC 0x02 229*4882a593Smuzhiyun #define DA9211_BUCKB_MODE_AUTO 0x03 230*4882a593Smuzhiyun #define DA9211_BUCKB_UP_CTRL_SHIFT 2 231*4882a593Smuzhiyun #define DA9211_BUCKB_UP_CTRL_MASK 0x1C 232*4882a593Smuzhiyun #define DA9211_BUCKB_DOWN_CTRL_SHIFT 5 233*4882a593Smuzhiyun #define DA9211_BUCKB_DOWN_CTRL_MASK 0xE0 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun /* DA9211_REG_BUCK_CONF (addr=0xD3) */ 236*4882a593Smuzhiyun #define DA9211_PHASE_SEL_A_SHIFT 0 237*4882a593Smuzhiyun #define DA9211_PHASE_SEL_A_MASK 0x03 238*4882a593Smuzhiyun #define DA9211_PHASE_SEL_B_SHIFT 2 239*4882a593Smuzhiyun #define DA9211_PHASE_SEL_B_MASK 0x04 240*4882a593Smuzhiyun #define DA9211_PH_SH_EN_A_SHIFT 3 241*4882a593Smuzhiyun #define DA9211_PH_SH_EN_A_MASK 0x08 242*4882a593Smuzhiyun #define DA9211_PH_SH_EN_B_SHIFT 4 243*4882a593Smuzhiyun #define DA9211_PH_SH_EN_B_MASK 0x10 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* DA9211_REG_VBUCKA_MAX (addr=0xD5) */ 246*4882a593Smuzhiyun #define DA9211_VBUCKA_BASE_SHIFT 0 247*4882a593Smuzhiyun #define DA9211_VBUCKA_BASE_MASK 0x7F 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* DA9211_REG_VBUCKB_MAX (addr=0xD6) */ 250*4882a593Smuzhiyun #define DA9211_VBUCKB_BASE_SHIFT 0 251*4882a593Smuzhiyun #define DA9211_VBUCKB_BASE_MASK 0x7F 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun /* DA9211_REG_VBUCKA/B_A/B (addr=0xD7/0xD8/0xD9/0xDA) */ 254*4882a593Smuzhiyun #define DA9211_VBUCK_SHIFT 0 255*4882a593Smuzhiyun #define DA9211_VBUCK_MASK 0x7F 256*4882a593Smuzhiyun #define DA9211_VBUCK_BIAS 0 257*4882a593Smuzhiyun #define DA9211_BUCK_SL 0x80 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* DA9211_REG_INTERFACE (addr=0x105) */ 260*4882a593Smuzhiyun #define DA9211_IF_BASE_ADDR_SHIFT 4 261*4882a593Smuzhiyun #define DA9211_IF_BASE_ADDR_MASK 0xF0 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* DA9211_REG_CONFIG_E (addr=0x147) */ 264*4882a593Smuzhiyun #define DA9211_SLAVE_SEL 0x40 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #endif /* __DA9211_REGISTERS_H__ */ 267