1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Regulator driver for DA9063 PMIC series
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright 2012 Dialog Semiconductors Ltd.
6*4882a593Smuzhiyun // Copyright 2013 Philipp Zabel, Pengutronix
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // Author: Krystian Garbaciak <krystian.garbaciak@diasemi.com>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/err.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/regulator/driver.h>
19*4882a593Smuzhiyun #include <linux/regulator/machine.h>
20*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
21*4882a593Smuzhiyun #include <linux/mfd/da9063/core.h>
22*4882a593Smuzhiyun #include <linux/mfd/da9063/registers.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Definition for registering regmap bit fields using a mask */
26*4882a593Smuzhiyun #define BFIELD(_reg, _mask) \
27*4882a593Smuzhiyun REG_FIELD(_reg, __builtin_ffs((int)_mask) - 1, \
28*4882a593Smuzhiyun sizeof(unsigned int) * 8 - __builtin_clz((_mask)) - 1)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* DA9063 and DA9063L regulator IDs */
31*4882a593Smuzhiyun enum {
32*4882a593Smuzhiyun /* BUCKs */
33*4882a593Smuzhiyun DA9063_ID_BCORE1,
34*4882a593Smuzhiyun DA9063_ID_BCORE2,
35*4882a593Smuzhiyun DA9063_ID_BPRO,
36*4882a593Smuzhiyun DA9063_ID_BMEM,
37*4882a593Smuzhiyun DA9063_ID_BIO,
38*4882a593Smuzhiyun DA9063_ID_BPERI,
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* BCORE1 and BCORE2 in merged mode */
41*4882a593Smuzhiyun DA9063_ID_BCORES_MERGED,
42*4882a593Smuzhiyun /* BMEM and BIO in merged mode */
43*4882a593Smuzhiyun DA9063_ID_BMEM_BIO_MERGED,
44*4882a593Smuzhiyun /* When two BUCKs are merged, they cannot be reused separately */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* LDOs on both DA9063 and DA9063L */
47*4882a593Smuzhiyun DA9063_ID_LDO3,
48*4882a593Smuzhiyun DA9063_ID_LDO7,
49*4882a593Smuzhiyun DA9063_ID_LDO8,
50*4882a593Smuzhiyun DA9063_ID_LDO9,
51*4882a593Smuzhiyun DA9063_ID_LDO11,
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* DA9063-only LDOs */
54*4882a593Smuzhiyun DA9063_ID_LDO1,
55*4882a593Smuzhiyun DA9063_ID_LDO2,
56*4882a593Smuzhiyun DA9063_ID_LDO4,
57*4882a593Smuzhiyun DA9063_ID_LDO5,
58*4882a593Smuzhiyun DA9063_ID_LDO6,
59*4882a593Smuzhiyun DA9063_ID_LDO10,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Old regulator platform data */
63*4882a593Smuzhiyun struct da9063_regulator_data {
64*4882a593Smuzhiyun int id;
65*4882a593Smuzhiyun struct regulator_init_data *initdata;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun struct da9063_regulators_pdata {
69*4882a593Smuzhiyun unsigned int n_regulators;
70*4882a593Smuzhiyun struct da9063_regulator_data *regulator_data;
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Regulator capabilities and registers description */
74*4882a593Smuzhiyun struct da9063_regulator_info {
75*4882a593Smuzhiyun struct regulator_desc desc;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* DA9063 main register fields */
78*4882a593Smuzhiyun struct reg_field mode; /* buck mode of operation */
79*4882a593Smuzhiyun struct reg_field suspend;
80*4882a593Smuzhiyun struct reg_field sleep;
81*4882a593Smuzhiyun struct reg_field suspend_sleep;
82*4882a593Smuzhiyun unsigned int suspend_vsel_reg;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* DA9063 event detection bit */
85*4882a593Smuzhiyun struct reg_field oc_event;
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Macros for LDO */
89*4882a593Smuzhiyun #define DA9063_LDO(chip, regl_name, min_mV, step_mV, max_mV) \
90*4882a593Smuzhiyun .desc.id = chip##_ID_##regl_name, \
91*4882a593Smuzhiyun .desc.name = __stringify(chip##_##regl_name), \
92*4882a593Smuzhiyun .desc.ops = &da9063_ldo_ops, \
93*4882a593Smuzhiyun .desc.min_uV = (min_mV) * 1000, \
94*4882a593Smuzhiyun .desc.uV_step = (step_mV) * 1000, \
95*4882a593Smuzhiyun .desc.n_voltages = (((max_mV) - (min_mV))/(step_mV) + 1 \
96*4882a593Smuzhiyun + (DA9063_V##regl_name##_BIAS)), \
97*4882a593Smuzhiyun .desc.enable_reg = DA9063_REG_##regl_name##_CONT, \
98*4882a593Smuzhiyun .desc.enable_mask = DA9063_LDO_EN, \
99*4882a593Smuzhiyun .desc.vsel_reg = DA9063_REG_V##regl_name##_A, \
100*4882a593Smuzhiyun .desc.vsel_mask = DA9063_V##regl_name##_MASK, \
101*4882a593Smuzhiyun .desc.linear_min_sel = DA9063_V##regl_name##_BIAS, \
102*4882a593Smuzhiyun .sleep = BFIELD(DA9063_REG_V##regl_name##_A, DA9063_LDO_SL), \
103*4882a593Smuzhiyun .suspend = BFIELD(DA9063_REG_##regl_name##_CONT, DA9063_LDO_CONF), \
104*4882a593Smuzhiyun .suspend_sleep = BFIELD(DA9063_REG_V##regl_name##_B, DA9063_LDO_SL), \
105*4882a593Smuzhiyun .suspend_vsel_reg = DA9063_REG_V##regl_name##_B
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Macros for voltage DC/DC converters (BUCKs) */
108*4882a593Smuzhiyun #define DA9063_BUCK(chip, regl_name, min_mV, step_mV, max_mV, limits_array, \
109*4882a593Smuzhiyun creg, cmask) \
110*4882a593Smuzhiyun .desc.id = chip##_ID_##regl_name, \
111*4882a593Smuzhiyun .desc.name = __stringify(chip##_##regl_name), \
112*4882a593Smuzhiyun .desc.ops = &da9063_buck_ops, \
113*4882a593Smuzhiyun .desc.min_uV = (min_mV) * 1000, \
114*4882a593Smuzhiyun .desc.uV_step = (step_mV) * 1000, \
115*4882a593Smuzhiyun .desc.n_voltages = ((max_mV) - (min_mV))/(step_mV) + 1, \
116*4882a593Smuzhiyun .desc.csel_reg = (creg), \
117*4882a593Smuzhiyun .desc.csel_mask = (cmask), \
118*4882a593Smuzhiyun .desc.curr_table = limits_array, \
119*4882a593Smuzhiyun .desc.n_current_limits = ARRAY_SIZE(limits_array)
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define DA9063_BUCK_COMMON_FIELDS(regl_name) \
122*4882a593Smuzhiyun .desc.enable_reg = DA9063_REG_##regl_name##_CONT, \
123*4882a593Smuzhiyun .desc.enable_mask = DA9063_BUCK_EN, \
124*4882a593Smuzhiyun .desc.vsel_reg = DA9063_REG_V##regl_name##_A, \
125*4882a593Smuzhiyun .desc.vsel_mask = DA9063_VBUCK_MASK, \
126*4882a593Smuzhiyun .desc.linear_min_sel = DA9063_VBUCK_BIAS, \
127*4882a593Smuzhiyun .sleep = BFIELD(DA9063_REG_V##regl_name##_A, DA9063_BUCK_SL), \
128*4882a593Smuzhiyun .suspend = BFIELD(DA9063_REG_##regl_name##_CONT, DA9063_BUCK_CONF), \
129*4882a593Smuzhiyun .suspend_sleep = BFIELD(DA9063_REG_V##regl_name##_B, DA9063_BUCK_SL), \
130*4882a593Smuzhiyun .suspend_vsel_reg = DA9063_REG_V##regl_name##_B, \
131*4882a593Smuzhiyun .mode = BFIELD(DA9063_REG_##regl_name##_CFG, DA9063_BUCK_MODE_MASK)
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* Defines asignment of regulators info table to chip model */
134*4882a593Smuzhiyun struct da9063_dev_model {
135*4882a593Smuzhiyun const struct da9063_regulator_info *regulator_info;
136*4882a593Smuzhiyun unsigned int n_regulators;
137*4882a593Smuzhiyun enum da9063_type type;
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Single regulator settings */
141*4882a593Smuzhiyun struct da9063_regulator {
142*4882a593Smuzhiyun struct regulator_desc desc;
143*4882a593Smuzhiyun struct regulator_dev *rdev;
144*4882a593Smuzhiyun struct da9063 *hw;
145*4882a593Smuzhiyun const struct da9063_regulator_info *info;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun struct regmap_field *mode;
148*4882a593Smuzhiyun struct regmap_field *suspend;
149*4882a593Smuzhiyun struct regmap_field *sleep;
150*4882a593Smuzhiyun struct regmap_field *suspend_sleep;
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* Encapsulates all information for the regulators driver */
154*4882a593Smuzhiyun struct da9063_regulators {
155*4882a593Smuzhiyun unsigned int n_regulators;
156*4882a593Smuzhiyun /* Array size to be defined during init. Keep at end. */
157*4882a593Smuzhiyun struct da9063_regulator regulator[];
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /* BUCK modes for DA9063 */
161*4882a593Smuzhiyun enum {
162*4882a593Smuzhiyun BUCK_MODE_MANUAL, /* 0 */
163*4882a593Smuzhiyun BUCK_MODE_SLEEP, /* 1 */
164*4882a593Smuzhiyun BUCK_MODE_SYNC, /* 2 */
165*4882a593Smuzhiyun BUCK_MODE_AUTO /* 3 */
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* Regulator operations */
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /*
171*4882a593Smuzhiyun * Current limits array (in uA) for BCORE1, BCORE2, BPRO.
172*4882a593Smuzhiyun * Entry indexes corresponds to register values.
173*4882a593Smuzhiyun */
174*4882a593Smuzhiyun static const unsigned int da9063_buck_a_limits[] = {
175*4882a593Smuzhiyun 500000, 600000, 700000, 800000, 900000, 1000000, 1100000, 1200000,
176*4882a593Smuzhiyun 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1900000, 2000000
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun * Current limits array (in uA) for BMEM, BIO, BPERI.
181*4882a593Smuzhiyun * Entry indexes corresponds to register values.
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun static const unsigned int da9063_buck_b_limits[] = {
184*4882a593Smuzhiyun 1500000, 1600000, 1700000, 1800000, 1900000, 2000000, 2100000, 2200000,
185*4882a593Smuzhiyun 2300000, 2400000, 2500000, 2600000, 2700000, 2800000, 2900000, 3000000
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /*
189*4882a593Smuzhiyun * Current limits array (in uA) for merged BCORE1 and BCORE2.
190*4882a593Smuzhiyun * Entry indexes corresponds to register values.
191*4882a593Smuzhiyun */
192*4882a593Smuzhiyun static const unsigned int da9063_bcores_merged_limits[] = {
193*4882a593Smuzhiyun 1000000, 1200000, 1400000, 1600000, 1800000, 2000000, 2200000, 2400000,
194*4882a593Smuzhiyun 2600000, 2800000, 3000000, 3200000, 3400000, 3600000, 3800000, 4000000
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun /*
198*4882a593Smuzhiyun * Current limits array (in uA) for merged BMEM and BIO.
199*4882a593Smuzhiyun * Entry indexes corresponds to register values.
200*4882a593Smuzhiyun */
201*4882a593Smuzhiyun static const unsigned int da9063_bmem_bio_merged_limits[] = {
202*4882a593Smuzhiyun 3000000, 3200000, 3400000, 3600000, 3800000, 4000000, 4200000, 4400000,
203*4882a593Smuzhiyun 4600000, 4800000, 5000000, 5200000, 5400000, 5600000, 5800000, 6000000
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun
da9063_buck_set_mode(struct regulator_dev * rdev,unsigned int mode)206*4882a593Smuzhiyun static int da9063_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
209*4882a593Smuzhiyun unsigned int val;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun switch (mode) {
212*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
213*4882a593Smuzhiyun val = BUCK_MODE_SYNC;
214*4882a593Smuzhiyun break;
215*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
216*4882a593Smuzhiyun val = BUCK_MODE_AUTO;
217*4882a593Smuzhiyun break;
218*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
219*4882a593Smuzhiyun val = BUCK_MODE_SLEEP;
220*4882a593Smuzhiyun break;
221*4882a593Smuzhiyun default:
222*4882a593Smuzhiyun return -EINVAL;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun return regmap_field_write(regl->mode, val);
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /*
229*4882a593Smuzhiyun * Bucks use single mode register field for normal operation
230*4882a593Smuzhiyun * and suspend state.
231*4882a593Smuzhiyun * There are 3 modes to map to: FAST, NORMAL, and STANDBY.
232*4882a593Smuzhiyun */
233*4882a593Smuzhiyun
da9063_buck_get_mode(struct regulator_dev * rdev)234*4882a593Smuzhiyun static unsigned int da9063_buck_get_mode(struct regulator_dev *rdev)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
237*4882a593Smuzhiyun unsigned int val;
238*4882a593Smuzhiyun int ret;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ret = regmap_field_read(regl->mode, &val);
241*4882a593Smuzhiyun if (ret < 0)
242*4882a593Smuzhiyun return ret;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun switch (val) {
245*4882a593Smuzhiyun default:
246*4882a593Smuzhiyun case BUCK_MODE_MANUAL:
247*4882a593Smuzhiyun /* Sleep flag bit decides the mode */
248*4882a593Smuzhiyun break;
249*4882a593Smuzhiyun case BUCK_MODE_SLEEP:
250*4882a593Smuzhiyun return REGULATOR_MODE_STANDBY;
251*4882a593Smuzhiyun case BUCK_MODE_SYNC:
252*4882a593Smuzhiyun return REGULATOR_MODE_FAST;
253*4882a593Smuzhiyun case BUCK_MODE_AUTO:
254*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun ret = regmap_field_read(regl->sleep, &val);
258*4882a593Smuzhiyun if (ret < 0)
259*4882a593Smuzhiyun return 0;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun if (val)
262*4882a593Smuzhiyun return REGULATOR_MODE_STANDBY;
263*4882a593Smuzhiyun else
264*4882a593Smuzhiyun return REGULATOR_MODE_FAST;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun /*
268*4882a593Smuzhiyun * LDOs use sleep flags - one for normal and one for suspend state.
269*4882a593Smuzhiyun * There are 2 modes to map to: NORMAL and STANDBY (sleep) for each state.
270*4882a593Smuzhiyun */
271*4882a593Smuzhiyun
da9063_ldo_set_mode(struct regulator_dev * rdev,unsigned int mode)272*4882a593Smuzhiyun static int da9063_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
275*4882a593Smuzhiyun unsigned int val;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun switch (mode) {
278*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
279*4882a593Smuzhiyun val = 0;
280*4882a593Smuzhiyun break;
281*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
282*4882a593Smuzhiyun val = 1;
283*4882a593Smuzhiyun break;
284*4882a593Smuzhiyun default:
285*4882a593Smuzhiyun return -EINVAL;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return regmap_field_write(regl->sleep, val);
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
da9063_ldo_get_mode(struct regulator_dev * rdev)291*4882a593Smuzhiyun static unsigned int da9063_ldo_get_mode(struct regulator_dev *rdev)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
294*4882a593Smuzhiyun int ret, val;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun ret = regmap_field_read(regl->sleep, &val);
297*4882a593Smuzhiyun if (ret < 0)
298*4882a593Smuzhiyun return 0;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (val)
301*4882a593Smuzhiyun return REGULATOR_MODE_STANDBY;
302*4882a593Smuzhiyun else
303*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
da9063_buck_get_status(struct regulator_dev * rdev)306*4882a593Smuzhiyun static int da9063_buck_get_status(struct regulator_dev *rdev)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun int ret = regulator_is_enabled_regmap(rdev);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun if (ret == 0) {
311*4882a593Smuzhiyun ret = REGULATOR_STATUS_OFF;
312*4882a593Smuzhiyun } else if (ret > 0) {
313*4882a593Smuzhiyun ret = da9063_buck_get_mode(rdev);
314*4882a593Smuzhiyun if (ret > 0)
315*4882a593Smuzhiyun ret = regulator_mode_to_status(ret);
316*4882a593Smuzhiyun else if (ret == 0)
317*4882a593Smuzhiyun ret = -EIO;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun return ret;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
da9063_ldo_get_status(struct regulator_dev * rdev)323*4882a593Smuzhiyun static int da9063_ldo_get_status(struct regulator_dev *rdev)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun int ret = regulator_is_enabled_regmap(rdev);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun if (ret == 0) {
328*4882a593Smuzhiyun ret = REGULATOR_STATUS_OFF;
329*4882a593Smuzhiyun } else if (ret > 0) {
330*4882a593Smuzhiyun ret = da9063_ldo_get_mode(rdev);
331*4882a593Smuzhiyun if (ret > 0)
332*4882a593Smuzhiyun ret = regulator_mode_to_status(ret);
333*4882a593Smuzhiyun else if (ret == 0)
334*4882a593Smuzhiyun ret = -EIO;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun return ret;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
da9063_set_suspend_voltage(struct regulator_dev * rdev,int uV)340*4882a593Smuzhiyun static int da9063_set_suspend_voltage(struct regulator_dev *rdev, int uV)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
343*4882a593Smuzhiyun const struct da9063_regulator_info *rinfo = regl->info;
344*4882a593Smuzhiyun int ret, sel;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun sel = regulator_map_voltage_linear(rdev, uV, uV);
347*4882a593Smuzhiyun if (sel < 0)
348*4882a593Smuzhiyun return sel;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun sel <<= ffs(rdev->desc->vsel_mask) - 1;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun ret = regmap_update_bits(regl->hw->regmap, rinfo->suspend_vsel_reg,
353*4882a593Smuzhiyun rdev->desc->vsel_mask, sel);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun return ret;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
da9063_suspend_enable(struct regulator_dev * rdev)358*4882a593Smuzhiyun static int da9063_suspend_enable(struct regulator_dev *rdev)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun return regmap_field_write(regl->suspend, 1);
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
da9063_suspend_disable(struct regulator_dev * rdev)365*4882a593Smuzhiyun static int da9063_suspend_disable(struct regulator_dev *rdev)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun return regmap_field_write(regl->suspend, 0);
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
da9063_buck_set_suspend_mode(struct regulator_dev * rdev,unsigned int mode)372*4882a593Smuzhiyun static int da9063_buck_set_suspend_mode(struct regulator_dev *rdev,
373*4882a593Smuzhiyun unsigned int mode)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
376*4882a593Smuzhiyun int val;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun switch (mode) {
379*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
380*4882a593Smuzhiyun val = BUCK_MODE_SYNC;
381*4882a593Smuzhiyun break;
382*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
383*4882a593Smuzhiyun val = BUCK_MODE_AUTO;
384*4882a593Smuzhiyun break;
385*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
386*4882a593Smuzhiyun val = BUCK_MODE_SLEEP;
387*4882a593Smuzhiyun break;
388*4882a593Smuzhiyun default:
389*4882a593Smuzhiyun return -EINVAL;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun return regmap_field_write(regl->mode, val);
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
da9063_ldo_set_suspend_mode(struct regulator_dev * rdev,unsigned int mode)395*4882a593Smuzhiyun static int da9063_ldo_set_suspend_mode(struct regulator_dev *rdev,
396*4882a593Smuzhiyun unsigned int mode)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun struct da9063_regulator *regl = rdev_get_drvdata(rdev);
399*4882a593Smuzhiyun unsigned int val;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun switch (mode) {
402*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
403*4882a593Smuzhiyun val = 0;
404*4882a593Smuzhiyun break;
405*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
406*4882a593Smuzhiyun val = 1;
407*4882a593Smuzhiyun break;
408*4882a593Smuzhiyun default:
409*4882a593Smuzhiyun return -EINVAL;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun return regmap_field_write(regl->suspend_sleep, val);
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun static const struct regulator_ops da9063_buck_ops = {
416*4882a593Smuzhiyun .enable = regulator_enable_regmap,
417*4882a593Smuzhiyun .disable = regulator_disable_regmap,
418*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
419*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
420*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
421*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
422*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
423*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
424*4882a593Smuzhiyun .set_mode = da9063_buck_set_mode,
425*4882a593Smuzhiyun .get_mode = da9063_buck_get_mode,
426*4882a593Smuzhiyun .get_status = da9063_buck_get_status,
427*4882a593Smuzhiyun .set_suspend_voltage = da9063_set_suspend_voltage,
428*4882a593Smuzhiyun .set_suspend_enable = da9063_suspend_enable,
429*4882a593Smuzhiyun .set_suspend_disable = da9063_suspend_disable,
430*4882a593Smuzhiyun .set_suspend_mode = da9063_buck_set_suspend_mode,
431*4882a593Smuzhiyun };
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun static const struct regulator_ops da9063_ldo_ops = {
434*4882a593Smuzhiyun .enable = regulator_enable_regmap,
435*4882a593Smuzhiyun .disable = regulator_disable_regmap,
436*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
437*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
438*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
439*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
440*4882a593Smuzhiyun .set_mode = da9063_ldo_set_mode,
441*4882a593Smuzhiyun .get_mode = da9063_ldo_get_mode,
442*4882a593Smuzhiyun .get_status = da9063_ldo_get_status,
443*4882a593Smuzhiyun .set_suspend_voltage = da9063_set_suspend_voltage,
444*4882a593Smuzhiyun .set_suspend_enable = da9063_suspend_enable,
445*4882a593Smuzhiyun .set_suspend_disable = da9063_suspend_disable,
446*4882a593Smuzhiyun .set_suspend_mode = da9063_ldo_set_suspend_mode,
447*4882a593Smuzhiyun };
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun /* Info of regulators for DA9063 */
450*4882a593Smuzhiyun static const struct da9063_regulator_info da9063_regulator_info[] = {
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun DA9063_BUCK(DA9063, BCORE1, 300, 10, 1570,
453*4882a593Smuzhiyun da9063_buck_a_limits,
454*4882a593Smuzhiyun DA9063_REG_BUCK_ILIM_C, DA9063_BCORE1_ILIM_MASK),
455*4882a593Smuzhiyun DA9063_BUCK_COMMON_FIELDS(BCORE1),
456*4882a593Smuzhiyun },
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun DA9063_BUCK(DA9063, BCORE2, 300, 10, 1570,
459*4882a593Smuzhiyun da9063_buck_a_limits,
460*4882a593Smuzhiyun DA9063_REG_BUCK_ILIM_C, DA9063_BCORE2_ILIM_MASK),
461*4882a593Smuzhiyun DA9063_BUCK_COMMON_FIELDS(BCORE2),
462*4882a593Smuzhiyun },
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun DA9063_BUCK(DA9063, BPRO, 530, 10, 1800,
465*4882a593Smuzhiyun da9063_buck_a_limits,
466*4882a593Smuzhiyun DA9063_REG_BUCK_ILIM_B, DA9063_BPRO_ILIM_MASK),
467*4882a593Smuzhiyun DA9063_BUCK_COMMON_FIELDS(BPRO),
468*4882a593Smuzhiyun },
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun DA9063_BUCK(DA9063, BMEM, 800, 20, 3340,
471*4882a593Smuzhiyun da9063_buck_b_limits,
472*4882a593Smuzhiyun DA9063_REG_BUCK_ILIM_A, DA9063_BMEM_ILIM_MASK),
473*4882a593Smuzhiyun DA9063_BUCK_COMMON_FIELDS(BMEM),
474*4882a593Smuzhiyun },
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun DA9063_BUCK(DA9063, BIO, 800, 20, 3340,
477*4882a593Smuzhiyun da9063_buck_b_limits,
478*4882a593Smuzhiyun DA9063_REG_BUCK_ILIM_A, DA9063_BIO_ILIM_MASK),
479*4882a593Smuzhiyun DA9063_BUCK_COMMON_FIELDS(BIO),
480*4882a593Smuzhiyun },
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun DA9063_BUCK(DA9063, BPERI, 800, 20, 3340,
483*4882a593Smuzhiyun da9063_buck_b_limits,
484*4882a593Smuzhiyun DA9063_REG_BUCK_ILIM_B, DA9063_BPERI_ILIM_MASK),
485*4882a593Smuzhiyun DA9063_BUCK_COMMON_FIELDS(BPERI),
486*4882a593Smuzhiyun },
487*4882a593Smuzhiyun {
488*4882a593Smuzhiyun DA9063_BUCK(DA9063, BCORES_MERGED, 300, 10, 1570,
489*4882a593Smuzhiyun da9063_bcores_merged_limits,
490*4882a593Smuzhiyun DA9063_REG_BUCK_ILIM_C, DA9063_BCORE1_ILIM_MASK),
491*4882a593Smuzhiyun /* BCORES_MERGED uses the same register fields as BCORE1 */
492*4882a593Smuzhiyun DA9063_BUCK_COMMON_FIELDS(BCORE1),
493*4882a593Smuzhiyun },
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun DA9063_BUCK(DA9063, BMEM_BIO_MERGED, 800, 20, 3340,
496*4882a593Smuzhiyun da9063_bmem_bio_merged_limits,
497*4882a593Smuzhiyun DA9063_REG_BUCK_ILIM_A, DA9063_BMEM_ILIM_MASK),
498*4882a593Smuzhiyun /* BMEM_BIO_MERGED uses the same register fields as BMEM */
499*4882a593Smuzhiyun DA9063_BUCK_COMMON_FIELDS(BMEM),
500*4882a593Smuzhiyun },
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO3, 900, 20, 3440),
503*4882a593Smuzhiyun .oc_event = BFIELD(DA9063_REG_STATUS_D, DA9063_LDO3_LIM),
504*4882a593Smuzhiyun },
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO7, 900, 50, 3600),
507*4882a593Smuzhiyun .oc_event = BFIELD(DA9063_REG_STATUS_D, DA9063_LDO7_LIM),
508*4882a593Smuzhiyun },
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO8, 900, 50, 3600),
511*4882a593Smuzhiyun .oc_event = BFIELD(DA9063_REG_STATUS_D, DA9063_LDO8_LIM),
512*4882a593Smuzhiyun },
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO9, 950, 50, 3600),
515*4882a593Smuzhiyun },
516*4882a593Smuzhiyun {
517*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO11, 900, 50, 3600),
518*4882a593Smuzhiyun .oc_event = BFIELD(DA9063_REG_STATUS_D, DA9063_LDO11_LIM),
519*4882a593Smuzhiyun },
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun /* The following LDOs are present only on DA9063, not on DA9063L */
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO1, 600, 20, 1860),
524*4882a593Smuzhiyun },
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO2, 600, 20, 1860),
527*4882a593Smuzhiyun },
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO4, 900, 20, 3440),
530*4882a593Smuzhiyun .oc_event = BFIELD(DA9063_REG_STATUS_D, DA9063_LDO4_LIM),
531*4882a593Smuzhiyun },
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO5, 900, 50, 3600),
534*4882a593Smuzhiyun },
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO6, 900, 50, 3600),
537*4882a593Smuzhiyun },
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun DA9063_LDO(DA9063, LDO10, 900, 50, 3600),
541*4882a593Smuzhiyun },
542*4882a593Smuzhiyun };
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun /* Link chip model with regulators info table */
545*4882a593Smuzhiyun static struct da9063_dev_model regulators_models[] = {
546*4882a593Smuzhiyun {
547*4882a593Smuzhiyun .regulator_info = da9063_regulator_info,
548*4882a593Smuzhiyun .n_regulators = ARRAY_SIZE(da9063_regulator_info),
549*4882a593Smuzhiyun .type = PMIC_TYPE_DA9063,
550*4882a593Smuzhiyun },
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun .regulator_info = da9063_regulator_info,
553*4882a593Smuzhiyun .n_regulators = ARRAY_SIZE(da9063_regulator_info) - 6,
554*4882a593Smuzhiyun .type = PMIC_TYPE_DA9063L,
555*4882a593Smuzhiyun },
556*4882a593Smuzhiyun { }
557*4882a593Smuzhiyun };
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun /* Regulator interrupt handlers */
da9063_ldo_lim_event(int irq,void * data)560*4882a593Smuzhiyun static irqreturn_t da9063_ldo_lim_event(int irq, void *data)
561*4882a593Smuzhiyun {
562*4882a593Smuzhiyun struct da9063_regulators *regulators = data;
563*4882a593Smuzhiyun struct da9063 *hw = regulators->regulator[0].hw;
564*4882a593Smuzhiyun struct da9063_regulator *regl;
565*4882a593Smuzhiyun int bits, i, ret;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun ret = regmap_read(hw->regmap, DA9063_REG_STATUS_D, &bits);
568*4882a593Smuzhiyun if (ret < 0)
569*4882a593Smuzhiyun return IRQ_NONE;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun for (i = regulators->n_regulators - 1; i >= 0; i--) {
572*4882a593Smuzhiyun regl = ®ulators->regulator[i];
573*4882a593Smuzhiyun if (regl->info->oc_event.reg != DA9063_REG_STATUS_D)
574*4882a593Smuzhiyun continue;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun if (BIT(regl->info->oc_event.lsb) & bits) {
577*4882a593Smuzhiyun regulator_notifier_call_chain(regl->rdev,
578*4882a593Smuzhiyun REGULATOR_EVENT_OVER_CURRENT, NULL);
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun return IRQ_HANDLED;
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun /*
586*4882a593Smuzhiyun * Probing and Initialisation functions
587*4882a593Smuzhiyun */
da9063_get_regulator_initdata(const struct da9063_regulators_pdata * regl_pdata,int id)588*4882a593Smuzhiyun static const struct regulator_init_data *da9063_get_regulator_initdata(
589*4882a593Smuzhiyun const struct da9063_regulators_pdata *regl_pdata, int id)
590*4882a593Smuzhiyun {
591*4882a593Smuzhiyun int i;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun for (i = 0; i < regl_pdata->n_regulators; i++) {
594*4882a593Smuzhiyun if (id == regl_pdata->regulator_data[i].id)
595*4882a593Smuzhiyun return regl_pdata->regulator_data[i].initdata;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun return NULL;
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun static struct of_regulator_match da9063_matches[] = {
602*4882a593Smuzhiyun [DA9063_ID_BCORE1] = { .name = "bcore1" },
603*4882a593Smuzhiyun [DA9063_ID_BCORE2] = { .name = "bcore2" },
604*4882a593Smuzhiyun [DA9063_ID_BPRO] = { .name = "bpro", },
605*4882a593Smuzhiyun [DA9063_ID_BMEM] = { .name = "bmem", },
606*4882a593Smuzhiyun [DA9063_ID_BIO] = { .name = "bio", },
607*4882a593Smuzhiyun [DA9063_ID_BPERI] = { .name = "bperi", },
608*4882a593Smuzhiyun [DA9063_ID_BCORES_MERGED] = { .name = "bcores-merged" },
609*4882a593Smuzhiyun [DA9063_ID_BMEM_BIO_MERGED] = { .name = "bmem-bio-merged", },
610*4882a593Smuzhiyun [DA9063_ID_LDO3] = { .name = "ldo3", },
611*4882a593Smuzhiyun [DA9063_ID_LDO7] = { .name = "ldo7", },
612*4882a593Smuzhiyun [DA9063_ID_LDO8] = { .name = "ldo8", },
613*4882a593Smuzhiyun [DA9063_ID_LDO9] = { .name = "ldo9", },
614*4882a593Smuzhiyun [DA9063_ID_LDO11] = { .name = "ldo11", },
615*4882a593Smuzhiyun /* The following LDOs are present only on DA9063, not on DA9063L */
616*4882a593Smuzhiyun [DA9063_ID_LDO1] = { .name = "ldo1", },
617*4882a593Smuzhiyun [DA9063_ID_LDO2] = { .name = "ldo2", },
618*4882a593Smuzhiyun [DA9063_ID_LDO4] = { .name = "ldo4", },
619*4882a593Smuzhiyun [DA9063_ID_LDO5] = { .name = "ldo5", },
620*4882a593Smuzhiyun [DA9063_ID_LDO6] = { .name = "ldo6", },
621*4882a593Smuzhiyun [DA9063_ID_LDO10] = { .name = "ldo10", },
622*4882a593Smuzhiyun };
623*4882a593Smuzhiyun
da9063_parse_regulators_dt(struct platform_device * pdev,struct of_regulator_match ** da9063_reg_matches)624*4882a593Smuzhiyun static struct da9063_regulators_pdata *da9063_parse_regulators_dt(
625*4882a593Smuzhiyun struct platform_device *pdev,
626*4882a593Smuzhiyun struct of_regulator_match **da9063_reg_matches)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun struct da9063 *da9063 = dev_get_drvdata(pdev->dev.parent);
629*4882a593Smuzhiyun struct da9063_regulators_pdata *pdata;
630*4882a593Smuzhiyun struct da9063_regulator_data *rdata;
631*4882a593Smuzhiyun struct device_node *node;
632*4882a593Smuzhiyun int da9063_matches_len = ARRAY_SIZE(da9063_matches);
633*4882a593Smuzhiyun int i, n, num;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun if (da9063->type == PMIC_TYPE_DA9063L)
636*4882a593Smuzhiyun da9063_matches_len -= 6;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun node = of_get_child_by_name(pdev->dev.parent->of_node, "regulators");
639*4882a593Smuzhiyun if (!node) {
640*4882a593Smuzhiyun dev_err(&pdev->dev, "Regulators device node not found\n");
641*4882a593Smuzhiyun return ERR_PTR(-ENODEV);
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun num = of_regulator_match(&pdev->dev, node, da9063_matches,
645*4882a593Smuzhiyun da9063_matches_len);
646*4882a593Smuzhiyun of_node_put(node);
647*4882a593Smuzhiyun if (num < 0) {
648*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to match regulators\n");
649*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
653*4882a593Smuzhiyun if (!pdata)
654*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun pdata->regulator_data = devm_kcalloc(&pdev->dev,
657*4882a593Smuzhiyun num, sizeof(*pdata->regulator_data),
658*4882a593Smuzhiyun GFP_KERNEL);
659*4882a593Smuzhiyun if (!pdata->regulator_data)
660*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
661*4882a593Smuzhiyun pdata->n_regulators = num;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun n = 0;
664*4882a593Smuzhiyun for (i = 0; i < da9063_matches_len; i++) {
665*4882a593Smuzhiyun if (!da9063_matches[i].init_data)
666*4882a593Smuzhiyun continue;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun rdata = &pdata->regulator_data[n];
669*4882a593Smuzhiyun rdata->id = i;
670*4882a593Smuzhiyun rdata->initdata = da9063_matches[i].init_data;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun n++;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun *da9063_reg_matches = da9063_matches;
676*4882a593Smuzhiyun return pdata;
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
da9063_regulator_probe(struct platform_device * pdev)679*4882a593Smuzhiyun static int da9063_regulator_probe(struct platform_device *pdev)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun struct da9063 *da9063 = dev_get_drvdata(pdev->dev.parent);
682*4882a593Smuzhiyun struct of_regulator_match *da9063_reg_matches = NULL;
683*4882a593Smuzhiyun struct da9063_regulators_pdata *regl_pdata;
684*4882a593Smuzhiyun const struct da9063_dev_model *model;
685*4882a593Smuzhiyun struct da9063_regulators *regulators;
686*4882a593Smuzhiyun struct da9063_regulator *regl;
687*4882a593Smuzhiyun struct regulator_config config;
688*4882a593Smuzhiyun bool bcores_merged, bmem_bio_merged;
689*4882a593Smuzhiyun int id, irq, n, n_regulators, ret, val;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun regl_pdata = da9063_parse_regulators_dt(pdev, &da9063_reg_matches);
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun if (IS_ERR(regl_pdata) || regl_pdata->n_regulators == 0) {
694*4882a593Smuzhiyun dev_err(&pdev->dev,
695*4882a593Smuzhiyun "No regulators defined for the platform\n");
696*4882a593Smuzhiyun return -ENODEV;
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun /* Find regulators set for particular device model */
700*4882a593Smuzhiyun for (model = regulators_models; model->regulator_info; model++) {
701*4882a593Smuzhiyun if (model->type == da9063->type)
702*4882a593Smuzhiyun break;
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun if (!model->regulator_info) {
705*4882a593Smuzhiyun dev_err(&pdev->dev, "Chip model not recognised (%u)\n",
706*4882a593Smuzhiyun da9063->type);
707*4882a593Smuzhiyun return -ENODEV;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun ret = regmap_read(da9063->regmap, DA9063_REG_CONFIG_H, &val);
711*4882a593Smuzhiyun if (ret < 0) {
712*4882a593Smuzhiyun dev_err(&pdev->dev,
713*4882a593Smuzhiyun "Error while reading BUCKs configuration\n");
714*4882a593Smuzhiyun return ret;
715*4882a593Smuzhiyun }
716*4882a593Smuzhiyun bcores_merged = val & DA9063_BCORE_MERGE;
717*4882a593Smuzhiyun bmem_bio_merged = val & DA9063_BUCK_MERGE;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun n_regulators = model->n_regulators;
720*4882a593Smuzhiyun if (bcores_merged)
721*4882a593Smuzhiyun n_regulators -= 2; /* remove BCORE1, BCORE2 */
722*4882a593Smuzhiyun else
723*4882a593Smuzhiyun n_regulators--; /* remove BCORES_MERGED */
724*4882a593Smuzhiyun if (bmem_bio_merged)
725*4882a593Smuzhiyun n_regulators -= 2; /* remove BMEM, BIO */
726*4882a593Smuzhiyun else
727*4882a593Smuzhiyun n_regulators--; /* remove BMEM_BIO_MERGED */
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun /* Allocate memory required by usable regulators */
730*4882a593Smuzhiyun regulators = devm_kzalloc(&pdev->dev, struct_size(regulators,
731*4882a593Smuzhiyun regulator, n_regulators), GFP_KERNEL);
732*4882a593Smuzhiyun if (!regulators)
733*4882a593Smuzhiyun return -ENOMEM;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun regulators->n_regulators = n_regulators;
736*4882a593Smuzhiyun platform_set_drvdata(pdev, regulators);
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun /* Register all regulators declared in platform information */
739*4882a593Smuzhiyun n = 0;
740*4882a593Smuzhiyun id = 0;
741*4882a593Smuzhiyun while (n < regulators->n_regulators) {
742*4882a593Smuzhiyun /* Skip regulator IDs depending on merge mode configuration */
743*4882a593Smuzhiyun switch (id) {
744*4882a593Smuzhiyun case DA9063_ID_BCORE1:
745*4882a593Smuzhiyun case DA9063_ID_BCORE2:
746*4882a593Smuzhiyun if (bcores_merged) {
747*4882a593Smuzhiyun id++;
748*4882a593Smuzhiyun continue;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun break;
751*4882a593Smuzhiyun case DA9063_ID_BMEM:
752*4882a593Smuzhiyun case DA9063_ID_BIO:
753*4882a593Smuzhiyun if (bmem_bio_merged) {
754*4882a593Smuzhiyun id++;
755*4882a593Smuzhiyun continue;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun break;
758*4882a593Smuzhiyun case DA9063_ID_BCORES_MERGED:
759*4882a593Smuzhiyun if (!bcores_merged) {
760*4882a593Smuzhiyun id++;
761*4882a593Smuzhiyun continue;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun break;
764*4882a593Smuzhiyun case DA9063_ID_BMEM_BIO_MERGED:
765*4882a593Smuzhiyun if (!bmem_bio_merged) {
766*4882a593Smuzhiyun id++;
767*4882a593Smuzhiyun continue;
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun break;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun /* Initialise regulator structure */
773*4882a593Smuzhiyun regl = ®ulators->regulator[n];
774*4882a593Smuzhiyun regl->hw = da9063;
775*4882a593Smuzhiyun regl->info = &model->regulator_info[id];
776*4882a593Smuzhiyun regl->desc = regl->info->desc;
777*4882a593Smuzhiyun regl->desc.type = REGULATOR_VOLTAGE;
778*4882a593Smuzhiyun regl->desc.owner = THIS_MODULE;
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun if (regl->info->mode.reg) {
781*4882a593Smuzhiyun regl->mode = devm_regmap_field_alloc(&pdev->dev,
782*4882a593Smuzhiyun da9063->regmap, regl->info->mode);
783*4882a593Smuzhiyun if (IS_ERR(regl->mode))
784*4882a593Smuzhiyun return PTR_ERR(regl->mode);
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun if (regl->info->suspend.reg) {
788*4882a593Smuzhiyun regl->suspend = devm_regmap_field_alloc(&pdev->dev,
789*4882a593Smuzhiyun da9063->regmap, regl->info->suspend);
790*4882a593Smuzhiyun if (IS_ERR(regl->suspend))
791*4882a593Smuzhiyun return PTR_ERR(regl->suspend);
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun if (regl->info->sleep.reg) {
795*4882a593Smuzhiyun regl->sleep = devm_regmap_field_alloc(&pdev->dev,
796*4882a593Smuzhiyun da9063->regmap, regl->info->sleep);
797*4882a593Smuzhiyun if (IS_ERR(regl->sleep))
798*4882a593Smuzhiyun return PTR_ERR(regl->sleep);
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun if (regl->info->suspend_sleep.reg) {
802*4882a593Smuzhiyun regl->suspend_sleep = devm_regmap_field_alloc(&pdev->dev,
803*4882a593Smuzhiyun da9063->regmap, regl->info->suspend_sleep);
804*4882a593Smuzhiyun if (IS_ERR(regl->suspend_sleep))
805*4882a593Smuzhiyun return PTR_ERR(regl->suspend_sleep);
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun /* Register regulator */
809*4882a593Smuzhiyun memset(&config, 0, sizeof(config));
810*4882a593Smuzhiyun config.dev = &pdev->dev;
811*4882a593Smuzhiyun config.init_data = da9063_get_regulator_initdata(regl_pdata, id);
812*4882a593Smuzhiyun config.driver_data = regl;
813*4882a593Smuzhiyun if (da9063_reg_matches)
814*4882a593Smuzhiyun config.of_node = da9063_reg_matches[id].of_node;
815*4882a593Smuzhiyun config.regmap = da9063->regmap;
816*4882a593Smuzhiyun regl->rdev = devm_regulator_register(&pdev->dev, ®l->desc,
817*4882a593Smuzhiyun &config);
818*4882a593Smuzhiyun if (IS_ERR(regl->rdev)) {
819*4882a593Smuzhiyun dev_err(&pdev->dev,
820*4882a593Smuzhiyun "Failed to register %s regulator\n",
821*4882a593Smuzhiyun regl->desc.name);
822*4882a593Smuzhiyun return PTR_ERR(regl->rdev);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun id++;
825*4882a593Smuzhiyun n++;
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun /* LDOs overcurrent event support */
829*4882a593Smuzhiyun irq = platform_get_irq_byname(pdev, "LDO_LIM");
830*4882a593Smuzhiyun if (irq < 0)
831*4882a593Smuzhiyun return irq;
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, irq,
834*4882a593Smuzhiyun NULL, da9063_ldo_lim_event,
835*4882a593Smuzhiyun IRQF_TRIGGER_LOW | IRQF_ONESHOT,
836*4882a593Smuzhiyun "LDO_LIM", regulators);
837*4882a593Smuzhiyun if (ret)
838*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request LDO_LIM IRQ.\n");
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun return ret;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun static struct platform_driver da9063_regulator_driver = {
844*4882a593Smuzhiyun .driver = {
845*4882a593Smuzhiyun .name = DA9063_DRVNAME_REGULATORS,
846*4882a593Smuzhiyun },
847*4882a593Smuzhiyun .probe = da9063_regulator_probe,
848*4882a593Smuzhiyun };
849*4882a593Smuzhiyun
da9063_regulator_init(void)850*4882a593Smuzhiyun static int __init da9063_regulator_init(void)
851*4882a593Smuzhiyun {
852*4882a593Smuzhiyun return platform_driver_register(&da9063_regulator_driver);
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun subsys_initcall(da9063_regulator_init);
855*4882a593Smuzhiyun
da9063_regulator_cleanup(void)856*4882a593Smuzhiyun static void __exit da9063_regulator_cleanup(void)
857*4882a593Smuzhiyun {
858*4882a593Smuzhiyun platform_driver_unregister(&da9063_regulator_driver);
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun module_exit(da9063_regulator_cleanup);
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun /* Module information */
864*4882a593Smuzhiyun MODULE_AUTHOR("Krystian Garbaciak <krystian.garbaciak@diasemi.com>");
865*4882a593Smuzhiyun MODULE_DESCRIPTION("DA9063 regulators driver");
866*4882a593Smuzhiyun MODULE_LICENSE("GPL");
867*4882a593Smuzhiyun MODULE_ALIAS("platform:" DA9063_DRVNAME_REGULATORS);
868