xref: /OK3568_Linux_fs/kernel/drivers/regulator/da9052-regulator.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // da9052-regulator.c: Regulator driver for DA9052
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright(c) 2011 Dialog Semiconductor Ltd.
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // Author: David Dajun Chen <dchen@diasemi.com>
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/regulator/driver.h>
15*4882a593Smuzhiyun #include <linux/regulator/machine.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/mfd/da9052/da9052.h>
20*4882a593Smuzhiyun #include <linux/mfd/da9052/reg.h>
21*4882a593Smuzhiyun #include <linux/mfd/da9052/pdata.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /* Buck step size */
24*4882a593Smuzhiyun #define DA9052_BUCK_PERI_3uV_STEP		100000
25*4882a593Smuzhiyun #define DA9052_BUCK_PERI_REG_MAP_UPTO_3uV	24
26*4882a593Smuzhiyun #define DA9052_CONST_3uV			3000000
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define DA9052_MIN_UA		0
29*4882a593Smuzhiyun #define DA9052_MAX_UA		3
30*4882a593Smuzhiyun #define DA9052_CURRENT_RANGE	4
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* Bit masks */
33*4882a593Smuzhiyun #define DA9052_BUCK_ILIM_MASK_EVEN	0x0c
34*4882a593Smuzhiyun #define DA9052_BUCK_ILIM_MASK_ODD	0xc0
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* DA9052 REGULATOR IDs */
37*4882a593Smuzhiyun #define DA9052_ID_BUCK1		0
38*4882a593Smuzhiyun #define DA9052_ID_BUCK2		1
39*4882a593Smuzhiyun #define DA9052_ID_BUCK3		2
40*4882a593Smuzhiyun #define DA9052_ID_BUCK4		3
41*4882a593Smuzhiyun #define DA9052_ID_LDO1		4
42*4882a593Smuzhiyun #define DA9052_ID_LDO2		5
43*4882a593Smuzhiyun #define DA9052_ID_LDO3		6
44*4882a593Smuzhiyun #define DA9052_ID_LDO4		7
45*4882a593Smuzhiyun #define DA9052_ID_LDO5		8
46*4882a593Smuzhiyun #define DA9052_ID_LDO6		9
47*4882a593Smuzhiyun #define DA9052_ID_LDO7		10
48*4882a593Smuzhiyun #define DA9052_ID_LDO8		11
49*4882a593Smuzhiyun #define DA9052_ID_LDO9		12
50*4882a593Smuzhiyun #define DA9052_ID_LDO10		13
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun static const u32 da9052_current_limits[3][4] = {
53*4882a593Smuzhiyun 	{700000, 800000, 1000000, 1200000},	/* DA9052-BC BUCKs */
54*4882a593Smuzhiyun 	{1600000, 2000000, 2400000, 3000000},	/* DA9053-AA/Bx BUCK-CORE */
55*4882a593Smuzhiyun 	{800000, 1000000, 1200000, 1500000},	/* DA9053-AA/Bx BUCK-PRO,
56*4882a593Smuzhiyun 						 * BUCK-MEM and BUCK-PERI
57*4882a593Smuzhiyun 						*/
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun struct da9052_regulator_info {
61*4882a593Smuzhiyun 	struct regulator_desc reg_desc;
62*4882a593Smuzhiyun 	int step_uV;
63*4882a593Smuzhiyun 	int min_uV;
64*4882a593Smuzhiyun 	int max_uV;
65*4882a593Smuzhiyun 	unsigned char activate_bit;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun struct da9052_regulator {
69*4882a593Smuzhiyun 	struct da9052 *da9052;
70*4882a593Smuzhiyun 	struct da9052_regulator_info *info;
71*4882a593Smuzhiyun 	struct regulator_dev *rdev;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
verify_range(struct da9052_regulator_info * info,int min_uV,int max_uV)74*4882a593Smuzhiyun static int verify_range(struct da9052_regulator_info *info,
75*4882a593Smuzhiyun 			 int min_uV, int max_uV)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	if (min_uV > info->max_uV || max_uV < info->min_uV)
78*4882a593Smuzhiyun 		return -EINVAL;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
da9052_dcdc_get_current_limit(struct regulator_dev * rdev)83*4882a593Smuzhiyun static int da9052_dcdc_get_current_limit(struct regulator_dev *rdev)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
86*4882a593Smuzhiyun 	int offset = rdev_get_id(rdev);
87*4882a593Smuzhiyun 	int ret, row = 2;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	ret = da9052_reg_read(regulator->da9052, DA9052_BUCKA_REG + offset/2);
90*4882a593Smuzhiyun 	if (ret < 0)
91*4882a593Smuzhiyun 		return ret;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	/* Determine the even or odd position of the buck current limit
94*4882a593Smuzhiyun 	 * register field
95*4882a593Smuzhiyun 	*/
96*4882a593Smuzhiyun 	if (offset % 2 == 0)
97*4882a593Smuzhiyun 		ret = (ret & DA9052_BUCK_ILIM_MASK_EVEN) >> 2;
98*4882a593Smuzhiyun 	else
99*4882a593Smuzhiyun 		ret = (ret & DA9052_BUCK_ILIM_MASK_ODD) >> 6;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	/* Select the appropriate current limit range */
102*4882a593Smuzhiyun 	if (regulator->da9052->chip_id == DA9052)
103*4882a593Smuzhiyun 		row = 0;
104*4882a593Smuzhiyun 	else if (offset == 0)
105*4882a593Smuzhiyun 		row = 1;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	return da9052_current_limits[row][ret];
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
da9052_dcdc_set_current_limit(struct regulator_dev * rdev,int min_uA,int max_uA)110*4882a593Smuzhiyun static int da9052_dcdc_set_current_limit(struct regulator_dev *rdev, int min_uA,
111*4882a593Smuzhiyun 					  int max_uA)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
114*4882a593Smuzhiyun 	int offset = rdev_get_id(rdev);
115*4882a593Smuzhiyun 	int reg_val = 0;
116*4882a593Smuzhiyun 	int i, row = 2;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* Select the appropriate current limit range */
119*4882a593Smuzhiyun 	if (regulator->da9052->chip_id == DA9052)
120*4882a593Smuzhiyun 		row = 0;
121*4882a593Smuzhiyun 	else if (offset == 0)
122*4882a593Smuzhiyun 		row = 1;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	for (i = DA9052_CURRENT_RANGE - 1; i >= 0; i--) {
125*4882a593Smuzhiyun 		if ((min_uA <= da9052_current_limits[row][i]) &&
126*4882a593Smuzhiyun 		    (da9052_current_limits[row][i] <= max_uA)) {
127*4882a593Smuzhiyun 			reg_val = i;
128*4882a593Smuzhiyun 			break;
129*4882a593Smuzhiyun 		}
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	if (i < 0)
133*4882a593Smuzhiyun 		return -EINVAL;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* Determine the even or odd position of the buck current limit
136*4882a593Smuzhiyun 	 * register field
137*4882a593Smuzhiyun 	*/
138*4882a593Smuzhiyun 	if (offset % 2 == 0)
139*4882a593Smuzhiyun 		return da9052_reg_update(regulator->da9052,
140*4882a593Smuzhiyun 					 DA9052_BUCKA_REG + offset/2,
141*4882a593Smuzhiyun 					 DA9052_BUCK_ILIM_MASK_EVEN,
142*4882a593Smuzhiyun 					 reg_val << 2);
143*4882a593Smuzhiyun 	else
144*4882a593Smuzhiyun 		return da9052_reg_update(regulator->da9052,
145*4882a593Smuzhiyun 					 DA9052_BUCKA_REG + offset/2,
146*4882a593Smuzhiyun 					 DA9052_BUCK_ILIM_MASK_ODD,
147*4882a593Smuzhiyun 					 reg_val << 6);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
da9052_list_voltage(struct regulator_dev * rdev,unsigned int selector)150*4882a593Smuzhiyun static int da9052_list_voltage(struct regulator_dev *rdev,
151*4882a593Smuzhiyun 				unsigned int selector)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
154*4882a593Smuzhiyun 	struct da9052_regulator_info *info = regulator->info;
155*4882a593Smuzhiyun 	int id = rdev_get_id(rdev);
156*4882a593Smuzhiyun 	int volt_uV;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	if ((id == DA9052_ID_BUCK4) && (regulator->da9052->chip_id == DA9052)
159*4882a593Smuzhiyun 		&& (selector >= DA9052_BUCK_PERI_REG_MAP_UPTO_3uV)) {
160*4882a593Smuzhiyun 		volt_uV = ((DA9052_BUCK_PERI_REG_MAP_UPTO_3uV * info->step_uV)
161*4882a593Smuzhiyun 			  + info->min_uV);
162*4882a593Smuzhiyun 		volt_uV += (selector - DA9052_BUCK_PERI_REG_MAP_UPTO_3uV)
163*4882a593Smuzhiyun 				    * (DA9052_BUCK_PERI_3uV_STEP);
164*4882a593Smuzhiyun 	} else {
165*4882a593Smuzhiyun 		volt_uV = (selector * info->step_uV) + info->min_uV;
166*4882a593Smuzhiyun 	}
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	if (volt_uV > info->max_uV)
169*4882a593Smuzhiyun 		return -EINVAL;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	return volt_uV;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
da9052_map_voltage(struct regulator_dev * rdev,int min_uV,int max_uV)174*4882a593Smuzhiyun static int da9052_map_voltage(struct regulator_dev *rdev,
175*4882a593Smuzhiyun 			      int min_uV, int max_uV)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
178*4882a593Smuzhiyun 	struct da9052_regulator_info *info = regulator->info;
179*4882a593Smuzhiyun 	int id = rdev_get_id(rdev);
180*4882a593Smuzhiyun 	int ret, sel;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	ret = verify_range(info, min_uV, max_uV);
183*4882a593Smuzhiyun 	if (ret < 0)
184*4882a593Smuzhiyun 		return ret;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	if (min_uV < info->min_uV)
187*4882a593Smuzhiyun 		min_uV = info->min_uV;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	if ((id == DA9052_ID_BUCK4) && (regulator->da9052->chip_id == DA9052)
190*4882a593Smuzhiyun 		&& (min_uV >= DA9052_CONST_3uV)) {
191*4882a593Smuzhiyun 			sel = DA9052_BUCK_PERI_REG_MAP_UPTO_3uV +
192*4882a593Smuzhiyun 			      DIV_ROUND_UP(min_uV - DA9052_CONST_3uV,
193*4882a593Smuzhiyun 					   DA9052_BUCK_PERI_3uV_STEP);
194*4882a593Smuzhiyun 	} else {
195*4882a593Smuzhiyun 		sel = DIV_ROUND_UP(min_uV - info->min_uV, info->step_uV);
196*4882a593Smuzhiyun 	}
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	ret = da9052_list_voltage(rdev, sel);
199*4882a593Smuzhiyun 	if (ret < 0)
200*4882a593Smuzhiyun 		return ret;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return sel;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
da9052_regulator_set_voltage_sel(struct regulator_dev * rdev,unsigned int selector)205*4882a593Smuzhiyun static int da9052_regulator_set_voltage_sel(struct regulator_dev *rdev,
206*4882a593Smuzhiyun 					    unsigned int selector)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
209*4882a593Smuzhiyun 	struct da9052_regulator_info *info = regulator->info;
210*4882a593Smuzhiyun 	int id = rdev_get_id(rdev);
211*4882a593Smuzhiyun 	int ret;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	ret = da9052_reg_update(regulator->da9052, rdev->desc->vsel_reg,
214*4882a593Smuzhiyun 				rdev->desc->vsel_mask, selector);
215*4882a593Smuzhiyun 	if (ret < 0)
216*4882a593Smuzhiyun 		return ret;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	/* Some LDOs and DCDCs are DVC controlled which requires enabling of
219*4882a593Smuzhiyun 	 * the activate bit to implment the changes on the output.
220*4882a593Smuzhiyun 	 */
221*4882a593Smuzhiyun 	switch (id) {
222*4882a593Smuzhiyun 	case DA9052_ID_BUCK1:
223*4882a593Smuzhiyun 	case DA9052_ID_BUCK2:
224*4882a593Smuzhiyun 	case DA9052_ID_BUCK3:
225*4882a593Smuzhiyun 	case DA9052_ID_LDO2:
226*4882a593Smuzhiyun 	case DA9052_ID_LDO3:
227*4882a593Smuzhiyun 		ret = da9052_reg_update(regulator->da9052, DA9052_SUPPLY_REG,
228*4882a593Smuzhiyun 					info->activate_bit, info->activate_bit);
229*4882a593Smuzhiyun 		break;
230*4882a593Smuzhiyun 	}
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	return ret;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun 
da9052_regulator_set_voltage_time_sel(struct regulator_dev * rdev,unsigned int old_sel,unsigned int new_sel)235*4882a593Smuzhiyun static int da9052_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
236*4882a593Smuzhiyun 						 unsigned int old_sel,
237*4882a593Smuzhiyun 						 unsigned int new_sel)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
240*4882a593Smuzhiyun 	struct da9052_regulator_info *info = regulator->info;
241*4882a593Smuzhiyun 	int id = rdev_get_id(rdev);
242*4882a593Smuzhiyun 	int ret = 0;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	/* The DVC controlled LDOs and DCDCs ramp with 6.25mV/µs after enabling
245*4882a593Smuzhiyun 	 * the activate bit.
246*4882a593Smuzhiyun 	 */
247*4882a593Smuzhiyun 	switch (id) {
248*4882a593Smuzhiyun 	case DA9052_ID_BUCK1:
249*4882a593Smuzhiyun 	case DA9052_ID_BUCK2:
250*4882a593Smuzhiyun 	case DA9052_ID_BUCK3:
251*4882a593Smuzhiyun 	case DA9052_ID_LDO2:
252*4882a593Smuzhiyun 	case DA9052_ID_LDO3:
253*4882a593Smuzhiyun 		ret = DIV_ROUND_UP(abs(new_sel - old_sel) * info->step_uV,
254*4882a593Smuzhiyun 				   6250);
255*4882a593Smuzhiyun 		break;
256*4882a593Smuzhiyun 	}
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	return ret;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun static const struct regulator_ops da9052_dcdc_ops = {
262*4882a593Smuzhiyun 	.get_current_limit = da9052_dcdc_get_current_limit,
263*4882a593Smuzhiyun 	.set_current_limit = da9052_dcdc_set_current_limit,
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	.list_voltage = da9052_list_voltage,
266*4882a593Smuzhiyun 	.map_voltage = da9052_map_voltage,
267*4882a593Smuzhiyun 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
268*4882a593Smuzhiyun 	.set_voltage_sel = da9052_regulator_set_voltage_sel,
269*4882a593Smuzhiyun 	.set_voltage_time_sel = da9052_regulator_set_voltage_time_sel,
270*4882a593Smuzhiyun 	.is_enabled = regulator_is_enabled_regmap,
271*4882a593Smuzhiyun 	.enable = regulator_enable_regmap,
272*4882a593Smuzhiyun 	.disable = regulator_disable_regmap,
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun static const struct regulator_ops da9052_ldo_ops = {
276*4882a593Smuzhiyun 	.list_voltage = da9052_list_voltage,
277*4882a593Smuzhiyun 	.map_voltage = da9052_map_voltage,
278*4882a593Smuzhiyun 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
279*4882a593Smuzhiyun 	.set_voltage_sel = da9052_regulator_set_voltage_sel,
280*4882a593Smuzhiyun 	.set_voltage_time_sel = da9052_regulator_set_voltage_time_sel,
281*4882a593Smuzhiyun 	.is_enabled = regulator_is_enabled_regmap,
282*4882a593Smuzhiyun 	.enable = regulator_enable_regmap,
283*4882a593Smuzhiyun 	.disable = regulator_disable_regmap,
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun #define DA9052_LDO(_id, _name, step, min, max, sbits, ebits, abits) \
287*4882a593Smuzhiyun {\
288*4882a593Smuzhiyun 	.reg_desc = {\
289*4882a593Smuzhiyun 		.name = #_name,\
290*4882a593Smuzhiyun 		.of_match = of_match_ptr(#_name),\
291*4882a593Smuzhiyun 		.regulators_node = of_match_ptr("regulators"),\
292*4882a593Smuzhiyun 		.ops = &da9052_ldo_ops,\
293*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,\
294*4882a593Smuzhiyun 		.id = DA9052_ID_##_id,\
295*4882a593Smuzhiyun 		.n_voltages = (max - min) / step + 1, \
296*4882a593Smuzhiyun 		.owner = THIS_MODULE,\
297*4882a593Smuzhiyun 		.vsel_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
298*4882a593Smuzhiyun 		.vsel_mask = (1 << (sbits)) - 1,\
299*4882a593Smuzhiyun 		.enable_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
300*4882a593Smuzhiyun 		.enable_mask = 1 << (ebits),\
301*4882a593Smuzhiyun 	},\
302*4882a593Smuzhiyun 	.min_uV = (min) * 1000,\
303*4882a593Smuzhiyun 	.max_uV = (max) * 1000,\
304*4882a593Smuzhiyun 	.step_uV = (step) * 1000,\
305*4882a593Smuzhiyun 	.activate_bit = (abits),\
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun #define DA9052_DCDC(_id, _name, step, min, max, sbits, ebits, abits) \
309*4882a593Smuzhiyun {\
310*4882a593Smuzhiyun 	.reg_desc = {\
311*4882a593Smuzhiyun 		.name = #_name,\
312*4882a593Smuzhiyun 		.of_match = of_match_ptr(#_name),\
313*4882a593Smuzhiyun 		.regulators_node = of_match_ptr("regulators"),\
314*4882a593Smuzhiyun 		.ops = &da9052_dcdc_ops,\
315*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,\
316*4882a593Smuzhiyun 		.id = DA9052_ID_##_id,\
317*4882a593Smuzhiyun 		.n_voltages = (max - min) / step + 1, \
318*4882a593Smuzhiyun 		.owner = THIS_MODULE,\
319*4882a593Smuzhiyun 		.vsel_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
320*4882a593Smuzhiyun 		.vsel_mask = (1 << (sbits)) - 1,\
321*4882a593Smuzhiyun 		.enable_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
322*4882a593Smuzhiyun 		.enable_mask = 1 << (ebits),\
323*4882a593Smuzhiyun 	},\
324*4882a593Smuzhiyun 	.min_uV = (min) * 1000,\
325*4882a593Smuzhiyun 	.max_uV = (max) * 1000,\
326*4882a593Smuzhiyun 	.step_uV = (step) * 1000,\
327*4882a593Smuzhiyun 	.activate_bit = (abits),\
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun static struct da9052_regulator_info da9052_regulator_info[] = {
331*4882a593Smuzhiyun 	DA9052_DCDC(BUCK1, buck1, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBCOREGO),
332*4882a593Smuzhiyun 	DA9052_DCDC(BUCK2, buck2, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBPROGO),
333*4882a593Smuzhiyun 	DA9052_DCDC(BUCK3, buck3, 25, 950, 2525, 6, 6, DA9052_SUPPLY_VBMEMGO),
334*4882a593Smuzhiyun 	DA9052_DCDC(BUCK4, buck4, 50, 1800, 3600, 5, 6, 0),
335*4882a593Smuzhiyun 	DA9052_LDO(LDO1, ldo1, 50, 600, 1800, 5, 6, 0),
336*4882a593Smuzhiyun 	DA9052_LDO(LDO2, ldo2, 25, 600, 1800, 6, 6, DA9052_SUPPLY_VLDO2GO),
337*4882a593Smuzhiyun 	DA9052_LDO(LDO3, ldo3, 25, 1725, 3300, 6, 6, DA9052_SUPPLY_VLDO3GO),
338*4882a593Smuzhiyun 	DA9052_LDO(LDO4, ldo4, 25, 1725, 3300, 6, 6, 0),
339*4882a593Smuzhiyun 	DA9052_LDO(LDO5, ldo5, 50, 1200, 3600, 6, 6, 0),
340*4882a593Smuzhiyun 	DA9052_LDO(LDO6, ldo6, 50, 1200, 3600, 6, 6, 0),
341*4882a593Smuzhiyun 	DA9052_LDO(LDO7, ldo7, 50, 1200, 3600, 6, 6, 0),
342*4882a593Smuzhiyun 	DA9052_LDO(LDO8, ldo8, 50, 1200, 3600, 6, 6, 0),
343*4882a593Smuzhiyun 	DA9052_LDO(LDO9, ldo9, 50, 1250, 3650, 6, 6, 0),
344*4882a593Smuzhiyun 	DA9052_LDO(LDO10, ldo10, 50, 1200, 3600, 6, 6, 0),
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun static struct da9052_regulator_info da9053_regulator_info[] = {
348*4882a593Smuzhiyun 	DA9052_DCDC(BUCK1, buck1, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBCOREGO),
349*4882a593Smuzhiyun 	DA9052_DCDC(BUCK2, buck2, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBPROGO),
350*4882a593Smuzhiyun 	DA9052_DCDC(BUCK3, buck3, 25, 950, 2525, 6, 6, DA9052_SUPPLY_VBMEMGO),
351*4882a593Smuzhiyun 	DA9052_DCDC(BUCK4, buck4, 25, 950, 2525, 6, 6, 0),
352*4882a593Smuzhiyun 	DA9052_LDO(LDO1, ldo1, 50, 600, 1800, 5, 6, 0),
353*4882a593Smuzhiyun 	DA9052_LDO(LDO2, ldo2, 25, 600, 1800, 6, 6, DA9052_SUPPLY_VLDO2GO),
354*4882a593Smuzhiyun 	DA9052_LDO(LDO3, ldo3, 25, 1725, 3300, 6, 6, DA9052_SUPPLY_VLDO3GO),
355*4882a593Smuzhiyun 	DA9052_LDO(LDO4, ldo4, 25, 1725, 3300, 6, 6, 0),
356*4882a593Smuzhiyun 	DA9052_LDO(LDO5, ldo5, 50, 1200, 3600, 6, 6, 0),
357*4882a593Smuzhiyun 	DA9052_LDO(LDO6, ldo6, 50, 1200, 3600, 6, 6, 0),
358*4882a593Smuzhiyun 	DA9052_LDO(LDO7, ldo7, 50, 1200, 3600, 6, 6, 0),
359*4882a593Smuzhiyun 	DA9052_LDO(LDO8, ldo8, 50, 1200, 3600, 6, 6, 0),
360*4882a593Smuzhiyun 	DA9052_LDO(LDO9, ldo9, 50, 1250, 3650, 6, 6, 0),
361*4882a593Smuzhiyun 	DA9052_LDO(LDO10, ldo10, 50, 1200, 3600, 6, 6, 0),
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun 
find_regulator_info(u8 chip_id,int id)364*4882a593Smuzhiyun static inline struct da9052_regulator_info *find_regulator_info(u8 chip_id,
365*4882a593Smuzhiyun 								 int id)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	struct da9052_regulator_info *info;
368*4882a593Smuzhiyun 	int i;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	switch (chip_id) {
371*4882a593Smuzhiyun 	case DA9052:
372*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(da9052_regulator_info); i++) {
373*4882a593Smuzhiyun 			info = &da9052_regulator_info[i];
374*4882a593Smuzhiyun 			if (info->reg_desc.id == id)
375*4882a593Smuzhiyun 				return info;
376*4882a593Smuzhiyun 		}
377*4882a593Smuzhiyun 		break;
378*4882a593Smuzhiyun 	case DA9053_AA:
379*4882a593Smuzhiyun 	case DA9053_BA:
380*4882a593Smuzhiyun 	case DA9053_BB:
381*4882a593Smuzhiyun 	case DA9053_BC:
382*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(da9053_regulator_info); i++) {
383*4882a593Smuzhiyun 			info = &da9053_regulator_info[i];
384*4882a593Smuzhiyun 			if (info->reg_desc.id == id)
385*4882a593Smuzhiyun 				return info;
386*4882a593Smuzhiyun 		}
387*4882a593Smuzhiyun 		break;
388*4882a593Smuzhiyun 	}
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	return NULL;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun 
da9052_regulator_probe(struct platform_device * pdev)393*4882a593Smuzhiyun static int da9052_regulator_probe(struct platform_device *pdev)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun 	const struct mfd_cell *cell = mfd_get_cell(pdev);
396*4882a593Smuzhiyun 	struct regulator_config config = { };
397*4882a593Smuzhiyun 	struct da9052_regulator *regulator;
398*4882a593Smuzhiyun 	struct da9052 *da9052;
399*4882a593Smuzhiyun 	struct da9052_pdata *pdata;
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	regulator = devm_kzalloc(&pdev->dev, sizeof(struct da9052_regulator),
402*4882a593Smuzhiyun 				 GFP_KERNEL);
403*4882a593Smuzhiyun 	if (!regulator)
404*4882a593Smuzhiyun 		return -ENOMEM;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	da9052 = dev_get_drvdata(pdev->dev.parent);
407*4882a593Smuzhiyun 	pdata = dev_get_platdata(da9052->dev);
408*4882a593Smuzhiyun 	regulator->da9052 = da9052;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	regulator->info = find_regulator_info(regulator->da9052->chip_id,
411*4882a593Smuzhiyun 					      cell->id);
412*4882a593Smuzhiyun 	if (regulator->info == NULL) {
413*4882a593Smuzhiyun 		dev_err(&pdev->dev, "invalid regulator ID specified\n");
414*4882a593Smuzhiyun 		return -EINVAL;
415*4882a593Smuzhiyun 	}
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	config.dev = da9052->dev;
418*4882a593Smuzhiyun 	config.driver_data = regulator;
419*4882a593Smuzhiyun 	config.regmap = da9052->regmap;
420*4882a593Smuzhiyun 	if (pdata)
421*4882a593Smuzhiyun 		config.init_data = pdata->regulators[cell->id];
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	regulator->rdev = devm_regulator_register(&pdev->dev,
424*4882a593Smuzhiyun 						  &regulator->info->reg_desc,
425*4882a593Smuzhiyun 						  &config);
426*4882a593Smuzhiyun 	if (IS_ERR(regulator->rdev)) {
427*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to register regulator %s\n",
428*4882a593Smuzhiyun 			regulator->info->reg_desc.name);
429*4882a593Smuzhiyun 		return PTR_ERR(regulator->rdev);
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	platform_set_drvdata(pdev, regulator);
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	return 0;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun static struct platform_driver da9052_regulator_driver = {
438*4882a593Smuzhiyun 	.probe = da9052_regulator_probe,
439*4882a593Smuzhiyun 	.driver = {
440*4882a593Smuzhiyun 		.name = "da9052-regulator",
441*4882a593Smuzhiyun 	},
442*4882a593Smuzhiyun };
443*4882a593Smuzhiyun 
da9052_regulator_init(void)444*4882a593Smuzhiyun static int __init da9052_regulator_init(void)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun 	return platform_driver_register(&da9052_regulator_driver);
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun subsys_initcall(da9052_regulator_init);
449*4882a593Smuzhiyun 
da9052_regulator_exit(void)450*4882a593Smuzhiyun static void __exit da9052_regulator_exit(void)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	platform_driver_unregister(&da9052_regulator_driver);
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun module_exit(da9052_regulator_exit);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
457*4882a593Smuzhiyun MODULE_DESCRIPTION("Power Regulator driver for Dialog DA9052 PMIC");
458*4882a593Smuzhiyun MODULE_LICENSE("GPL");
459*4882a593Smuzhiyun MODULE_ALIAS("platform:da9052-regulator");
460