1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Voltage regulator support for AMS AS3722 PMIC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 ams
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Florian Lobmaier <florian.lobmaier@ams.com>
8*4882a593Smuzhiyun * Author: Laxman Dewangan <ldewangan@nvidia.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/mfd/as3722.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/of_platform.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/regulator/driver.h>
19*4882a593Smuzhiyun #include <linux/regulator/machine.h>
20*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* Regulator IDs */
24*4882a593Smuzhiyun enum as3722_regulators_id {
25*4882a593Smuzhiyun AS3722_REGULATOR_ID_SD0,
26*4882a593Smuzhiyun AS3722_REGULATOR_ID_SD1,
27*4882a593Smuzhiyun AS3722_REGULATOR_ID_SD2,
28*4882a593Smuzhiyun AS3722_REGULATOR_ID_SD3,
29*4882a593Smuzhiyun AS3722_REGULATOR_ID_SD4,
30*4882a593Smuzhiyun AS3722_REGULATOR_ID_SD5,
31*4882a593Smuzhiyun AS3722_REGULATOR_ID_SD6,
32*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO0,
33*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO1,
34*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO2,
35*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO3,
36*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO4,
37*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO5,
38*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO6,
39*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO7,
40*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO9,
41*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO10,
42*4882a593Smuzhiyun AS3722_REGULATOR_ID_LDO11,
43*4882a593Smuzhiyun AS3722_REGULATOR_ID_MAX,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct as3722_register_mapping {
47*4882a593Smuzhiyun u8 regulator_id;
48*4882a593Smuzhiyun const char *name;
49*4882a593Smuzhiyun const char *sname;
50*4882a593Smuzhiyun u8 vsel_reg;
51*4882a593Smuzhiyun u8 vsel_mask;
52*4882a593Smuzhiyun int n_voltages;
53*4882a593Smuzhiyun u32 enable_reg;
54*4882a593Smuzhiyun u8 enable_mask;
55*4882a593Smuzhiyun u32 control_reg;
56*4882a593Smuzhiyun u8 mode_mask;
57*4882a593Smuzhiyun u32 sleep_ctrl_reg;
58*4882a593Smuzhiyun u8 sleep_ctrl_mask;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun struct as3722_regulator_config_data {
62*4882a593Smuzhiyun struct regulator_init_data *reg_init;
63*4882a593Smuzhiyun bool enable_tracking;
64*4882a593Smuzhiyun int ext_control;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct as3722_regulators {
68*4882a593Smuzhiyun struct device *dev;
69*4882a593Smuzhiyun struct as3722 *as3722;
70*4882a593Smuzhiyun struct regulator_desc desc[AS3722_REGULATOR_ID_MAX];
71*4882a593Smuzhiyun struct as3722_regulator_config_data
72*4882a593Smuzhiyun reg_config_data[AS3722_REGULATOR_ID_MAX];
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const struct as3722_register_mapping as3722_reg_lookup[] = {
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_SD0,
78*4882a593Smuzhiyun .name = "as3722-sd0",
79*4882a593Smuzhiyun .vsel_reg = AS3722_SD0_VOLTAGE_REG,
80*4882a593Smuzhiyun .vsel_mask = AS3722_SD_VSEL_MASK,
81*4882a593Smuzhiyun .enable_reg = AS3722_SD_CONTROL_REG,
82*4882a593Smuzhiyun .enable_mask = AS3722_SDn_CTRL(0),
83*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL1_REG,
84*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_SD0_EXT_ENABLE_MASK,
85*4882a593Smuzhiyun .control_reg = AS3722_SD0_CONTROL_REG,
86*4882a593Smuzhiyun .mode_mask = AS3722_SD0_MODE_FAST,
87*4882a593Smuzhiyun },
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_SD1,
90*4882a593Smuzhiyun .name = "as3722-sd1",
91*4882a593Smuzhiyun .vsel_reg = AS3722_SD1_VOLTAGE_REG,
92*4882a593Smuzhiyun .vsel_mask = AS3722_SD_VSEL_MASK,
93*4882a593Smuzhiyun .enable_reg = AS3722_SD_CONTROL_REG,
94*4882a593Smuzhiyun .enable_mask = AS3722_SDn_CTRL(1),
95*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL1_REG,
96*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_SD1_EXT_ENABLE_MASK,
97*4882a593Smuzhiyun .control_reg = AS3722_SD1_CONTROL_REG,
98*4882a593Smuzhiyun .mode_mask = AS3722_SD1_MODE_FAST,
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_SD2,
102*4882a593Smuzhiyun .name = "as3722-sd2",
103*4882a593Smuzhiyun .sname = "vsup-sd2",
104*4882a593Smuzhiyun .vsel_reg = AS3722_SD2_VOLTAGE_REG,
105*4882a593Smuzhiyun .vsel_mask = AS3722_SD_VSEL_MASK,
106*4882a593Smuzhiyun .enable_reg = AS3722_SD_CONTROL_REG,
107*4882a593Smuzhiyun .enable_mask = AS3722_SDn_CTRL(2),
108*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL1_REG,
109*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_SD2_EXT_ENABLE_MASK,
110*4882a593Smuzhiyun .control_reg = AS3722_SD23_CONTROL_REG,
111*4882a593Smuzhiyun .mode_mask = AS3722_SD2_MODE_FAST,
112*4882a593Smuzhiyun .n_voltages = AS3722_SD2_VSEL_MAX + 1,
113*4882a593Smuzhiyun },
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_SD3,
116*4882a593Smuzhiyun .name = "as3722-sd3",
117*4882a593Smuzhiyun .sname = "vsup-sd3",
118*4882a593Smuzhiyun .vsel_reg = AS3722_SD3_VOLTAGE_REG,
119*4882a593Smuzhiyun .vsel_mask = AS3722_SD_VSEL_MASK,
120*4882a593Smuzhiyun .enable_reg = AS3722_SD_CONTROL_REG,
121*4882a593Smuzhiyun .enable_mask = AS3722_SDn_CTRL(3),
122*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL1_REG,
123*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_SD3_EXT_ENABLE_MASK,
124*4882a593Smuzhiyun .control_reg = AS3722_SD23_CONTROL_REG,
125*4882a593Smuzhiyun .mode_mask = AS3722_SD3_MODE_FAST,
126*4882a593Smuzhiyun .n_voltages = AS3722_SD2_VSEL_MAX + 1,
127*4882a593Smuzhiyun },
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_SD4,
130*4882a593Smuzhiyun .name = "as3722-sd4",
131*4882a593Smuzhiyun .sname = "vsup-sd4",
132*4882a593Smuzhiyun .vsel_reg = AS3722_SD4_VOLTAGE_REG,
133*4882a593Smuzhiyun .vsel_mask = AS3722_SD_VSEL_MASK,
134*4882a593Smuzhiyun .enable_reg = AS3722_SD_CONTROL_REG,
135*4882a593Smuzhiyun .enable_mask = AS3722_SDn_CTRL(4),
136*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL2_REG,
137*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_SD4_EXT_ENABLE_MASK,
138*4882a593Smuzhiyun .control_reg = AS3722_SD4_CONTROL_REG,
139*4882a593Smuzhiyun .mode_mask = AS3722_SD4_MODE_FAST,
140*4882a593Smuzhiyun .n_voltages = AS3722_SD2_VSEL_MAX + 1,
141*4882a593Smuzhiyun },
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_SD5,
144*4882a593Smuzhiyun .name = "as3722-sd5",
145*4882a593Smuzhiyun .sname = "vsup-sd5",
146*4882a593Smuzhiyun .vsel_reg = AS3722_SD5_VOLTAGE_REG,
147*4882a593Smuzhiyun .vsel_mask = AS3722_SD_VSEL_MASK,
148*4882a593Smuzhiyun .enable_reg = AS3722_SD_CONTROL_REG,
149*4882a593Smuzhiyun .enable_mask = AS3722_SDn_CTRL(5),
150*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL2_REG,
151*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_SD5_EXT_ENABLE_MASK,
152*4882a593Smuzhiyun .control_reg = AS3722_SD5_CONTROL_REG,
153*4882a593Smuzhiyun .mode_mask = AS3722_SD5_MODE_FAST,
154*4882a593Smuzhiyun .n_voltages = AS3722_SD2_VSEL_MAX + 1,
155*4882a593Smuzhiyun },
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_SD6,
158*4882a593Smuzhiyun .name = "as3722-sd6",
159*4882a593Smuzhiyun .vsel_reg = AS3722_SD6_VOLTAGE_REG,
160*4882a593Smuzhiyun .vsel_mask = AS3722_SD_VSEL_MASK,
161*4882a593Smuzhiyun .enable_reg = AS3722_SD_CONTROL_REG,
162*4882a593Smuzhiyun .enable_mask = AS3722_SDn_CTRL(6),
163*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL2_REG,
164*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_SD6_EXT_ENABLE_MASK,
165*4882a593Smuzhiyun .control_reg = AS3722_SD6_CONTROL_REG,
166*4882a593Smuzhiyun .mode_mask = AS3722_SD6_MODE_FAST,
167*4882a593Smuzhiyun },
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO0,
170*4882a593Smuzhiyun .name = "as3722-ldo0",
171*4882a593Smuzhiyun .sname = "vin-ldo0",
172*4882a593Smuzhiyun .vsel_reg = AS3722_LDO0_VOLTAGE_REG,
173*4882a593Smuzhiyun .vsel_mask = AS3722_LDO0_VSEL_MASK,
174*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL0_REG,
175*4882a593Smuzhiyun .enable_mask = AS3722_LDO0_CTRL,
176*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL3_REG,
177*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO0_EXT_ENABLE_MASK,
178*4882a593Smuzhiyun .n_voltages = AS3722_LDO0_NUM_VOLT,
179*4882a593Smuzhiyun },
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO1,
182*4882a593Smuzhiyun .name = "as3722-ldo1",
183*4882a593Smuzhiyun .sname = "vin-ldo1-6",
184*4882a593Smuzhiyun .vsel_reg = AS3722_LDO1_VOLTAGE_REG,
185*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
186*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL0_REG,
187*4882a593Smuzhiyun .enable_mask = AS3722_LDO1_CTRL,
188*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL3_REG,
189*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO1_EXT_ENABLE_MASK,
190*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
191*4882a593Smuzhiyun },
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO2,
194*4882a593Smuzhiyun .name = "as3722-ldo2",
195*4882a593Smuzhiyun .sname = "vin-ldo2-5-7",
196*4882a593Smuzhiyun .vsel_reg = AS3722_LDO2_VOLTAGE_REG,
197*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
198*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL0_REG,
199*4882a593Smuzhiyun .enable_mask = AS3722_LDO2_CTRL,
200*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL3_REG,
201*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO2_EXT_ENABLE_MASK,
202*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
203*4882a593Smuzhiyun },
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO3,
206*4882a593Smuzhiyun .name = "as3722-ldo3",
207*4882a593Smuzhiyun .sname = "vin-ldo3-4",
208*4882a593Smuzhiyun .vsel_reg = AS3722_LDO3_VOLTAGE_REG,
209*4882a593Smuzhiyun .vsel_mask = AS3722_LDO3_VSEL_MASK,
210*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL0_REG,
211*4882a593Smuzhiyun .enable_mask = AS3722_LDO3_CTRL,
212*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL3_REG,
213*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO3_EXT_ENABLE_MASK,
214*4882a593Smuzhiyun .n_voltages = AS3722_LDO3_NUM_VOLT,
215*4882a593Smuzhiyun },
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO4,
218*4882a593Smuzhiyun .name = "as3722-ldo4",
219*4882a593Smuzhiyun .sname = "vin-ldo3-4",
220*4882a593Smuzhiyun .vsel_reg = AS3722_LDO4_VOLTAGE_REG,
221*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
222*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL0_REG,
223*4882a593Smuzhiyun .enable_mask = AS3722_LDO4_CTRL,
224*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL4_REG,
225*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO4_EXT_ENABLE_MASK,
226*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
227*4882a593Smuzhiyun },
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO5,
230*4882a593Smuzhiyun .name = "as3722-ldo5",
231*4882a593Smuzhiyun .sname = "vin-ldo2-5-7",
232*4882a593Smuzhiyun .vsel_reg = AS3722_LDO5_VOLTAGE_REG,
233*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
234*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL0_REG,
235*4882a593Smuzhiyun .enable_mask = AS3722_LDO5_CTRL,
236*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL4_REG,
237*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO5_EXT_ENABLE_MASK,
238*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
239*4882a593Smuzhiyun },
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO6,
242*4882a593Smuzhiyun .name = "as3722-ldo6",
243*4882a593Smuzhiyun .sname = "vin-ldo1-6",
244*4882a593Smuzhiyun .vsel_reg = AS3722_LDO6_VOLTAGE_REG,
245*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
246*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL0_REG,
247*4882a593Smuzhiyun .enable_mask = AS3722_LDO6_CTRL,
248*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL4_REG,
249*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO6_EXT_ENABLE_MASK,
250*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
251*4882a593Smuzhiyun },
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO7,
254*4882a593Smuzhiyun .name = "as3722-ldo7",
255*4882a593Smuzhiyun .sname = "vin-ldo2-5-7",
256*4882a593Smuzhiyun .vsel_reg = AS3722_LDO7_VOLTAGE_REG,
257*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
258*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL0_REG,
259*4882a593Smuzhiyun .enable_mask = AS3722_LDO7_CTRL,
260*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL4_REG,
261*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO7_EXT_ENABLE_MASK,
262*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
263*4882a593Smuzhiyun },
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO9,
266*4882a593Smuzhiyun .name = "as3722-ldo9",
267*4882a593Smuzhiyun .sname = "vin-ldo9-10",
268*4882a593Smuzhiyun .vsel_reg = AS3722_LDO9_VOLTAGE_REG,
269*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
270*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL1_REG,
271*4882a593Smuzhiyun .enable_mask = AS3722_LDO9_CTRL,
272*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL5_REG,
273*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO9_EXT_ENABLE_MASK,
274*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
275*4882a593Smuzhiyun },
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO10,
278*4882a593Smuzhiyun .name = "as3722-ldo10",
279*4882a593Smuzhiyun .sname = "vin-ldo9-10",
280*4882a593Smuzhiyun .vsel_reg = AS3722_LDO10_VOLTAGE_REG,
281*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
282*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL1_REG,
283*4882a593Smuzhiyun .enable_mask = AS3722_LDO10_CTRL,
284*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL5_REG,
285*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO10_EXT_ENABLE_MASK,
286*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
287*4882a593Smuzhiyun },
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun .regulator_id = AS3722_REGULATOR_ID_LDO11,
290*4882a593Smuzhiyun .name = "as3722-ldo11",
291*4882a593Smuzhiyun .sname = "vin-ldo11",
292*4882a593Smuzhiyun .vsel_reg = AS3722_LDO11_VOLTAGE_REG,
293*4882a593Smuzhiyun .vsel_mask = AS3722_LDO_VSEL_MASK,
294*4882a593Smuzhiyun .enable_reg = AS3722_LDOCONTROL1_REG,
295*4882a593Smuzhiyun .enable_mask = AS3722_LDO11_CTRL,
296*4882a593Smuzhiyun .sleep_ctrl_reg = AS3722_ENABLE_CTRL5_REG,
297*4882a593Smuzhiyun .sleep_ctrl_mask = AS3722_LDO11_EXT_ENABLE_MASK,
298*4882a593Smuzhiyun .n_voltages = AS3722_LDO_NUM_VOLT,
299*4882a593Smuzhiyun },
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun static const unsigned int as3722_ldo_current[] = { 150000, 300000 };
303*4882a593Smuzhiyun static const unsigned int as3722_sd016_current[] = {
304*4882a593Smuzhiyun 2500000, 3000000, 3500000
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun static const struct regulator_ops as3722_ldo0_ops = {
308*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
309*4882a593Smuzhiyun .enable = regulator_enable_regmap,
310*4882a593Smuzhiyun .disable = regulator_disable_regmap,
311*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
312*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
313*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
314*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
315*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun static const struct regulator_ops as3722_ldo0_extcntrl_ops = {
319*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
320*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
321*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
322*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
323*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun
as3722_ldo3_set_tracking_mode(struct as3722_regulators * as3722_reg,int id,u8 mode)326*4882a593Smuzhiyun static int as3722_ldo3_set_tracking_mode(struct as3722_regulators *as3722_reg,
327*4882a593Smuzhiyun int id, u8 mode)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun struct as3722 *as3722 = as3722_reg->as3722;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun switch (mode) {
332*4882a593Smuzhiyun case AS3722_LDO3_MODE_PMOS:
333*4882a593Smuzhiyun case AS3722_LDO3_MODE_PMOS_TRACKING:
334*4882a593Smuzhiyun case AS3722_LDO3_MODE_NMOS:
335*4882a593Smuzhiyun case AS3722_LDO3_MODE_SWITCH:
336*4882a593Smuzhiyun return as3722_update_bits(as3722,
337*4882a593Smuzhiyun as3722_reg_lookup[id].vsel_reg,
338*4882a593Smuzhiyun AS3722_LDO3_MODE_MASK, mode);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun default:
341*4882a593Smuzhiyun return -EINVAL;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
as3722_ldo3_get_current_limit(struct regulator_dev * rdev)345*4882a593Smuzhiyun static int as3722_ldo3_get_current_limit(struct regulator_dev *rdev)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun return 150000;
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun static const struct regulator_ops as3722_ldo3_ops = {
351*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
352*4882a593Smuzhiyun .enable = regulator_enable_regmap,
353*4882a593Smuzhiyun .disable = regulator_disable_regmap,
354*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
355*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
356*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
357*4882a593Smuzhiyun .get_current_limit = as3722_ldo3_get_current_limit,
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun static const struct regulator_ops as3722_ldo3_extcntrl_ops = {
361*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
362*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
363*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
364*4882a593Smuzhiyun .get_current_limit = as3722_ldo3_get_current_limit,
365*4882a593Smuzhiyun };
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun static const struct regulator_ops as3722_ldo6_ops = {
368*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
369*4882a593Smuzhiyun .enable = regulator_enable_regmap,
370*4882a593Smuzhiyun .disable = regulator_disable_regmap,
371*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
372*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
373*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
374*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
375*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
376*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
377*4882a593Smuzhiyun .get_bypass = regulator_get_bypass_regmap,
378*4882a593Smuzhiyun .set_bypass = regulator_set_bypass_regmap,
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun static const struct regulator_ops as3722_ldo6_extcntrl_ops = {
382*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
383*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
384*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
385*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
386*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
387*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
388*4882a593Smuzhiyun .get_bypass = regulator_get_bypass_regmap,
389*4882a593Smuzhiyun .set_bypass = regulator_set_bypass_regmap,
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun static const struct linear_range as3722_ldo_ranges[] = {
393*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(0, 0x00, 0x00, 0),
394*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(825000, 0x01, 0x24, 25000),
395*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1725000, 0x40, 0x7F, 25000),
396*4882a593Smuzhiyun };
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun static const struct regulator_ops as3722_ldo_ops = {
399*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
400*4882a593Smuzhiyun .enable = regulator_enable_regmap,
401*4882a593Smuzhiyun .disable = regulator_disable_regmap,
402*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
403*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
404*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
405*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
406*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
407*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
408*4882a593Smuzhiyun };
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun static const struct regulator_ops as3722_ldo_extcntrl_ops = {
411*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
412*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
413*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
414*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
415*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
416*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
417*4882a593Smuzhiyun };
418*4882a593Smuzhiyun
as3722_sd_get_mode(struct regulator_dev * rdev)419*4882a593Smuzhiyun static unsigned int as3722_sd_get_mode(struct regulator_dev *rdev)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun struct as3722_regulators *as3722_regs = rdev_get_drvdata(rdev);
422*4882a593Smuzhiyun struct as3722 *as3722 = as3722_regs->as3722;
423*4882a593Smuzhiyun int id = rdev_get_id(rdev);
424*4882a593Smuzhiyun u32 val;
425*4882a593Smuzhiyun int ret;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun if (!as3722_reg_lookup[id].control_reg)
428*4882a593Smuzhiyun return -ENOTSUPP;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun ret = as3722_read(as3722, as3722_reg_lookup[id].control_reg, &val);
431*4882a593Smuzhiyun if (ret < 0) {
432*4882a593Smuzhiyun dev_err(as3722_regs->dev, "Reg 0x%02x read failed: %d\n",
433*4882a593Smuzhiyun as3722_reg_lookup[id].control_reg, ret);
434*4882a593Smuzhiyun return ret;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if (val & as3722_reg_lookup[id].mode_mask)
438*4882a593Smuzhiyun return REGULATOR_MODE_FAST;
439*4882a593Smuzhiyun else
440*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
as3722_sd_set_mode(struct regulator_dev * rdev,unsigned int mode)443*4882a593Smuzhiyun static int as3722_sd_set_mode(struct regulator_dev *rdev,
444*4882a593Smuzhiyun unsigned int mode)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun struct as3722_regulators *as3722_regs = rdev_get_drvdata(rdev);
447*4882a593Smuzhiyun struct as3722 *as3722 = as3722_regs->as3722;
448*4882a593Smuzhiyun u8 id = rdev_get_id(rdev);
449*4882a593Smuzhiyun u8 val = 0;
450*4882a593Smuzhiyun int ret;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun if (!as3722_reg_lookup[id].control_reg)
453*4882a593Smuzhiyun return -ERANGE;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun switch (mode) {
456*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
457*4882a593Smuzhiyun val = as3722_reg_lookup[id].mode_mask;
458*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL: /* fall down */
459*4882a593Smuzhiyun break;
460*4882a593Smuzhiyun default:
461*4882a593Smuzhiyun return -EINVAL;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun ret = as3722_update_bits(as3722, as3722_reg_lookup[id].control_reg,
465*4882a593Smuzhiyun as3722_reg_lookup[id].mode_mask, val);
466*4882a593Smuzhiyun if (ret < 0) {
467*4882a593Smuzhiyun dev_err(as3722_regs->dev, "Reg 0x%02x update failed: %d\n",
468*4882a593Smuzhiyun as3722_reg_lookup[id].control_reg, ret);
469*4882a593Smuzhiyun return ret;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun return ret;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
as3722_sd0_is_low_voltage(struct as3722_regulators * as3722_regs)474*4882a593Smuzhiyun static bool as3722_sd0_is_low_voltage(struct as3722_regulators *as3722_regs)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun int err;
477*4882a593Smuzhiyun unsigned val;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun err = as3722_read(as3722_regs->as3722, AS3722_FUSE7_REG, &val);
480*4882a593Smuzhiyun if (err < 0) {
481*4882a593Smuzhiyun dev_err(as3722_regs->dev, "Reg 0x%02x read failed: %d\n",
482*4882a593Smuzhiyun AS3722_FUSE7_REG, err);
483*4882a593Smuzhiyun return false;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun if (val & AS3722_FUSE7_SD0_LOW_VOLTAGE)
486*4882a593Smuzhiyun return true;
487*4882a593Smuzhiyun return false;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun static const struct linear_range as3722_sd2345_ranges[] = {
491*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(0, 0x00, 0x00, 0),
492*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(612500, 0x01, 0x40, 12500),
493*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1425000, 0x41, 0x70, 25000),
494*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2650000, 0x71, 0x7F, 50000),
495*4882a593Smuzhiyun };
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun static const struct regulator_ops as3722_sd016_ops = {
498*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
499*4882a593Smuzhiyun .enable = regulator_enable_regmap,
500*4882a593Smuzhiyun .disable = regulator_disable_regmap,
501*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
502*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
503*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
504*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
505*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
506*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
507*4882a593Smuzhiyun .get_mode = as3722_sd_get_mode,
508*4882a593Smuzhiyun .set_mode = as3722_sd_set_mode,
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun static const struct regulator_ops as3722_sd016_extcntrl_ops = {
512*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
513*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
514*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
515*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
516*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
517*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
518*4882a593Smuzhiyun .get_mode = as3722_sd_get_mode,
519*4882a593Smuzhiyun .set_mode = as3722_sd_set_mode,
520*4882a593Smuzhiyun };
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun static const struct regulator_ops as3722_sd2345_ops = {
523*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
524*4882a593Smuzhiyun .enable = regulator_enable_regmap,
525*4882a593Smuzhiyun .disable = regulator_disable_regmap,
526*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
527*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
528*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
529*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
530*4882a593Smuzhiyun .get_mode = as3722_sd_get_mode,
531*4882a593Smuzhiyun .set_mode = as3722_sd_set_mode,
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun static const struct regulator_ops as3722_sd2345_extcntrl_ops = {
535*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
536*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
537*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
538*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
539*4882a593Smuzhiyun .get_mode = as3722_sd_get_mode,
540*4882a593Smuzhiyun .set_mode = as3722_sd_set_mode,
541*4882a593Smuzhiyun };
542*4882a593Smuzhiyun
as3722_extreg_init(struct as3722_regulators * as3722_regs,int id,int ext_pwr_ctrl)543*4882a593Smuzhiyun static int as3722_extreg_init(struct as3722_regulators *as3722_regs, int id,
544*4882a593Smuzhiyun int ext_pwr_ctrl)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun int ret;
547*4882a593Smuzhiyun unsigned int val;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun if ((ext_pwr_ctrl < AS3722_EXT_CONTROL_ENABLE1) ||
550*4882a593Smuzhiyun (ext_pwr_ctrl > AS3722_EXT_CONTROL_ENABLE3))
551*4882a593Smuzhiyun return -EINVAL;
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun val = ext_pwr_ctrl << (ffs(as3722_reg_lookup[id].sleep_ctrl_mask) - 1);
554*4882a593Smuzhiyun ret = as3722_update_bits(as3722_regs->as3722,
555*4882a593Smuzhiyun as3722_reg_lookup[id].sleep_ctrl_reg,
556*4882a593Smuzhiyun as3722_reg_lookup[id].sleep_ctrl_mask, val);
557*4882a593Smuzhiyun if (ret < 0)
558*4882a593Smuzhiyun dev_err(as3722_regs->dev, "Reg 0x%02x update failed: %d\n",
559*4882a593Smuzhiyun as3722_reg_lookup[id].sleep_ctrl_reg, ret);
560*4882a593Smuzhiyun return ret;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun static struct of_regulator_match as3722_regulator_matches[] = {
564*4882a593Smuzhiyun { .name = "sd0", },
565*4882a593Smuzhiyun { .name = "sd1", },
566*4882a593Smuzhiyun { .name = "sd2", },
567*4882a593Smuzhiyun { .name = "sd3", },
568*4882a593Smuzhiyun { .name = "sd4", },
569*4882a593Smuzhiyun { .name = "sd5", },
570*4882a593Smuzhiyun { .name = "sd6", },
571*4882a593Smuzhiyun { .name = "ldo0", },
572*4882a593Smuzhiyun { .name = "ldo1", },
573*4882a593Smuzhiyun { .name = "ldo2", },
574*4882a593Smuzhiyun { .name = "ldo3", },
575*4882a593Smuzhiyun { .name = "ldo4", },
576*4882a593Smuzhiyun { .name = "ldo5", },
577*4882a593Smuzhiyun { .name = "ldo6", },
578*4882a593Smuzhiyun { .name = "ldo7", },
579*4882a593Smuzhiyun { .name = "ldo9", },
580*4882a593Smuzhiyun { .name = "ldo10", },
581*4882a593Smuzhiyun { .name = "ldo11", },
582*4882a593Smuzhiyun };
583*4882a593Smuzhiyun
as3722_get_regulator_dt_data(struct platform_device * pdev,struct as3722_regulators * as3722_regs)584*4882a593Smuzhiyun static int as3722_get_regulator_dt_data(struct platform_device *pdev,
585*4882a593Smuzhiyun struct as3722_regulators *as3722_regs)
586*4882a593Smuzhiyun {
587*4882a593Smuzhiyun struct device_node *np;
588*4882a593Smuzhiyun struct as3722_regulator_config_data *reg_config;
589*4882a593Smuzhiyun u32 prop;
590*4882a593Smuzhiyun int id;
591*4882a593Smuzhiyun int ret;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun np = of_get_child_by_name(pdev->dev.parent->of_node, "regulators");
594*4882a593Smuzhiyun if (!np) {
595*4882a593Smuzhiyun dev_err(&pdev->dev, "Device is not having regulators node\n");
596*4882a593Smuzhiyun return -ENODEV;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun pdev->dev.of_node = np;
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun ret = of_regulator_match(&pdev->dev, np, as3722_regulator_matches,
601*4882a593Smuzhiyun ARRAY_SIZE(as3722_regulator_matches));
602*4882a593Smuzhiyun of_node_put(np);
603*4882a593Smuzhiyun if (ret < 0) {
604*4882a593Smuzhiyun dev_err(&pdev->dev, "Parsing of regulator node failed: %d\n",
605*4882a593Smuzhiyun ret);
606*4882a593Smuzhiyun return ret;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun for (id = 0; id < ARRAY_SIZE(as3722_regulator_matches); ++id) {
610*4882a593Smuzhiyun struct device_node *reg_node;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun reg_config = &as3722_regs->reg_config_data[id];
613*4882a593Smuzhiyun reg_config->reg_init = as3722_regulator_matches[id].init_data;
614*4882a593Smuzhiyun reg_node = as3722_regulator_matches[id].of_node;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun if (!reg_config->reg_init || !reg_node)
617*4882a593Smuzhiyun continue;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun ret = of_property_read_u32(reg_node, "ams,ext-control", &prop);
620*4882a593Smuzhiyun if (!ret) {
621*4882a593Smuzhiyun if (prop < 3)
622*4882a593Smuzhiyun reg_config->ext_control = prop;
623*4882a593Smuzhiyun else
624*4882a593Smuzhiyun dev_warn(&pdev->dev,
625*4882a593Smuzhiyun "ext-control have invalid option: %u\n",
626*4882a593Smuzhiyun prop);
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun reg_config->enable_tracking =
629*4882a593Smuzhiyun of_property_read_bool(reg_node, "ams,enable-tracking");
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun return 0;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
as3722_regulator_probe(struct platform_device * pdev)634*4882a593Smuzhiyun static int as3722_regulator_probe(struct platform_device *pdev)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun struct as3722 *as3722 = dev_get_drvdata(pdev->dev.parent);
637*4882a593Smuzhiyun struct as3722_regulators *as3722_regs;
638*4882a593Smuzhiyun struct as3722_regulator_config_data *reg_config;
639*4882a593Smuzhiyun struct regulator_dev *rdev;
640*4882a593Smuzhiyun struct regulator_config config = { };
641*4882a593Smuzhiyun const struct regulator_ops *ops;
642*4882a593Smuzhiyun int id;
643*4882a593Smuzhiyun int ret;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun as3722_regs = devm_kzalloc(&pdev->dev, sizeof(*as3722_regs),
646*4882a593Smuzhiyun GFP_KERNEL);
647*4882a593Smuzhiyun if (!as3722_regs)
648*4882a593Smuzhiyun return -ENOMEM;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun as3722_regs->dev = &pdev->dev;
651*4882a593Smuzhiyun as3722_regs->as3722 = as3722;
652*4882a593Smuzhiyun platform_set_drvdata(pdev, as3722_regs);
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun ret = as3722_get_regulator_dt_data(pdev, as3722_regs);
655*4882a593Smuzhiyun if (ret < 0)
656*4882a593Smuzhiyun return ret;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun config.dev = &pdev->dev;
659*4882a593Smuzhiyun config.driver_data = as3722_regs;
660*4882a593Smuzhiyun config.regmap = as3722->regmap;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun for (id = 0; id < AS3722_REGULATOR_ID_MAX; id++) {
663*4882a593Smuzhiyun struct regulator_desc *desc;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun desc = &as3722_regs->desc[id];
666*4882a593Smuzhiyun reg_config = &as3722_regs->reg_config_data[id];
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun desc->name = as3722_reg_lookup[id].name;
669*4882a593Smuzhiyun desc->supply_name = as3722_reg_lookup[id].sname;
670*4882a593Smuzhiyun desc->id = as3722_reg_lookup[id].regulator_id;
671*4882a593Smuzhiyun desc->n_voltages = as3722_reg_lookup[id].n_voltages;
672*4882a593Smuzhiyun desc->type = REGULATOR_VOLTAGE;
673*4882a593Smuzhiyun desc->owner = THIS_MODULE;
674*4882a593Smuzhiyun desc->enable_reg = as3722_reg_lookup[id].enable_reg;
675*4882a593Smuzhiyun desc->enable_mask = as3722_reg_lookup[id].enable_mask;
676*4882a593Smuzhiyun desc->vsel_reg = as3722_reg_lookup[id].vsel_reg;
677*4882a593Smuzhiyun desc->vsel_mask = as3722_reg_lookup[id].vsel_mask;
678*4882a593Smuzhiyun switch (id) {
679*4882a593Smuzhiyun case AS3722_REGULATOR_ID_LDO0:
680*4882a593Smuzhiyun if (reg_config->ext_control)
681*4882a593Smuzhiyun ops = &as3722_ldo0_extcntrl_ops;
682*4882a593Smuzhiyun else
683*4882a593Smuzhiyun ops = &as3722_ldo0_ops;
684*4882a593Smuzhiyun desc->min_uV = 825000;
685*4882a593Smuzhiyun desc->uV_step = 25000;
686*4882a593Smuzhiyun desc->linear_min_sel = 1;
687*4882a593Smuzhiyun desc->enable_time = 500;
688*4882a593Smuzhiyun desc->curr_table = as3722_ldo_current;
689*4882a593Smuzhiyun desc->n_current_limits = ARRAY_SIZE(as3722_ldo_current);
690*4882a593Smuzhiyun desc->csel_reg = as3722_reg_lookup[id].vsel_reg;
691*4882a593Smuzhiyun desc->csel_mask = AS3722_LDO_ILIMIT_MASK;
692*4882a593Smuzhiyun break;
693*4882a593Smuzhiyun case AS3722_REGULATOR_ID_LDO3:
694*4882a593Smuzhiyun if (reg_config->ext_control)
695*4882a593Smuzhiyun ops = &as3722_ldo3_extcntrl_ops;
696*4882a593Smuzhiyun else
697*4882a593Smuzhiyun ops = &as3722_ldo3_ops;
698*4882a593Smuzhiyun desc->min_uV = 620000;
699*4882a593Smuzhiyun desc->uV_step = 20000;
700*4882a593Smuzhiyun desc->linear_min_sel = 1;
701*4882a593Smuzhiyun desc->enable_time = 500;
702*4882a593Smuzhiyun if (reg_config->enable_tracking) {
703*4882a593Smuzhiyun ret = as3722_ldo3_set_tracking_mode(as3722_regs,
704*4882a593Smuzhiyun id, AS3722_LDO3_MODE_PMOS_TRACKING);
705*4882a593Smuzhiyun if (ret < 0) {
706*4882a593Smuzhiyun dev_err(&pdev->dev,
707*4882a593Smuzhiyun "LDO3 tracking failed: %d\n",
708*4882a593Smuzhiyun ret);
709*4882a593Smuzhiyun return ret;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun break;
713*4882a593Smuzhiyun case AS3722_REGULATOR_ID_LDO6:
714*4882a593Smuzhiyun if (reg_config->ext_control)
715*4882a593Smuzhiyun ops = &as3722_ldo6_extcntrl_ops;
716*4882a593Smuzhiyun else
717*4882a593Smuzhiyun ops = &as3722_ldo6_ops;
718*4882a593Smuzhiyun desc->enable_time = 500;
719*4882a593Smuzhiyun desc->bypass_reg = AS3722_LDO6_VOLTAGE_REG;
720*4882a593Smuzhiyun desc->bypass_mask = AS3722_LDO_VSEL_MASK;
721*4882a593Smuzhiyun desc->bypass_val_on = AS3722_LDO6_VSEL_BYPASS;
722*4882a593Smuzhiyun desc->bypass_val_off = AS3722_LDO6_VSEL_BYPASS;
723*4882a593Smuzhiyun desc->linear_ranges = as3722_ldo_ranges;
724*4882a593Smuzhiyun desc->n_linear_ranges = ARRAY_SIZE(as3722_ldo_ranges);
725*4882a593Smuzhiyun desc->curr_table = as3722_ldo_current;
726*4882a593Smuzhiyun desc->n_current_limits = ARRAY_SIZE(as3722_ldo_current);
727*4882a593Smuzhiyun desc->csel_reg = as3722_reg_lookup[id].vsel_reg;
728*4882a593Smuzhiyun desc->csel_mask = AS3722_LDO_ILIMIT_MASK;
729*4882a593Smuzhiyun break;
730*4882a593Smuzhiyun case AS3722_REGULATOR_ID_SD0:
731*4882a593Smuzhiyun case AS3722_REGULATOR_ID_SD1:
732*4882a593Smuzhiyun case AS3722_REGULATOR_ID_SD6:
733*4882a593Smuzhiyun if (reg_config->ext_control)
734*4882a593Smuzhiyun ops = &as3722_sd016_extcntrl_ops;
735*4882a593Smuzhiyun else
736*4882a593Smuzhiyun ops = &as3722_sd016_ops;
737*4882a593Smuzhiyun if (id == AS3722_REGULATOR_ID_SD0 &&
738*4882a593Smuzhiyun as3722_sd0_is_low_voltage(as3722_regs)) {
739*4882a593Smuzhiyun as3722_regs->desc[id].n_voltages =
740*4882a593Smuzhiyun AS3722_SD0_VSEL_LOW_VOL_MAX + 1;
741*4882a593Smuzhiyun as3722_regs->desc[id].min_uV = 410000;
742*4882a593Smuzhiyun } else {
743*4882a593Smuzhiyun as3722_regs->desc[id].n_voltages =
744*4882a593Smuzhiyun AS3722_SD0_VSEL_MAX + 1;
745*4882a593Smuzhiyun as3722_regs->desc[id].min_uV = 610000;
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun desc->uV_step = 10000;
748*4882a593Smuzhiyun desc->linear_min_sel = 1;
749*4882a593Smuzhiyun desc->enable_time = 600;
750*4882a593Smuzhiyun desc->curr_table = as3722_sd016_current;
751*4882a593Smuzhiyun desc->n_current_limits =
752*4882a593Smuzhiyun ARRAY_SIZE(as3722_sd016_current);
753*4882a593Smuzhiyun if (id == AS3722_REGULATOR_ID_SD0) {
754*4882a593Smuzhiyun desc->csel_reg = AS3722_OVCURRENT_REG;
755*4882a593Smuzhiyun desc->csel_mask =
756*4882a593Smuzhiyun AS3722_OVCURRENT_SD0_TRIP_MASK;
757*4882a593Smuzhiyun } else if (id == AS3722_REGULATOR_ID_SD1) {
758*4882a593Smuzhiyun desc->csel_reg = AS3722_OVCURRENT_REG;
759*4882a593Smuzhiyun desc->csel_mask =
760*4882a593Smuzhiyun AS3722_OVCURRENT_SD1_TRIP_MASK;
761*4882a593Smuzhiyun } else if (id == AS3722_REGULATOR_ID_SD6) {
762*4882a593Smuzhiyun desc->csel_reg = AS3722_OVCURRENT_DEB_REG;
763*4882a593Smuzhiyun desc->csel_mask =
764*4882a593Smuzhiyun AS3722_OVCURRENT_SD6_TRIP_MASK;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun break;
767*4882a593Smuzhiyun case AS3722_REGULATOR_ID_SD2:
768*4882a593Smuzhiyun case AS3722_REGULATOR_ID_SD3:
769*4882a593Smuzhiyun case AS3722_REGULATOR_ID_SD4:
770*4882a593Smuzhiyun case AS3722_REGULATOR_ID_SD5:
771*4882a593Smuzhiyun if (reg_config->ext_control)
772*4882a593Smuzhiyun ops = &as3722_sd2345_extcntrl_ops;
773*4882a593Smuzhiyun else
774*4882a593Smuzhiyun ops = &as3722_sd2345_ops;
775*4882a593Smuzhiyun desc->linear_ranges = as3722_sd2345_ranges;
776*4882a593Smuzhiyun desc->n_linear_ranges =
777*4882a593Smuzhiyun ARRAY_SIZE(as3722_sd2345_ranges);
778*4882a593Smuzhiyun break;
779*4882a593Smuzhiyun default:
780*4882a593Smuzhiyun if (reg_config->ext_control)
781*4882a593Smuzhiyun ops = &as3722_ldo_extcntrl_ops;
782*4882a593Smuzhiyun else
783*4882a593Smuzhiyun ops = &as3722_ldo_ops;
784*4882a593Smuzhiyun desc->enable_time = 500;
785*4882a593Smuzhiyun desc->linear_ranges = as3722_ldo_ranges;
786*4882a593Smuzhiyun desc->n_linear_ranges = ARRAY_SIZE(as3722_ldo_ranges);
787*4882a593Smuzhiyun desc->curr_table = as3722_ldo_current;
788*4882a593Smuzhiyun desc->n_current_limits = ARRAY_SIZE(as3722_ldo_current);
789*4882a593Smuzhiyun desc->csel_reg = as3722_reg_lookup[id].vsel_reg;
790*4882a593Smuzhiyun desc->csel_mask = AS3722_LDO_ILIMIT_MASK;
791*4882a593Smuzhiyun break;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun desc->ops = ops;
794*4882a593Smuzhiyun config.init_data = reg_config->reg_init;
795*4882a593Smuzhiyun config.of_node = as3722_regulator_matches[id].of_node;
796*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev, desc, &config);
797*4882a593Smuzhiyun if (IS_ERR(rdev)) {
798*4882a593Smuzhiyun ret = PTR_ERR(rdev);
799*4882a593Smuzhiyun dev_err(&pdev->dev, "regulator %d register failed %d\n",
800*4882a593Smuzhiyun id, ret);
801*4882a593Smuzhiyun return ret;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun if (reg_config->ext_control) {
805*4882a593Smuzhiyun ret = regulator_enable_regmap(rdev);
806*4882a593Smuzhiyun if (ret < 0) {
807*4882a593Smuzhiyun dev_err(&pdev->dev,
808*4882a593Smuzhiyun "Regulator %d enable failed: %d\n",
809*4882a593Smuzhiyun id, ret);
810*4882a593Smuzhiyun return ret;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun ret = as3722_extreg_init(as3722_regs, id,
813*4882a593Smuzhiyun reg_config->ext_control);
814*4882a593Smuzhiyun if (ret < 0) {
815*4882a593Smuzhiyun dev_err(&pdev->dev,
816*4882a593Smuzhiyun "AS3722 ext control failed: %d", ret);
817*4882a593Smuzhiyun return ret;
818*4882a593Smuzhiyun }
819*4882a593Smuzhiyun }
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun return 0;
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun static const struct of_device_id of_as3722_regulator_match[] = {
825*4882a593Smuzhiyun { .compatible = "ams,as3722-regulator", },
826*4882a593Smuzhiyun {},
827*4882a593Smuzhiyun };
828*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_as3722_regulator_match);
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun static struct platform_driver as3722_regulator_driver = {
831*4882a593Smuzhiyun .driver = {
832*4882a593Smuzhiyun .name = "as3722-regulator",
833*4882a593Smuzhiyun .of_match_table = of_as3722_regulator_match,
834*4882a593Smuzhiyun },
835*4882a593Smuzhiyun .probe = as3722_regulator_probe,
836*4882a593Smuzhiyun };
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun module_platform_driver(as3722_regulator_driver);
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun MODULE_ALIAS("platform:as3722-regulator");
841*4882a593Smuzhiyun MODULE_DESCRIPTION("AS3722 regulator driver");
842*4882a593Smuzhiyun MODULE_AUTHOR("Florian Lobmaier <florian.lobmaier@ams.com>");
843*4882a593Smuzhiyun MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
844*4882a593Smuzhiyun MODULE_LICENSE("GPL");
845