1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * RapidIO Tsi568 switch support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2009-2010 Integrated Device Technology, Inc.
6*4882a593Smuzhiyun * Alexandre Bounine <alexandre.bounine@idt.com>
7*4882a593Smuzhiyun * - Added EM support
8*4882a593Smuzhiyun * - Modified switch operations initialization.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright 2005 MontaVista Software, Inc.
11*4882a593Smuzhiyun * Matt Porter <mporter@kernel.crashing.org>
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/rio.h>
15*4882a593Smuzhiyun #include <linux/rio_drv.h>
16*4882a593Smuzhiyun #include <linux/rio_ids.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include "../rio.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Global (broadcast) route registers */
22*4882a593Smuzhiyun #define SPBC_ROUTE_CFG_DESTID 0x10070
23*4882a593Smuzhiyun #define SPBC_ROUTE_CFG_PORT 0x10074
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Per port route registers */
26*4882a593Smuzhiyun #define SPP_ROUTE_CFG_DESTID(n) (0x11070 + 0x100*n)
27*4882a593Smuzhiyun #define SPP_ROUTE_CFG_PORT(n) (0x11074 + 0x100*n)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define TSI568_SP_MODE(n) (0x11004 + 0x100*n)
30*4882a593Smuzhiyun #define TSI568_SP_MODE_PW_DIS 0x08000000
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static int
tsi568_route_add_entry(struct rio_mport * mport,u16 destid,u8 hopcount,u16 table,u16 route_destid,u8 route_port)33*4882a593Smuzhiyun tsi568_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
34*4882a593Smuzhiyun u16 table, u16 route_destid, u8 route_port)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun if (table == RIO_GLOBAL_TABLE) {
37*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
38*4882a593Smuzhiyun SPBC_ROUTE_CFG_DESTID, route_destid);
39*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
40*4882a593Smuzhiyun SPBC_ROUTE_CFG_PORT, route_port);
41*4882a593Smuzhiyun } else {
42*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
43*4882a593Smuzhiyun SPP_ROUTE_CFG_DESTID(table),
44*4882a593Smuzhiyun route_destid);
45*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
46*4882a593Smuzhiyun SPP_ROUTE_CFG_PORT(table), route_port);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun udelay(10);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static int
tsi568_route_get_entry(struct rio_mport * mport,u16 destid,u8 hopcount,u16 table,u16 route_destid,u8 * route_port)55*4882a593Smuzhiyun tsi568_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
56*4882a593Smuzhiyun u16 table, u16 route_destid, u8 *route_port)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun int ret = 0;
59*4882a593Smuzhiyun u32 result;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun if (table == RIO_GLOBAL_TABLE) {
62*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
63*4882a593Smuzhiyun SPBC_ROUTE_CFG_DESTID, route_destid);
64*4882a593Smuzhiyun rio_mport_read_config_32(mport, destid, hopcount,
65*4882a593Smuzhiyun SPBC_ROUTE_CFG_PORT, &result);
66*4882a593Smuzhiyun } else {
67*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
68*4882a593Smuzhiyun SPP_ROUTE_CFG_DESTID(table),
69*4882a593Smuzhiyun route_destid);
70*4882a593Smuzhiyun rio_mport_read_config_32(mport, destid, hopcount,
71*4882a593Smuzhiyun SPP_ROUTE_CFG_PORT(table), &result);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun *route_port = result;
75*4882a593Smuzhiyun if (*route_port > 15)
76*4882a593Smuzhiyun ret = -1;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return ret;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static int
tsi568_route_clr_table(struct rio_mport * mport,u16 destid,u8 hopcount,u16 table)82*4882a593Smuzhiyun tsi568_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
83*4882a593Smuzhiyun u16 table)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun u32 route_idx;
86*4882a593Smuzhiyun u32 lut_size;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun lut_size = (mport->sys_size) ? 0x1ff : 0xff;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (table == RIO_GLOBAL_TABLE) {
91*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
92*4882a593Smuzhiyun SPBC_ROUTE_CFG_DESTID, 0x80000000);
93*4882a593Smuzhiyun for (route_idx = 0; route_idx <= lut_size; route_idx++)
94*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
95*4882a593Smuzhiyun SPBC_ROUTE_CFG_PORT,
96*4882a593Smuzhiyun RIO_INVALID_ROUTE);
97*4882a593Smuzhiyun } else {
98*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
99*4882a593Smuzhiyun SPP_ROUTE_CFG_DESTID(table),
100*4882a593Smuzhiyun 0x80000000);
101*4882a593Smuzhiyun for (route_idx = 0; route_idx <= lut_size; route_idx++)
102*4882a593Smuzhiyun rio_mport_write_config_32(mport, destid, hopcount,
103*4882a593Smuzhiyun SPP_ROUTE_CFG_PORT(table),
104*4882a593Smuzhiyun RIO_INVALID_ROUTE);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static int
tsi568_em_init(struct rio_dev * rdev)111*4882a593Smuzhiyun tsi568_em_init(struct rio_dev *rdev)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun u32 regval;
114*4882a593Smuzhiyun int portnum;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun pr_debug("TSI568 %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* Make sure that Port-Writes are disabled (for all ports) */
119*4882a593Smuzhiyun for (portnum = 0;
120*4882a593Smuzhiyun portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) {
121*4882a593Smuzhiyun rio_read_config_32(rdev, TSI568_SP_MODE(portnum), ®val);
122*4882a593Smuzhiyun rio_write_config_32(rdev, TSI568_SP_MODE(portnum),
123*4882a593Smuzhiyun regval | TSI568_SP_MODE_PW_DIS);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun static struct rio_switch_ops tsi568_switch_ops = {
130*4882a593Smuzhiyun .owner = THIS_MODULE,
131*4882a593Smuzhiyun .add_entry = tsi568_route_add_entry,
132*4882a593Smuzhiyun .get_entry = tsi568_route_get_entry,
133*4882a593Smuzhiyun .clr_table = tsi568_route_clr_table,
134*4882a593Smuzhiyun .set_domain = NULL,
135*4882a593Smuzhiyun .get_domain = NULL,
136*4882a593Smuzhiyun .em_init = tsi568_em_init,
137*4882a593Smuzhiyun .em_handle = NULL,
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
tsi568_probe(struct rio_dev * rdev,const struct rio_device_id * id)140*4882a593Smuzhiyun static int tsi568_probe(struct rio_dev *rdev, const struct rio_device_id *id)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun spin_lock(&rdev->rswitch->lock);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (rdev->rswitch->ops) {
147*4882a593Smuzhiyun spin_unlock(&rdev->rswitch->lock);
148*4882a593Smuzhiyun return -EINVAL;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun rdev->rswitch->ops = &tsi568_switch_ops;
152*4882a593Smuzhiyun spin_unlock(&rdev->rswitch->lock);
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
tsi568_remove(struct rio_dev * rdev)156*4882a593Smuzhiyun static void tsi568_remove(struct rio_dev *rdev)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
159*4882a593Smuzhiyun spin_lock(&rdev->rswitch->lock);
160*4882a593Smuzhiyun if (rdev->rswitch->ops != &tsi568_switch_ops) {
161*4882a593Smuzhiyun spin_unlock(&rdev->rswitch->lock);
162*4882a593Smuzhiyun return;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun rdev->rswitch->ops = NULL;
165*4882a593Smuzhiyun spin_unlock(&rdev->rswitch->lock);
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun static const struct rio_device_id tsi568_id_table[] = {
169*4882a593Smuzhiyun {RIO_DEVICE(RIO_DID_TSI568, RIO_VID_TUNDRA)},
170*4882a593Smuzhiyun { 0, } /* terminate list */
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun static struct rio_driver tsi568_driver = {
174*4882a593Smuzhiyun .name = "tsi568",
175*4882a593Smuzhiyun .id_table = tsi568_id_table,
176*4882a593Smuzhiyun .probe = tsi568_probe,
177*4882a593Smuzhiyun .remove = tsi568_remove,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
tsi568_init(void)180*4882a593Smuzhiyun static int __init tsi568_init(void)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun return rio_register_driver(&tsi568_driver);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
tsi568_exit(void)185*4882a593Smuzhiyun static void __exit tsi568_exit(void)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun rio_unregister_driver(&tsi568_driver);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun device_initcall(tsi568_init);
191*4882a593Smuzhiyun module_exit(tsi568_exit);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun MODULE_DESCRIPTION("IDT Tsi568 Serial RapidIO switch driver");
194*4882a593Smuzhiyun MODULE_AUTHOR("Integrated Device Technology, Inc.");
195*4882a593Smuzhiyun MODULE_LICENSE("GPL");
196