1 // SPDX-License-Identifier: GPL-2.0
2
3 /*
4 * PWM-I2S driver for Rockchip SoCs
5 *
6 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19
20 /* transmit operation control register */
21 #define I2S_TXCR_FBM_MSB 0
22 #define I2S_TXCR_FBM_LSB BIT(11)
23 #define I2S_TXCR_IBM_NORMAL 0
24 #define I2S_TXCR_IBM_LSJM BIT(9)
25 #define I2S_TXCR_IBM_RSJM BIT(10)
26 #define I2S_TXCR_IBM_MASK GENMASK(10, 9)
27 #define I2S_TXCR_VDW(x) ((x) - 1)
28 #define I2S_TXCR_VDW_MASK GENMASK(4, 0)
29
30 /* clock generation register */
31 #define I2S_CKR_TSD(x) ((x) - 1)
32 #define I2S_CKR_TSD_MASK GENMASK(7, 0)
33
34 /* DMA control register */
35 #define I2S_DMACR_TDE_DISABLE 0
36 #define I2S_DMACR_TDE_ENABLE BIT(8)
37 #define I2S_DMACR_TDL(x) (x)
38 #define I2S_DMACR_TDL_MASK GENMASK(4, 0)
39
40 /* Transfer start register */
41 #define I2S_XFER_TXS_STOP 0
42 #define I2S_XFER_TXS_START BIT(0)
43
44 /* clear SCLK domain logic register */
45 #define I2S_CLR_TXC BIT(0)
46
47 /* Mclk div register */
48 #define I2S_CLKDIV_TXM(x) ((x) - 1)
49
50 /* I2S REGS */
51 #define I2S_TXCR (0x0000)
52 #define I2S_RXCR (0x0004)
53 #define I2S_CKR (0x0008)
54 #define I2S_FIFOLR (0x000c)
55 #define I2S_DMACR (0x0010)
56 #define I2S_INTCR (0x0014)
57 #define I2S_INTSR (0x0018)
58 #define I2S_XFER (0x001c)
59 #define I2S_CLR (0x0020)
60 #define I2S_TXDR (0x0024)
61 #define I2S_RXDR (0x0028)
62 #define I2S_TDM_TXCR (0x0030)
63 #define I2S_TDM_RXCR (0x0034)
64 #define I2S_CLKDIV (0x0038)
65
66 /* Hardware Param */
67 #define I2S_FORMAT_BITS 32
68 #define I2S_CHANNEL_NUM 2
69 #define I2S_FRAME_BITS (I2S_FORMAT_BITS * I2S_CHANNEL_NUM)
70 #define I2S_FRAME_BYTES (I2S_FRAME_BITS / 8)
71 #define I2S_FIFO_WATERMARK_LEVEL 30
72
73 #define I2S_DMA_BUFFER_SIZE 256
74 #define I2S_DMA_BUFFER_FRAME_SIZE (I2S_DMA_BUFFER_SIZE / I2S_FRAME_BYTES)
75
76 struct rockchip_i2s_pwm_dma {
77 struct dma_chan *chan_tx;
78 dma_addr_t tx_addr;
79 char *tx_buff;
80 dma_cookie_t tx_cookie;
81 };
82
83 struct rockchip_i2s_pwm_chip {
84 struct pwm_chip chip;
85 struct clk *hclk;
86 struct clk *mclk;
87 void __iomem *base;
88 struct rockchip_i2s_pwm_dma dma;
89 const struct rockchip_i2s_pwm_data *data;
90
91 struct pwm_state pwm_state;
92 };
93
94 struct rockchip_i2s_pwm_data {
95 unsigned int reg_clkdiv;
96 unsigned int bit_clkdiv;
97 unsigned int mask_clkdiv;
98 };
99
100 static inline
to_rockchip_i2s_pwm_chip(struct pwm_chip * c)101 struct rockchip_i2s_pwm_chip *to_rockchip_i2s_pwm_chip(struct pwm_chip *c)
102 {
103 return container_of(c, struct rockchip_i2s_pwm_chip, chip);
104 }
105
rockchip_i2s_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)106 static void rockchip_i2s_pwm_get_state(struct pwm_chip *chip,
107 struct pwm_device *pwm,
108 struct pwm_state *state)
109 {
110 struct rockchip_i2s_pwm_chip *pc = to_rockchip_i2s_pwm_chip(chip);
111 u32 ctrl;
112 int ret;
113
114 ret = clk_enable(pc->hclk);
115 if (ret)
116 return;
117
118 memcpy(state, &pc->pwm_state, sizeof(struct pwm_state));
119
120 ctrl = readl_relaxed(pc->base + I2S_XFER);
121 if (ctrl & I2S_XFER_TXS_START)
122 state->enabled = true;
123 else
124 state->enabled = false;
125
126 clk_disable(pc->hclk);
127 }
128
rockchip_i2s_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)129 static int rockchip_i2s_pwm_config(struct pwm_chip *chip,
130 struct pwm_device *pwm,
131 struct pwm_state *state)
132 {
133 struct rockchip_i2s_pwm_chip *pc = to_rockchip_i2s_pwm_chip(chip);
134 unsigned long div_bclk;
135 unsigned long flags;
136 u64 mclk_rate, period_div, duty, duty_div;
137 unsigned int div_val;
138 int ret, i;
139
140 ret = clk_enable(pc->hclk);
141 if (ret)
142 return ret;
143 /*
144 * Assume the time of a frame is a period of pwm, so a frame is the unit
145 * of the pwm, we have to config the buffer per frame.
146 */
147 mclk_rate = clk_get_rate(pc->mclk);
148 period_div = mclk_rate * state->period;
149 div_bclk = DIV_ROUND_CLOSEST(period_div, I2S_FRAME_BITS * NSEC_PER_SEC);
150
151 /*
152 * The duty pecent is equal to the bits percent at whole frame, as the
153 * time of a frame is a period.
154 */
155 duty_div = DIV_ROUND_CLOSEST(I2S_FRAME_BITS * state->duty_cycle,
156 state->period);
157 if (duty_div > 0)
158 duty = GENMASK_ULL(duty_div - 1, 0);
159 else
160 duty = 0;
161
162 if (state->polarity == PWM_POLARITY_INVERSED)
163 duty = ~duty;
164
165 local_irq_save(flags);
166
167 div_val = readl_relaxed(pc->base + pc->data->reg_clkdiv);
168 div_val &= ~pc->data->mask_clkdiv;
169 writel_relaxed((I2S_CLKDIV_TXM(div_bclk) << pc->data->bit_clkdiv)
170 | div_val, pc->base + pc->data->reg_clkdiv);
171
172 for (i = 0; i < I2S_DMA_BUFFER_FRAME_SIZE; i++)
173 memcpy((u64 *)pc->dma.tx_buff + i, &duty, sizeof(u64));
174
175 pc->pwm_state.period = state->period;
176 pc->pwm_state.duty_cycle = state->duty_cycle;
177 pc->pwm_state.polarity = state->polarity;
178
179 local_irq_restore(flags);
180 clk_disable(pc->hclk);
181
182 return ret;
183 }
184
rockchip_i2s_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm,bool enable)185 static int rockchip_i2s_pwm_enable(struct pwm_chip *chip,
186 struct pwm_device *pwm,
187 bool enable)
188 {
189 struct rockchip_i2s_pwm_chip *pc = to_rockchip_i2s_pwm_chip(chip);
190 struct rockchip_i2s_pwm_dma *dma = &pc->dma;
191 struct dma_async_tx_descriptor *tx_desc;
192 int ret, retry = 10;
193 u32 val;
194
195 if (enable) {
196 ret = clk_enable(pc->hclk);
197 if (ret)
198 return ret;
199
200 ret = clk_enable(pc->mclk);
201 if (ret)
202 goto err_mclk;
203
204 tx_desc = dmaengine_prep_dma_cyclic(dma->chan_tx, dma->tx_addr,
205 I2S_DMA_BUFFER_SIZE,
206 I2S_DMA_BUFFER_SIZE,
207 DMA_MEM_TO_DEV,
208 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
209 if (!tx_desc) {
210 dev_err(chip->dev, "Not able to get tx desc for DMA\n");
211 ret = -EBUSY;
212 goto out;
213 }
214
215 tx_desc->callback = NULL;
216 tx_desc->callback_param = NULL;
217 dma->tx_cookie = dmaengine_submit(tx_desc);
218 ret = dma_submit_error(dma->tx_cookie);
219 if (ret) {
220 dev_err(chip->dev, "DMA submit failed\n");
221 goto out;
222 }
223
224 dma_async_issue_pending(pc->dma.chan_tx);
225
226 val = readl_relaxed(pc->base + I2S_DMACR);
227 val &= ~I2S_DMACR_TDE_ENABLE;
228 writel_relaxed(val | I2S_DMACR_TDE_ENABLE,
229 pc->base + I2S_DMACR);
230
231 val = readl_relaxed(pc->base + I2S_XFER);
232 val &= ~I2S_XFER_TXS_START;
233 writel_relaxed(val | I2S_XFER_TXS_START, pc->base + I2S_XFER);
234 } else {
235 dmaengine_terminate_all(pc->dma.chan_tx);
236
237 val = readl_relaxed(pc->base + I2S_DMACR);
238 val &= ~I2S_DMACR_TDE_ENABLE;
239 writel_relaxed(val | I2S_DMACR_TDE_DISABLE,
240 pc->base + I2S_DMACR);
241
242 val = readl_relaxed(pc->base + I2S_XFER);
243 val &= ~I2S_XFER_TXS_START;
244 writel_relaxed(val | I2S_XFER_TXS_STOP, pc->base + I2S_XFER);
245
246 usleep_range(100, 150);
247
248 val = readl_relaxed(pc->base + I2S_CLR);
249 val &= ~I2S_CLR_TXC;
250 writel_relaxed(val | I2S_CLR_TXC, pc->base + I2S_CLR);
251
252 /* Should wait for clear operation to finish */
253 do {
254 val = readl_relaxed(pc->base + I2S_CLR);
255 if (val)
256 break;
257 } while (--retry);
258
259 if (!retry)
260 dev_warn(chip->dev, "fail to clear\n");
261
262 clk_disable(pc->mclk);
263 clk_disable(pc->hclk);
264 }
265
266 return 0;
267
268 out:
269 clk_disable(pc->mclk);
270 err_mclk:
271 clk_disable(pc->hclk);
272
273 return ret;
274 }
275
rockchip_i2s_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)276 static int rockchip_i2s_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
277 struct pwm_state *state)
278 {
279 struct pwm_state curstate;
280 bool enabled;
281 int ret;
282
283 pwm_get_state(pwm, &curstate);
284 enabled = curstate.enabled;
285
286 ret = rockchip_i2s_pwm_config(chip, pwm, state);
287 if (ret)
288 return ret;
289
290 if (state->enabled != enabled) {
291 ret = rockchip_i2s_pwm_enable(chip, pwm, state->enabled);
292 if (ret)
293 return ret;
294 }
295
296 rockchip_i2s_pwm_get_state(chip, pwm, state);
297
298 return 0;
299 }
300
301 static const struct pwm_ops rockchip_i2s_pwm_ops = {
302 .get_state = rockchip_i2s_pwm_get_state,
303 .apply = rockchip_i2s_pwm_apply,
304 .owner = THIS_MODULE,
305 };
306
rockchip_i2s_pwm_dma_request(struct rockchip_i2s_pwm_chip * pc,struct device * dev,dma_addr_t phy_addr)307 static int rockchip_i2s_pwm_dma_request(struct rockchip_i2s_pwm_chip *pc,
308 struct device *dev,
309 dma_addr_t phy_addr)
310 {
311 struct rockchip_i2s_pwm_dma *dma = &pc->dma;
312 struct dma_slave_config dma_sconfig;
313 int ret;
314
315 memset(&dma_sconfig, 0, sizeof(dma_sconfig));
316
317 dma->chan_tx = dma_request_slave_channel(dev, "tx");
318 if (!dma->chan_tx) {
319 dev_err(dev, "can't request DMA tx channel\n");
320 return -ENODEV;
321 }
322
323 dma_sconfig.direction = DMA_MEM_TO_DEV;
324 dma_sconfig.dst_addr = phy_addr;
325 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
326 dma_sconfig.dst_maxburst = 2;
327
328 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
329 if (ret < 0) {
330 dev_err(dev, "can't configure tx channel\n");
331 goto fail;
332 }
333
334 dma->tx_buff = dma_alloc_coherent(dev, I2S_DMA_BUFFER_SIZE,
335 &dma->tx_addr, GFP_KERNEL);
336 if (!dma->tx_buff) {
337 ret = -ENOMEM;
338 goto fail;
339 }
340
341 return 0;
342 fail:
343 dma_release_channel(dma->chan_tx);
344 return ret;
345 }
346
rockchip_i2s_pwm_dma_release(struct rockchip_i2s_pwm_chip * pc)347 static void rockchip_i2s_pwm_dma_release(struct rockchip_i2s_pwm_chip *pc)
348 {
349 struct rockchip_i2s_pwm_dma *dma = &pc->dma;
350 struct device *dev = pc->chip.dev;
351
352 dma_free_coherent(dev, I2S_DMA_BUFFER_SIZE, dma->tx_buff, dma->tx_addr);
353 dma_release_channel(dma->chan_tx);
354 }
355
rockchip_i2s_pwm_hw_params(struct rockchip_i2s_pwm_chip * pc)356 static int rockchip_i2s_pwm_hw_params(struct rockchip_i2s_pwm_chip *pc)
357 {
358 unsigned int val = 0;
359 int ret;
360
361 ret = clk_enable(pc->hclk);
362 if (ret)
363 return ret;
364
365 /* Config tx format bits with 32, LSB, left justified. */
366 val = readl_relaxed(pc->base + I2S_TXCR);
367 val &= ~(I2S_TXCR_VDW_MASK | I2S_TXCR_IBM_MASK | I2S_TXCR_FBM_LSB);
368 writel_relaxed(val | I2S_TXCR_VDW(I2S_FORMAT_BITS) | I2S_TXCR_IBM_LSJM
369 | I2S_TXCR_FBM_LSB, pc->base + I2S_TXCR);
370
371 val = readl_relaxed(pc->base + I2S_CKR);
372 val &= ~I2S_CKR_TSD_MASK;
373 writel_relaxed(val | I2S_CKR_TSD(I2S_FRAME_BITS), pc->base + I2S_CKR);
374
375 /* Config the tx fifo watermark level to 30. */
376 val = readl_relaxed(pc->base + I2S_DMACR);
377 val &= ~I2S_DMACR_TDL_MASK;
378 writel_relaxed(val | I2S_DMACR_TDL(I2S_FIFO_WATERMARK_LEVEL),
379 pc->base + I2S_DMACR);
380
381 clk_disable(pc->hclk);
382 return 0;
383 }
384
385 static const struct rockchip_i2s_pwm_data i2s_pwm_data_v1 = {
386 .reg_clkdiv = 0x8,
387 .bit_clkdiv = 16,
388 .mask_clkdiv = GENMASK(23, 16),
389 };
390
391 static const struct rockchip_i2s_pwm_data i2s_pwm_data_v2 = {
392 .reg_clkdiv = 0x38,
393 .bit_clkdiv = 0,
394 .mask_clkdiv = GENMASK(7, 0),
395 };
396
397 static const struct of_device_id rockchip_i2s_pwm_match[] = {
398 { .compatible = "rockchip,i2s-pwm", .data = &i2s_pwm_data_v1 },
399 { .compatible = "rockchip,rk3308-i2s-pwm", .data = &i2s_pwm_data_v2 },
400 { /* sentinel */ },
401 };
402
rockchip_i2s_pwm_probe(struct platform_device * pdev)403 static int rockchip_i2s_pwm_probe(struct platform_device *pdev)
404 {
405 struct rockchip_i2s_pwm_chip *pc;
406 const struct of_device_id *id;
407 struct resource *res;
408 int ret;
409
410 id = of_match_device(rockchip_i2s_pwm_match, &pdev->dev);
411 if (!id)
412 return -EINVAL;
413
414 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
415 if (!pc)
416 return -ENOMEM;
417
418 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
419 pc->base = devm_ioremap_resource(&pdev->dev, res);
420 if (IS_ERR(pc->base))
421 return PTR_ERR(pc->base);
422
423 pc->hclk = devm_clk_get(&pdev->dev, "hclk");
424 if (IS_ERR(pc->hclk))
425 return PTR_ERR(pc->hclk);
426
427 pc->mclk = devm_clk_get(&pdev->dev, "mclk");
428 if (IS_ERR(pc->mclk))
429 return PTR_ERR(pc->mclk);
430
431 ret = clk_prepare(pc->hclk);
432 if (ret)
433 return ret;
434
435 ret = clk_prepare(pc->mclk);
436 if (ret)
437 goto err_hclk;
438
439 pc->chip.dev = &pdev->dev;
440 platform_set_drvdata(pdev, pc);
441
442 ret = rockchip_i2s_pwm_hw_params(pc);
443 if (ret)
444 goto err_mclk;
445
446 ret = rockchip_i2s_pwm_dma_request(pc, &pdev->dev,
447 res->start + I2S_TXDR);
448 if (ret) {
449 ret = -EPROBE_DEFER;
450 goto err_mclk;
451 }
452
453 pc->data = id->data;
454 pc->chip.ops = &rockchip_i2s_pwm_ops;
455 pc->chip.base = -1;
456 pc->chip.npwm = 1;
457 pc->chip.of_xlate = of_pwm_xlate_with_flags;
458 pc->chip.of_pwm_n_cells = 3;
459
460 ret = pwmchip_add(&pc->chip);
461 if (ret < 0) {
462 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
463 rockchip_i2s_pwm_dma_release(pc);
464 goto err_mclk;
465 }
466
467 return 0;
468
469 err_mclk:
470 clk_unprepare(pc->mclk);
471 err_hclk:
472 clk_unprepare(pc->hclk);
473
474 return ret;
475 }
476
rockchip_i2s_pwm_remove(struct platform_device * pdev)477 static int rockchip_i2s_pwm_remove(struct platform_device *pdev)
478 {
479 struct rockchip_i2s_pwm_chip *pc = platform_get_drvdata(pdev);
480 struct pwm_state curstate;
481
482 pwm_get_state(pc->chip.pwms, &curstate);
483 if (curstate.enabled)
484 dmaengine_terminate_all(pc->dma.chan_tx);
485
486 rockchip_i2s_pwm_dma_release(pc);
487
488 clk_unprepare(pc->mclk);
489 clk_unprepare(pc->hclk);
490
491 return pwmchip_remove(&pc->chip);
492 }
493
494 static struct platform_driver rockchip_i2s_pwm_driver = {
495 .driver = {
496 .name = "rockchip-i2s-pwm",
497 .of_match_table = rockchip_i2s_pwm_match,
498 },
499 .probe = rockchip_i2s_pwm_probe,
500 .remove = rockchip_i2s_pwm_remove,
501 };
502 module_platform_driver(rockchip_i2s_pwm_driver);
503
504 MODULE_AUTHOR("David Wu <david.wu@rock-chip.com>");
505 MODULE_DESCRIPTION("ROCKCHIP I2S PWM driver");
506 MODULE_LICENSE("GPL v2");
507