xref: /OK3568_Linux_fs/kernel/drivers/pwm/pwm-rcar.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * R-Car PWM Timer driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2015 Renesas Electronics Corporation
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Limitations:
8*4882a593Smuzhiyun  * - The hardware cannot generate a 0% duty cycle.
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/log2.h>
15*4882a593Smuzhiyun #include <linux/math64.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/pm_runtime.h>
20*4882a593Smuzhiyun #include <linux/pwm.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define RCAR_PWM_MAX_DIVISION	24
24*4882a593Smuzhiyun #define RCAR_PWM_MAX_CYCLE	1023
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define RCAR_PWMCR		0x00
27*4882a593Smuzhiyun #define  RCAR_PWMCR_CC0_MASK	0x000f0000
28*4882a593Smuzhiyun #define  RCAR_PWMCR_CC0_SHIFT	16
29*4882a593Smuzhiyun #define  RCAR_PWMCR_CCMD	BIT(15)
30*4882a593Smuzhiyun #define  RCAR_PWMCR_SYNC	BIT(11)
31*4882a593Smuzhiyun #define  RCAR_PWMCR_SS0		BIT(4)
32*4882a593Smuzhiyun #define  RCAR_PWMCR_EN0		BIT(0)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define RCAR_PWMCNT		0x04
35*4882a593Smuzhiyun #define  RCAR_PWMCNT_CYC0_MASK	0x03ff0000
36*4882a593Smuzhiyun #define  RCAR_PWMCNT_CYC0_SHIFT	16
37*4882a593Smuzhiyun #define  RCAR_PWMCNT_PH0_MASK	0x000003ff
38*4882a593Smuzhiyun #define  RCAR_PWMCNT_PH0_SHIFT	0
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun struct rcar_pwm_chip {
41*4882a593Smuzhiyun 	struct pwm_chip chip;
42*4882a593Smuzhiyun 	void __iomem *base;
43*4882a593Smuzhiyun 	struct clk *clk;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
to_rcar_pwm_chip(struct pwm_chip * chip)46*4882a593Smuzhiyun static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	return container_of(chip, struct rcar_pwm_chip, chip);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
rcar_pwm_write(struct rcar_pwm_chip * rp,u32 data,unsigned int offset)51*4882a593Smuzhiyun static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
52*4882a593Smuzhiyun 			   unsigned int offset)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun 	writel(data, rp->base + offset);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun 
rcar_pwm_read(struct rcar_pwm_chip * rp,unsigned int offset)57*4882a593Smuzhiyun static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	return readl(rp->base + offset);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
rcar_pwm_update(struct rcar_pwm_chip * rp,u32 mask,u32 data,unsigned int offset)62*4882a593Smuzhiyun static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
63*4882a593Smuzhiyun 			    unsigned int offset)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	u32 value;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	value = rcar_pwm_read(rp, offset);
68*4882a593Smuzhiyun 	value &= ~mask;
69*4882a593Smuzhiyun 	value |= data & mask;
70*4882a593Smuzhiyun 	rcar_pwm_write(rp, value, offset);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
rcar_pwm_get_clock_division(struct rcar_pwm_chip * rp,int period_ns)73*4882a593Smuzhiyun static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	unsigned long clk_rate = clk_get_rate(rp->clk);
76*4882a593Smuzhiyun 	u64 div, tmp;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	if (clk_rate == 0)
79*4882a593Smuzhiyun 		return -EINVAL;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
82*4882a593Smuzhiyun 	tmp = (u64)period_ns * clk_rate + div - 1;
83*4882a593Smuzhiyun 	tmp = div64_u64(tmp, div);
84*4882a593Smuzhiyun 	div = ilog2(tmp - 1) + 1;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
rcar_pwm_set_clock_control(struct rcar_pwm_chip * rp,unsigned int div)89*4882a593Smuzhiyun static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
90*4882a593Smuzhiyun 				       unsigned int div)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	u32 value;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	value = rcar_pwm_read(rp, RCAR_PWMCR);
95*4882a593Smuzhiyun 	value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	if (div & 1)
98*4882a593Smuzhiyun 		value |= RCAR_PWMCR_CCMD;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	div >>= 1;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	value |= div << RCAR_PWMCR_CC0_SHIFT;
103*4882a593Smuzhiyun 	rcar_pwm_write(rp, value, RCAR_PWMCR);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
rcar_pwm_set_counter(struct rcar_pwm_chip * rp,int div,int duty_ns,int period_ns)106*4882a593Smuzhiyun static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
107*4882a593Smuzhiyun 				int period_ns)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	unsigned long long one_cycle, tmp;	/* 0.01 nanoseconds */
110*4882a593Smuzhiyun 	unsigned long clk_rate = clk_get_rate(rp->clk);
111*4882a593Smuzhiyun 	u32 cyc, ph;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div);
114*4882a593Smuzhiyun 	do_div(one_cycle, clk_rate);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	tmp = period_ns * 100ULL;
117*4882a593Smuzhiyun 	do_div(tmp, one_cycle);
118*4882a593Smuzhiyun 	cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	tmp = duty_ns * 100ULL;
121*4882a593Smuzhiyun 	do_div(tmp, one_cycle);
122*4882a593Smuzhiyun 	ph = tmp & RCAR_PWMCNT_PH0_MASK;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* Avoid prohibited setting */
125*4882a593Smuzhiyun 	if (cyc == 0 || ph == 0)
126*4882a593Smuzhiyun 		return -EINVAL;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
rcar_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)133*4882a593Smuzhiyun static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	return pm_runtime_get_sync(chip->dev);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
rcar_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)138*4882a593Smuzhiyun static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	pm_runtime_put(chip->dev);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
rcar_pwm_enable(struct rcar_pwm_chip * rp)143*4882a593Smuzhiyun static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	u32 value;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/* Don't enable the PWM device if CYC0 or PH0 is 0 */
148*4882a593Smuzhiyun 	value = rcar_pwm_read(rp, RCAR_PWMCNT);
149*4882a593Smuzhiyun 	if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
150*4882a593Smuzhiyun 	    (value & RCAR_PWMCNT_PH0_MASK) == 0)
151*4882a593Smuzhiyun 		return -EINVAL;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun 
rcar_pwm_disable(struct rcar_pwm_chip * rp)158*4882a593Smuzhiyun static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
rcar_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)163*4882a593Smuzhiyun static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
164*4882a593Smuzhiyun 			  const struct pwm_state *state)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
167*4882a593Smuzhiyun 	int div, ret;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	/* This HW/driver only supports normal polarity */
170*4882a593Smuzhiyun 	if (state->polarity != PWM_POLARITY_NORMAL)
171*4882a593Smuzhiyun 		return -ENOTSUPP;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	if (!state->enabled) {
174*4882a593Smuzhiyun 		rcar_pwm_disable(rp);
175*4882a593Smuzhiyun 		return 0;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	div = rcar_pwm_get_clock_division(rp, state->period);
179*4882a593Smuzhiyun 	if (div < 0)
180*4882a593Smuzhiyun 		return div;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
185*4882a593Smuzhiyun 	if (!ret)
186*4882a593Smuzhiyun 		rcar_pwm_set_clock_control(rp, div);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	/* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
189*4882a593Smuzhiyun 	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	if (!ret)
192*4882a593Smuzhiyun 		ret = rcar_pwm_enable(rp);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	return ret;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun static const struct pwm_ops rcar_pwm_ops = {
198*4882a593Smuzhiyun 	.request = rcar_pwm_request,
199*4882a593Smuzhiyun 	.free = rcar_pwm_free,
200*4882a593Smuzhiyun 	.apply = rcar_pwm_apply,
201*4882a593Smuzhiyun 	.owner = THIS_MODULE,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
rcar_pwm_probe(struct platform_device * pdev)204*4882a593Smuzhiyun static int rcar_pwm_probe(struct platform_device *pdev)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	struct rcar_pwm_chip *rcar_pwm;
207*4882a593Smuzhiyun 	struct resource *res;
208*4882a593Smuzhiyun 	int ret;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
211*4882a593Smuzhiyun 	if (rcar_pwm == NULL)
212*4882a593Smuzhiyun 		return -ENOMEM;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215*4882a593Smuzhiyun 	rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res);
216*4882a593Smuzhiyun 	if (IS_ERR(rcar_pwm->base))
217*4882a593Smuzhiyun 		return PTR_ERR(rcar_pwm->base);
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
220*4882a593Smuzhiyun 	if (IS_ERR(rcar_pwm->clk)) {
221*4882a593Smuzhiyun 		dev_err(&pdev->dev, "cannot get clock\n");
222*4882a593Smuzhiyun 		return PTR_ERR(rcar_pwm->clk);
223*4882a593Smuzhiyun 	}
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	platform_set_drvdata(pdev, rcar_pwm);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	rcar_pwm->chip.dev = &pdev->dev;
228*4882a593Smuzhiyun 	rcar_pwm->chip.ops = &rcar_pwm_ops;
229*4882a593Smuzhiyun 	rcar_pwm->chip.base = -1;
230*4882a593Smuzhiyun 	rcar_pwm->chip.npwm = 1;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	ret = pwmchip_add(&rcar_pwm->chip);
235*4882a593Smuzhiyun 	if (ret < 0) {
236*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
237*4882a593Smuzhiyun 		pm_runtime_disable(&pdev->dev);
238*4882a593Smuzhiyun 		return ret;
239*4882a593Smuzhiyun 	}
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	return 0;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun 
rcar_pwm_remove(struct platform_device * pdev)244*4882a593Smuzhiyun static int rcar_pwm_remove(struct platform_device *pdev)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
247*4882a593Smuzhiyun 	int ret;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	ret = pwmchip_remove(&rcar_pwm->chip);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	return ret;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun static const struct of_device_id rcar_pwm_of_table[] = {
257*4882a593Smuzhiyun 	{ .compatible = "renesas,pwm-rcar", },
258*4882a593Smuzhiyun 	{ },
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun static struct platform_driver rcar_pwm_driver = {
263*4882a593Smuzhiyun 	.probe = rcar_pwm_probe,
264*4882a593Smuzhiyun 	.remove = rcar_pwm_remove,
265*4882a593Smuzhiyun 	.driver = {
266*4882a593Smuzhiyun 		.name = "pwm-rcar",
267*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(rcar_pwm_of_table),
268*4882a593Smuzhiyun 	}
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun module_platform_driver(rcar_pwm_driver);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
273*4882a593Smuzhiyun MODULE_DESCRIPTION("Renesas PWM Timer Driver");
274*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
275*4882a593Smuzhiyun MODULE_ALIAS("platform:pwm-rcar");
276