1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Intel Low Power Subsystem PWM controller driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014, Intel Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Derived from the original pwm-lpss.c 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __PWM_LPSS_H 11*4882a593Smuzhiyun #define __PWM_LPSS_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/device.h> 14*4882a593Smuzhiyun #include <linux/pwm.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MAX_PWMS 4 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct pwm_lpss_chip { 19*4882a593Smuzhiyun struct pwm_chip chip; 20*4882a593Smuzhiyun void __iomem *regs; 21*4882a593Smuzhiyun const struct pwm_lpss_boardinfo *info; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct pwm_lpss_boardinfo { 25*4882a593Smuzhiyun unsigned long clk_rate; 26*4882a593Smuzhiyun unsigned int npwm; 27*4882a593Smuzhiyun unsigned long base_unit_bits; 28*4882a593Smuzhiyun bool bypass; 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device 31*4882a593Smuzhiyun * messes with the PWM0 controllers state, 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun bool other_devices_aml_touches_pwm_regs; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, 37*4882a593Smuzhiyun const struct pwm_lpss_boardinfo *info); 38*4882a593Smuzhiyun int pwm_lpss_remove(struct pwm_lpss_chip *lpwm); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __PWM_LPSS_H */ 41