1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel Low Power Subsystem PWM controller PCI driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014, Intel Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Derived from the original pwm-lpss.c
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/pci.h>
13*4882a593Smuzhiyun #include <linux/pm_runtime.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "pwm-lpss.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* BayTrail */
18*4882a593Smuzhiyun static const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
19*4882a593Smuzhiyun .clk_rate = 25000000,
20*4882a593Smuzhiyun .npwm = 1,
21*4882a593Smuzhiyun .base_unit_bits = 16,
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Braswell */
25*4882a593Smuzhiyun static const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
26*4882a593Smuzhiyun .clk_rate = 19200000,
27*4882a593Smuzhiyun .npwm = 1,
28*4882a593Smuzhiyun .base_unit_bits = 16,
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Broxton */
32*4882a593Smuzhiyun static const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
33*4882a593Smuzhiyun .clk_rate = 19200000,
34*4882a593Smuzhiyun .npwm = 4,
35*4882a593Smuzhiyun .base_unit_bits = 22,
36*4882a593Smuzhiyun .bypass = true,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Tangier */
40*4882a593Smuzhiyun static const struct pwm_lpss_boardinfo pwm_lpss_tng_info = {
41*4882a593Smuzhiyun .clk_rate = 19200000,
42*4882a593Smuzhiyun .npwm = 4,
43*4882a593Smuzhiyun .base_unit_bits = 22,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
pwm_lpss_probe_pci(struct pci_dev * pdev,const struct pci_device_id * id)46*4882a593Smuzhiyun static int pwm_lpss_probe_pci(struct pci_dev *pdev,
47*4882a593Smuzhiyun const struct pci_device_id *id)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun const struct pwm_lpss_boardinfo *info;
50*4882a593Smuzhiyun struct pwm_lpss_chip *lpwm;
51*4882a593Smuzhiyun int err;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun err = pcim_enable_device(pdev);
54*4882a593Smuzhiyun if (err < 0)
55*4882a593Smuzhiyun return err;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun info = (struct pwm_lpss_boardinfo *)id->driver_data;
58*4882a593Smuzhiyun lpwm = pwm_lpss_probe(&pdev->dev, &pdev->resource[0], info);
59*4882a593Smuzhiyun if (IS_ERR(lpwm))
60*4882a593Smuzhiyun return PTR_ERR(lpwm);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun pci_set_drvdata(pdev, lpwm);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun pm_runtime_put(&pdev->dev);
65*4882a593Smuzhiyun pm_runtime_allow(&pdev->dev);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
pwm_lpss_remove_pci(struct pci_dev * pdev)70*4882a593Smuzhiyun static void pwm_lpss_remove_pci(struct pci_dev *pdev)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun struct pwm_lpss_chip *lpwm = pci_get_drvdata(pdev);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun pm_runtime_forbid(&pdev->dev);
75*4882a593Smuzhiyun pm_runtime_get_sync(&pdev->dev);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun pwm_lpss_remove(lpwm);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #ifdef CONFIG_PM
pwm_lpss_runtime_suspend_pci(struct device * dev)81*4882a593Smuzhiyun static int pwm_lpss_runtime_suspend_pci(struct device *dev)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun /*
84*4882a593Smuzhiyun * The PCI core will handle transition to D3 automatically. We only
85*4882a593Smuzhiyun * need to provide runtime PM hooks for that to happen.
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
pwm_lpss_runtime_resume_pci(struct device * dev)90*4882a593Smuzhiyun static int pwm_lpss_runtime_resume_pci(struct device *dev)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun #endif
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct dev_pm_ops pwm_lpss_pci_pm = {
97*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(pwm_lpss_runtime_suspend_pci,
98*4882a593Smuzhiyun pwm_lpss_runtime_resume_pci, NULL)
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct pci_device_id pwm_lpss_pci_ids[] = {
102*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0ac8), (unsigned long)&pwm_lpss_bxt_info},
103*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0f08), (unsigned long)&pwm_lpss_byt_info},
104*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0f09), (unsigned long)&pwm_lpss_byt_info},
105*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x11a5), (unsigned long)&pwm_lpss_tng_info},
106*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)&pwm_lpss_bxt_info},
107*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x2288), (unsigned long)&pwm_lpss_bsw_info},
108*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x2289), (unsigned long)&pwm_lpss_bsw_info},
109*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x31c8), (unsigned long)&pwm_lpss_bxt_info},
110*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x5ac8), (unsigned long)&pwm_lpss_bxt_info},
111*4882a593Smuzhiyun { },
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun static struct pci_driver pwm_lpss_driver_pci = {
116*4882a593Smuzhiyun .name = "pwm-lpss",
117*4882a593Smuzhiyun .id_table = pwm_lpss_pci_ids,
118*4882a593Smuzhiyun .probe = pwm_lpss_probe_pci,
119*4882a593Smuzhiyun .remove = pwm_lpss_remove_pci,
120*4882a593Smuzhiyun .driver = {
121*4882a593Smuzhiyun .pm = &pwm_lpss_pci_pm,
122*4882a593Smuzhiyun },
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun module_pci_driver(pwm_lpss_driver_pci);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun MODULE_DESCRIPTION("PWM PCI driver for Intel LPSS");
127*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
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