xref: /OK3568_Linux_fs/kernel/drivers/pwm/pwm-lpc32xx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/pwm.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun struct lpc32xx_pwm_chip {
18*4882a593Smuzhiyun 	struct pwm_chip chip;
19*4882a593Smuzhiyun 	struct clk *clk;
20*4882a593Smuzhiyun 	void __iomem *base;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define PWM_ENABLE	BIT(31)
24*4882a593Smuzhiyun #define PWM_PIN_LEVEL	BIT(30)
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define to_lpc32xx_pwm_chip(_chip) \
27*4882a593Smuzhiyun 	container_of(_chip, struct lpc32xx_pwm_chip, chip)
28*4882a593Smuzhiyun 
lpc32xx_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)29*4882a593Smuzhiyun static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
30*4882a593Smuzhiyun 			      int duty_ns, int period_ns)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun 	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
33*4882a593Smuzhiyun 	unsigned long long c;
34*4882a593Smuzhiyun 	int period_cycles, duty_cycles;
35*4882a593Smuzhiyun 	u32 val;
36*4882a593Smuzhiyun 	c = clk_get_rate(lpc32xx->clk);
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	/* The highest acceptable divisor is 256, which is represented by 0 */
39*4882a593Smuzhiyun 	period_cycles = div64_u64(c * period_ns,
40*4882a593Smuzhiyun 			       (unsigned long long)NSEC_PER_SEC * 256);
41*4882a593Smuzhiyun 	if (!period_cycles || period_cycles > 256)
42*4882a593Smuzhiyun 		return -ERANGE;
43*4882a593Smuzhiyun 	if (period_cycles == 256)
44*4882a593Smuzhiyun 		period_cycles = 0;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	/* Compute 256 x #duty/period value and care for corner cases */
47*4882a593Smuzhiyun 	duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
48*4882a593Smuzhiyun 				period_ns);
49*4882a593Smuzhiyun 	if (!duty_cycles)
50*4882a593Smuzhiyun 		duty_cycles = 1;
51*4882a593Smuzhiyun 	if (duty_cycles > 255)
52*4882a593Smuzhiyun 		duty_cycles = 255;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
55*4882a593Smuzhiyun 	val &= ~0xFFFF;
56*4882a593Smuzhiyun 	val |= (period_cycles << 8) | duty_cycles;
57*4882a593Smuzhiyun 	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
lpc32xx_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)62*4882a593Smuzhiyun static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
65*4882a593Smuzhiyun 	u32 val;
66*4882a593Smuzhiyun 	int ret;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	ret = clk_prepare_enable(lpc32xx->clk);
69*4882a593Smuzhiyun 	if (ret)
70*4882a593Smuzhiyun 		return ret;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
73*4882a593Smuzhiyun 	val |= PWM_ENABLE;
74*4882a593Smuzhiyun 	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
lpc32xx_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)79*4882a593Smuzhiyun static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
82*4882a593Smuzhiyun 	u32 val;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	val = readl(lpc32xx->base + (pwm->hwpwm << 2));
85*4882a593Smuzhiyun 	val &= ~PWM_ENABLE;
86*4882a593Smuzhiyun 	writel(val, lpc32xx->base + (pwm->hwpwm << 2));
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	clk_disable_unprepare(lpc32xx->clk);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun static const struct pwm_ops lpc32xx_pwm_ops = {
92*4882a593Smuzhiyun 	.config = lpc32xx_pwm_config,
93*4882a593Smuzhiyun 	.enable = lpc32xx_pwm_enable,
94*4882a593Smuzhiyun 	.disable = lpc32xx_pwm_disable,
95*4882a593Smuzhiyun 	.owner = THIS_MODULE,
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
lpc32xx_pwm_probe(struct platform_device * pdev)98*4882a593Smuzhiyun static int lpc32xx_pwm_probe(struct platform_device *pdev)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	struct lpc32xx_pwm_chip *lpc32xx;
101*4882a593Smuzhiyun 	struct resource *res;
102*4882a593Smuzhiyun 	int ret;
103*4882a593Smuzhiyun 	u32 val;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
106*4882a593Smuzhiyun 	if (!lpc32xx)
107*4882a593Smuzhiyun 		return -ENOMEM;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
110*4882a593Smuzhiyun 	lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
111*4882a593Smuzhiyun 	if (IS_ERR(lpc32xx->base))
112*4882a593Smuzhiyun 		return PTR_ERR(lpc32xx->base);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
115*4882a593Smuzhiyun 	if (IS_ERR(lpc32xx->clk))
116*4882a593Smuzhiyun 		return PTR_ERR(lpc32xx->clk);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	lpc32xx->chip.dev = &pdev->dev;
119*4882a593Smuzhiyun 	lpc32xx->chip.ops = &lpc32xx_pwm_ops;
120*4882a593Smuzhiyun 	lpc32xx->chip.npwm = 1;
121*4882a593Smuzhiyun 	lpc32xx->chip.base = -1;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* If PWM is disabled, configure the output to the default value */
124*4882a593Smuzhiyun 	val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
125*4882a593Smuzhiyun 	val &= ~PWM_PIN_LEVEL;
126*4882a593Smuzhiyun 	writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	ret = pwmchip_add(&lpc32xx->chip);
129*4882a593Smuzhiyun 	if (ret < 0) {
130*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
131*4882a593Smuzhiyun 		return ret;
132*4882a593Smuzhiyun 	}
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	platform_set_drvdata(pdev, lpc32xx);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
lpc32xx_pwm_remove(struct platform_device * pdev)139*4882a593Smuzhiyun static int lpc32xx_pwm_remove(struct platform_device *pdev)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
142*4882a593Smuzhiyun 	unsigned int i;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	for (i = 0; i < lpc32xx->chip.npwm; i++)
145*4882a593Smuzhiyun 		pwm_disable(&lpc32xx->chip.pwms[i]);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	return pwmchip_remove(&lpc32xx->chip);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
151*4882a593Smuzhiyun 	{ .compatible = "nxp,lpc3220-pwm", },
152*4882a593Smuzhiyun 	{ /* sentinel */ }
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun static struct platform_driver lpc32xx_pwm_driver = {
157*4882a593Smuzhiyun 	.driver = {
158*4882a593Smuzhiyun 		.name = "lpc32xx-pwm",
159*4882a593Smuzhiyun 		.of_match_table = lpc32xx_pwm_dt_ids,
160*4882a593Smuzhiyun 	},
161*4882a593Smuzhiyun 	.probe = lpc32xx_pwm_probe,
162*4882a593Smuzhiyun 	.remove = lpc32xx_pwm_remove,
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun module_platform_driver(lpc32xx_pwm_driver);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun MODULE_ALIAS("platform:lpc32xx-pwm");
167*4882a593Smuzhiyun MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
168*4882a593Smuzhiyun MODULE_DESCRIPTION("LPC32XX PWM Driver");
169*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
170