1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * simple driver for PWM (Pulse Width Modulator) controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bitfield.h>
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/pwm.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define MX1_PWMC 0x00 /* PWM Control Register */
23*4882a593Smuzhiyun #define MX1_PWMS 0x04 /* PWM Sample Register */
24*4882a593Smuzhiyun #define MX1_PWMP 0x08 /* PWM Period Register */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define MX1_PWMC_EN BIT(4)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct pwm_imx1_chip {
29*4882a593Smuzhiyun struct clk *clk_ipg;
30*4882a593Smuzhiyun struct clk *clk_per;
31*4882a593Smuzhiyun void __iomem *mmio_base;
32*4882a593Smuzhiyun struct pwm_chip chip;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define to_pwm_imx1_chip(chip) container_of(chip, struct pwm_imx1_chip, chip)
36*4882a593Smuzhiyun
pwm_imx1_clk_prepare_enable(struct pwm_chip * chip)37*4882a593Smuzhiyun static int pwm_imx1_clk_prepare_enable(struct pwm_chip *chip)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
40*4882a593Smuzhiyun int ret;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun ret = clk_prepare_enable(imx->clk_ipg);
43*4882a593Smuzhiyun if (ret)
44*4882a593Smuzhiyun return ret;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun ret = clk_prepare_enable(imx->clk_per);
47*4882a593Smuzhiyun if (ret) {
48*4882a593Smuzhiyun clk_disable_unprepare(imx->clk_ipg);
49*4882a593Smuzhiyun return ret;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
pwm_imx1_clk_disable_unprepare(struct pwm_chip * chip)55*4882a593Smuzhiyun static void pwm_imx1_clk_disable_unprepare(struct pwm_chip *chip)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun clk_disable_unprepare(imx->clk_per);
60*4882a593Smuzhiyun clk_disable_unprepare(imx->clk_ipg);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
pwm_imx1_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)63*4882a593Smuzhiyun static int pwm_imx1_config(struct pwm_chip *chip,
64*4882a593Smuzhiyun struct pwm_device *pwm, int duty_ns, int period_ns)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
67*4882a593Smuzhiyun u32 max, p;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * The PWM subsystem allows for exact frequencies. However,
71*4882a593Smuzhiyun * I cannot connect a scope on my device to the PWM line and
72*4882a593Smuzhiyun * thus cannot provide the program the PWM controller
73*4882a593Smuzhiyun * exactly. Instead, I'm relying on the fact that the
74*4882a593Smuzhiyun * Bootloader (u-boot or WinCE+haret) has programmed the PWM
75*4882a593Smuzhiyun * function group already. So I'll just modify the PWM sample
76*4882a593Smuzhiyun * register to follow the ratio of duty_ns vs. period_ns
77*4882a593Smuzhiyun * accordingly.
78*4882a593Smuzhiyun *
79*4882a593Smuzhiyun * This is good enough for programming the brightness of
80*4882a593Smuzhiyun * the LCD backlight.
81*4882a593Smuzhiyun *
82*4882a593Smuzhiyun * The real implementation would divide PERCLK[0] first by
83*4882a593Smuzhiyun * both the prescaler (/1 .. /128) and then by CLKSEL
84*4882a593Smuzhiyun * (/2 .. /16).
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun max = readl(imx->mmio_base + MX1_PWMP);
87*4882a593Smuzhiyun p = max * duty_ns / period_ns;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun writel(max - p, imx->mmio_base + MX1_PWMS);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
pwm_imx1_enable(struct pwm_chip * chip,struct pwm_device * pwm)94*4882a593Smuzhiyun static int pwm_imx1_enable(struct pwm_chip *chip, struct pwm_device *pwm)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
97*4882a593Smuzhiyun u32 value;
98*4882a593Smuzhiyun int ret;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun ret = pwm_imx1_clk_prepare_enable(chip);
101*4882a593Smuzhiyun if (ret < 0)
102*4882a593Smuzhiyun return ret;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun value = readl(imx->mmio_base + MX1_PWMC);
105*4882a593Smuzhiyun value |= MX1_PWMC_EN;
106*4882a593Smuzhiyun writel(value, imx->mmio_base + MX1_PWMC);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
pwm_imx1_disable(struct pwm_chip * chip,struct pwm_device * pwm)111*4882a593Smuzhiyun static void pwm_imx1_disable(struct pwm_chip *chip, struct pwm_device *pwm)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct pwm_imx1_chip *imx = to_pwm_imx1_chip(chip);
114*4882a593Smuzhiyun u32 value;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun value = readl(imx->mmio_base + MX1_PWMC);
117*4882a593Smuzhiyun value &= ~MX1_PWMC_EN;
118*4882a593Smuzhiyun writel(value, imx->mmio_base + MX1_PWMC);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun pwm_imx1_clk_disable_unprepare(chip);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun static const struct pwm_ops pwm_imx1_ops = {
124*4882a593Smuzhiyun .enable = pwm_imx1_enable,
125*4882a593Smuzhiyun .disable = pwm_imx1_disable,
126*4882a593Smuzhiyun .config = pwm_imx1_config,
127*4882a593Smuzhiyun .owner = THIS_MODULE,
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static const struct of_device_id pwm_imx1_dt_ids[] = {
131*4882a593Smuzhiyun { .compatible = "fsl,imx1-pwm", },
132*4882a593Smuzhiyun { /* sentinel */ }
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, pwm_imx1_dt_ids);
135*4882a593Smuzhiyun
pwm_imx1_probe(struct platform_device * pdev)136*4882a593Smuzhiyun static int pwm_imx1_probe(struct platform_device *pdev)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct pwm_imx1_chip *imx;
139*4882a593Smuzhiyun struct resource *r;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
142*4882a593Smuzhiyun if (!imx)
143*4882a593Smuzhiyun return -ENOMEM;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun platform_set_drvdata(pdev, imx);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
148*4882a593Smuzhiyun if (IS_ERR(imx->clk_ipg)) {
149*4882a593Smuzhiyun dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
150*4882a593Smuzhiyun PTR_ERR(imx->clk_ipg));
151*4882a593Smuzhiyun return PTR_ERR(imx->clk_ipg);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun imx->clk_per = devm_clk_get(&pdev->dev, "per");
155*4882a593Smuzhiyun if (IS_ERR(imx->clk_per)) {
156*4882a593Smuzhiyun int ret = PTR_ERR(imx->clk_per);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun if (ret != -EPROBE_DEFER)
159*4882a593Smuzhiyun dev_err(&pdev->dev,
160*4882a593Smuzhiyun "failed to get peripheral clock: %d\n",
161*4882a593Smuzhiyun ret);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun return ret;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun imx->chip.ops = &pwm_imx1_ops;
167*4882a593Smuzhiyun imx->chip.dev = &pdev->dev;
168*4882a593Smuzhiyun imx->chip.base = -1;
169*4882a593Smuzhiyun imx->chip.npwm = 1;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
172*4882a593Smuzhiyun imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
173*4882a593Smuzhiyun if (IS_ERR(imx->mmio_base))
174*4882a593Smuzhiyun return PTR_ERR(imx->mmio_base);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun return pwmchip_add(&imx->chip);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
pwm_imx1_remove(struct platform_device * pdev)179*4882a593Smuzhiyun static int pwm_imx1_remove(struct platform_device *pdev)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun struct pwm_imx1_chip *imx = platform_get_drvdata(pdev);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun return pwmchip_remove(&imx->chip);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static struct platform_driver pwm_imx1_driver = {
187*4882a593Smuzhiyun .driver = {
188*4882a593Smuzhiyun .name = "pwm-imx1",
189*4882a593Smuzhiyun .of_match_table = pwm_imx1_dt_ids,
190*4882a593Smuzhiyun },
191*4882a593Smuzhiyun .probe = pwm_imx1_probe,
192*4882a593Smuzhiyun .remove = pwm_imx1_remove,
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun module_platform_driver(pwm_imx1_driver);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
197*4882a593Smuzhiyun MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
198