xref: /OK3568_Linux_fs/kernel/drivers/pwm/pwm-cros-ec.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Expose a PWM controlled by the ChromeOS EC to the host processor.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2016 Google, Inc.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/platform_data/cros_ec_commands.h>
10*4882a593Smuzhiyun #include <linux/platform_data/cros_ec_proto.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/pwm.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /**
16*4882a593Smuzhiyun  * struct cros_ec_pwm_device - Driver data for EC PWM
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * @dev: Device node
19*4882a593Smuzhiyun  * @ec: Pointer to EC device
20*4882a593Smuzhiyun  * @chip: PWM controller chip
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun struct cros_ec_pwm_device {
23*4882a593Smuzhiyun 	struct device *dev;
24*4882a593Smuzhiyun 	struct cros_ec_device *ec;
25*4882a593Smuzhiyun 	struct pwm_chip chip;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /**
29*4882a593Smuzhiyun  * struct cros_ec_pwm - per-PWM driver data
30*4882a593Smuzhiyun  * @duty_cycle: cached duty cycle
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun struct cros_ec_pwm {
33*4882a593Smuzhiyun 	u16 duty_cycle;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
pwm_to_cros_ec_pwm(struct pwm_chip * c)36*4882a593Smuzhiyun static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *c)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun 	return container_of(c, struct cros_ec_pwm_device, chip);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun 
cros_ec_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)41*4882a593Smuzhiyun static int cros_ec_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	struct cros_ec_pwm *channel;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
46*4882a593Smuzhiyun 	if (!channel)
47*4882a593Smuzhiyun 		return -ENOMEM;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	pwm_set_chip_data(pwm, channel);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun 
cros_ec_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)54*4882a593Smuzhiyun static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	kfree(channel);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
cros_ec_pwm_set_duty(struct cros_ec_device * ec,u8 index,u16 duty)61*4882a593Smuzhiyun static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	struct {
64*4882a593Smuzhiyun 		struct cros_ec_command msg;
65*4882a593Smuzhiyun 		struct ec_params_pwm_set_duty params;
66*4882a593Smuzhiyun 	} __packed buf;
67*4882a593Smuzhiyun 	struct ec_params_pwm_set_duty *params = &buf.params;
68*4882a593Smuzhiyun 	struct cros_ec_command *msg = &buf.msg;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	memset(&buf, 0, sizeof(buf));
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	msg->version = 0;
73*4882a593Smuzhiyun 	msg->command = EC_CMD_PWM_SET_DUTY;
74*4882a593Smuzhiyun 	msg->insize = 0;
75*4882a593Smuzhiyun 	msg->outsize = sizeof(*params);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	params->duty = duty;
78*4882a593Smuzhiyun 	params->pwm_type = EC_PWM_TYPE_GENERIC;
79*4882a593Smuzhiyun 	params->index = index;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	return cros_ec_cmd_xfer_status(ec, msg);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
cros_ec_pwm_get_duty(struct cros_ec_device * ec,u8 index)84*4882a593Smuzhiyun static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	struct {
87*4882a593Smuzhiyun 		struct cros_ec_command msg;
88*4882a593Smuzhiyun 		union {
89*4882a593Smuzhiyun 			struct ec_params_pwm_get_duty params;
90*4882a593Smuzhiyun 			struct ec_response_pwm_get_duty resp;
91*4882a593Smuzhiyun 		};
92*4882a593Smuzhiyun 	} __packed buf;
93*4882a593Smuzhiyun 	struct ec_params_pwm_get_duty *params = &buf.params;
94*4882a593Smuzhiyun 	struct ec_response_pwm_get_duty *resp = &buf.resp;
95*4882a593Smuzhiyun 	struct cros_ec_command *msg = &buf.msg;
96*4882a593Smuzhiyun 	int ret;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	memset(&buf, 0, sizeof(buf));
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	msg->version = 0;
101*4882a593Smuzhiyun 	msg->command = EC_CMD_PWM_GET_DUTY;
102*4882a593Smuzhiyun 	msg->insize = sizeof(*resp);
103*4882a593Smuzhiyun 	msg->outsize = sizeof(*params);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	params->pwm_type = EC_PWM_TYPE_GENERIC;
106*4882a593Smuzhiyun 	params->index = index;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	ret = cros_ec_cmd_xfer_status(ec, msg);
109*4882a593Smuzhiyun 	if (ret < 0)
110*4882a593Smuzhiyun 		return ret;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return resp->duty;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
cros_ec_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)115*4882a593Smuzhiyun static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
116*4882a593Smuzhiyun 			     const struct pwm_state *state)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
119*4882a593Smuzhiyun 	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
120*4882a593Smuzhiyun 	u16 duty_cycle;
121*4882a593Smuzhiyun 	int ret;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* The EC won't let us change the period */
124*4882a593Smuzhiyun 	if (state->period != EC_PWM_MAX_DUTY)
125*4882a593Smuzhiyun 		return -EINVAL;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	/*
128*4882a593Smuzhiyun 	 * EC doesn't separate the concept of duty cycle and enabled, but
129*4882a593Smuzhiyun 	 * kernel does. Translate.
130*4882a593Smuzhiyun 	 */
131*4882a593Smuzhiyun 	duty_cycle = state->enabled ? state->duty_cycle : 0;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle);
134*4882a593Smuzhiyun 	if (ret < 0)
135*4882a593Smuzhiyun 		return ret;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	channel->duty_cycle = state->duty_cycle;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	return 0;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
cros_ec_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)142*4882a593Smuzhiyun static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
143*4882a593Smuzhiyun 				  struct pwm_state *state)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
146*4882a593Smuzhiyun 	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
147*4882a593Smuzhiyun 	int ret;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm);
150*4882a593Smuzhiyun 	if (ret < 0) {
151*4882a593Smuzhiyun 		dev_err(chip->dev, "error getting initial duty: %d\n", ret);
152*4882a593Smuzhiyun 		return;
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	state->enabled = (ret > 0);
156*4882a593Smuzhiyun 	state->period = EC_PWM_MAX_DUTY;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/*
159*4882a593Smuzhiyun 	 * Note that "disabled" and "duty cycle == 0" are treated the same. If
160*4882a593Smuzhiyun 	 * the cached duty cycle is not zero, used the cached duty cycle. This
161*4882a593Smuzhiyun 	 * ensures that the configured duty cycle is kept across a disable and
162*4882a593Smuzhiyun 	 * enable operation and avoids potentially confusing consumers.
163*4882a593Smuzhiyun 	 *
164*4882a593Smuzhiyun 	 * For the case of the initial hardware readout, channel->duty_cycle
165*4882a593Smuzhiyun 	 * will be 0 and the actual duty cycle read from the EC is used.
166*4882a593Smuzhiyun 	 */
167*4882a593Smuzhiyun 	if (ret == 0 && channel->duty_cycle > 0)
168*4882a593Smuzhiyun 		state->duty_cycle = channel->duty_cycle;
169*4882a593Smuzhiyun 	else
170*4882a593Smuzhiyun 		state->duty_cycle = ret;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static struct pwm_device *
cros_ec_pwm_xlate(struct pwm_chip * pc,const struct of_phandle_args * args)174*4882a593Smuzhiyun cros_ec_pwm_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	struct pwm_device *pwm;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	if (args->args[0] >= pc->npwm)
179*4882a593Smuzhiyun 		return ERR_PTR(-EINVAL);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
182*4882a593Smuzhiyun 	if (IS_ERR(pwm))
183*4882a593Smuzhiyun 		return pwm;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	/* The EC won't let us change the period */
186*4882a593Smuzhiyun 	pwm->args.period = EC_PWM_MAX_DUTY;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	return pwm;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun static const struct pwm_ops cros_ec_pwm_ops = {
192*4882a593Smuzhiyun 	.request = cros_ec_pwm_request,
193*4882a593Smuzhiyun 	.free = cros_ec_pwm_free,
194*4882a593Smuzhiyun 	.get_state	= cros_ec_pwm_get_state,
195*4882a593Smuzhiyun 	.apply		= cros_ec_pwm_apply,
196*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun /*
200*4882a593Smuzhiyun  * Determine the number of supported PWMs. The EC does not return the number
201*4882a593Smuzhiyun  * of PWMs it supports directly, so we have to read the pwm duty cycle for
202*4882a593Smuzhiyun  * subsequent channels until we get an error.
203*4882a593Smuzhiyun  */
cros_ec_num_pwms(struct cros_ec_device * ec)204*4882a593Smuzhiyun static int cros_ec_num_pwms(struct cros_ec_device *ec)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	int i, ret;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	/* The index field is only 8 bits */
209*4882a593Smuzhiyun 	for (i = 0; i <= U8_MAX; i++) {
210*4882a593Smuzhiyun 		ret = cros_ec_pwm_get_duty(ec, i);
211*4882a593Smuzhiyun 		/*
212*4882a593Smuzhiyun 		 * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
213*4882a593Smuzhiyun 		 * responses; everything else is treated as an error.
214*4882a593Smuzhiyun 		 * The EC error codes map to -EOPNOTSUPP and -EINVAL,
215*4882a593Smuzhiyun 		 * so check for those.
216*4882a593Smuzhiyun 		 */
217*4882a593Smuzhiyun 		switch (ret) {
218*4882a593Smuzhiyun 		case -EOPNOTSUPP:	/* invalid command */
219*4882a593Smuzhiyun 			return -ENODEV;
220*4882a593Smuzhiyun 		case -EINVAL:		/* invalid parameter */
221*4882a593Smuzhiyun 			return i;
222*4882a593Smuzhiyun 		default:
223*4882a593Smuzhiyun 			if (ret < 0)
224*4882a593Smuzhiyun 				return ret;
225*4882a593Smuzhiyun 			break;
226*4882a593Smuzhiyun 		}
227*4882a593Smuzhiyun 	}
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	return U8_MAX;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun 
cros_ec_pwm_probe(struct platform_device * pdev)232*4882a593Smuzhiyun static int cros_ec_pwm_probe(struct platform_device *pdev)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun 	struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
235*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
236*4882a593Smuzhiyun 	struct cros_ec_pwm_device *ec_pwm;
237*4882a593Smuzhiyun 	struct pwm_chip *chip;
238*4882a593Smuzhiyun 	int ret;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	if (!ec) {
241*4882a593Smuzhiyun 		dev_err(dev, "no parent EC device\n");
242*4882a593Smuzhiyun 		return -EINVAL;
243*4882a593Smuzhiyun 	}
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
246*4882a593Smuzhiyun 	if (!ec_pwm)
247*4882a593Smuzhiyun 		return -ENOMEM;
248*4882a593Smuzhiyun 	chip = &ec_pwm->chip;
249*4882a593Smuzhiyun 	ec_pwm->ec = ec;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	/* PWM chip */
252*4882a593Smuzhiyun 	chip->dev = dev;
253*4882a593Smuzhiyun 	chip->ops = &cros_ec_pwm_ops;
254*4882a593Smuzhiyun 	chip->of_xlate = cros_ec_pwm_xlate;
255*4882a593Smuzhiyun 	chip->of_pwm_n_cells = 1;
256*4882a593Smuzhiyun 	chip->base = -1;
257*4882a593Smuzhiyun 	ret = cros_ec_num_pwms(ec);
258*4882a593Smuzhiyun 	if (ret < 0) {
259*4882a593Smuzhiyun 		dev_err(dev, "Couldn't find PWMs: %d\n", ret);
260*4882a593Smuzhiyun 		return ret;
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 	chip->npwm = ret;
263*4882a593Smuzhiyun 	dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	ret = pwmchip_add(chip);
266*4882a593Smuzhiyun 	if (ret < 0) {
267*4882a593Smuzhiyun 		dev_err(dev, "cannot register PWM: %d\n", ret);
268*4882a593Smuzhiyun 		return ret;
269*4882a593Smuzhiyun 	}
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	platform_set_drvdata(pdev, ec_pwm);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	return ret;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun 
cros_ec_pwm_remove(struct platform_device * dev)276*4882a593Smuzhiyun static int cros_ec_pwm_remove(struct platform_device *dev)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun 	struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev);
279*4882a593Smuzhiyun 	struct pwm_chip *chip = &ec_pwm->chip;
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	return pwmchip_remove(chip);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun #ifdef CONFIG_OF
285*4882a593Smuzhiyun static const struct of_device_id cros_ec_pwm_of_match[] = {
286*4882a593Smuzhiyun 	{ .compatible = "google,cros-ec-pwm" },
287*4882a593Smuzhiyun 	{},
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
290*4882a593Smuzhiyun #endif
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static struct platform_driver cros_ec_pwm_driver = {
293*4882a593Smuzhiyun 	.probe = cros_ec_pwm_probe,
294*4882a593Smuzhiyun 	.remove = cros_ec_pwm_remove,
295*4882a593Smuzhiyun 	.driver = {
296*4882a593Smuzhiyun 		.name = "cros-ec-pwm",
297*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(cros_ec_pwm_of_match),
298*4882a593Smuzhiyun 	},
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun module_platform_driver(cros_ec_pwm_driver);
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun MODULE_ALIAS("platform:cros-ec-pwm");
303*4882a593Smuzhiyun MODULE_DESCRIPTION("ChromeOS EC PWM driver");
304*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
305