1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Marvell Berlin PWM driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015 Marvell Technology Group Ltd.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Antoine Tenart <antoine.tenart@free-electrons.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
9*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
10*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/pwm.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define BERLIN_PWM_EN 0x0
22*4882a593Smuzhiyun #define BERLIN_PWM_ENABLE BIT(0)
23*4882a593Smuzhiyun #define BERLIN_PWM_CONTROL 0x4
24*4882a593Smuzhiyun /*
25*4882a593Smuzhiyun * The prescaler claims to support 8 different moduli, configured using the
26*4882a593Smuzhiyun * low three bits of PWM_CONTROL. (Sequentially, they are 1, 4, 8, 16, 64,
27*4882a593Smuzhiyun * 256, 1024, and 4096.) However, the moduli from 4 to 1024 appear to be
28*4882a593Smuzhiyun * implemented by internally shifting TCNT left without adding additional
29*4882a593Smuzhiyun * bits. So, the max TCNT that actually works for a modulus of 4 is 0x3fff;
30*4882a593Smuzhiyun * for 8, 0x1fff; and so on. This means that those moduli are entirely
31*4882a593Smuzhiyun * useless, as we could just do the shift ourselves. The 4096 modulus is
32*4882a593Smuzhiyun * implemented with a real prescaler, so we do use that, but we treat it
33*4882a593Smuzhiyun * as a flag instead of pretending the modulus is actually configurable.
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun #define BERLIN_PWM_PRESCALE_4096 0x7
36*4882a593Smuzhiyun #define BERLIN_PWM_INVERT_POLARITY BIT(3)
37*4882a593Smuzhiyun #define BERLIN_PWM_DUTY 0x8
38*4882a593Smuzhiyun #define BERLIN_PWM_TCNT 0xc
39*4882a593Smuzhiyun #define BERLIN_PWM_MAX_TCNT 65535
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct berlin_pwm_channel {
42*4882a593Smuzhiyun u32 enable;
43*4882a593Smuzhiyun u32 ctrl;
44*4882a593Smuzhiyun u32 duty;
45*4882a593Smuzhiyun u32 tcnt;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun struct berlin_pwm_chip {
49*4882a593Smuzhiyun struct pwm_chip chip;
50*4882a593Smuzhiyun struct clk *clk;
51*4882a593Smuzhiyun void __iomem *base;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
to_berlin_pwm_chip(struct pwm_chip * chip)54*4882a593Smuzhiyun static inline struct berlin_pwm_chip *to_berlin_pwm_chip(struct pwm_chip *chip)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun return container_of(chip, struct berlin_pwm_chip, chip);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
berlin_pwm_readl(struct berlin_pwm_chip * chip,unsigned int channel,unsigned long offset)59*4882a593Smuzhiyun static inline u32 berlin_pwm_readl(struct berlin_pwm_chip *chip,
60*4882a593Smuzhiyun unsigned int channel, unsigned long offset)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun return readl_relaxed(chip->base + channel * 0x10 + offset);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
berlin_pwm_writel(struct berlin_pwm_chip * chip,unsigned int channel,u32 value,unsigned long offset)65*4882a593Smuzhiyun static inline void berlin_pwm_writel(struct berlin_pwm_chip *chip,
66*4882a593Smuzhiyun unsigned int channel, u32 value,
67*4882a593Smuzhiyun unsigned long offset)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun writel_relaxed(value, chip->base + channel * 0x10 + offset);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
berlin_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)72*4882a593Smuzhiyun static int berlin_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun struct berlin_pwm_channel *channel;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun channel = kzalloc(sizeof(*channel), GFP_KERNEL);
77*4882a593Smuzhiyun if (!channel)
78*4882a593Smuzhiyun return -ENOMEM;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return pwm_set_chip_data(pwm, channel);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
berlin_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)83*4882a593Smuzhiyun static void berlin_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct berlin_pwm_channel *channel = pwm_get_chip_data(pwm);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun kfree(channel);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
berlin_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm_dev,int duty_ns,int period_ns)90*4882a593Smuzhiyun static int berlin_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm_dev,
91*4882a593Smuzhiyun int duty_ns, int period_ns)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip);
94*4882a593Smuzhiyun bool prescale_4096 = false;
95*4882a593Smuzhiyun u32 value, duty, period;
96*4882a593Smuzhiyun u64 cycles;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun cycles = clk_get_rate(pwm->clk);
99*4882a593Smuzhiyun cycles *= period_ns;
100*4882a593Smuzhiyun do_div(cycles, NSEC_PER_SEC);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (cycles > BERLIN_PWM_MAX_TCNT) {
103*4882a593Smuzhiyun prescale_4096 = true;
104*4882a593Smuzhiyun cycles >>= 12; // Prescaled by 4096
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (cycles > BERLIN_PWM_MAX_TCNT)
107*4882a593Smuzhiyun return -ERANGE;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun period = cycles;
111*4882a593Smuzhiyun cycles *= duty_ns;
112*4882a593Smuzhiyun do_div(cycles, period_ns);
113*4882a593Smuzhiyun duty = cycles;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL);
116*4882a593Smuzhiyun if (prescale_4096)
117*4882a593Smuzhiyun value |= BERLIN_PWM_PRESCALE_4096;
118*4882a593Smuzhiyun else
119*4882a593Smuzhiyun value &= ~BERLIN_PWM_PRESCALE_4096;
120*4882a593Smuzhiyun berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun berlin_pwm_writel(pwm, pwm_dev->hwpwm, duty, BERLIN_PWM_DUTY);
123*4882a593Smuzhiyun berlin_pwm_writel(pwm, pwm_dev->hwpwm, period, BERLIN_PWM_TCNT);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
berlin_pwm_set_polarity(struct pwm_chip * chip,struct pwm_device * pwm_dev,enum pwm_polarity polarity)128*4882a593Smuzhiyun static int berlin_pwm_set_polarity(struct pwm_chip *chip,
129*4882a593Smuzhiyun struct pwm_device *pwm_dev,
130*4882a593Smuzhiyun enum pwm_polarity polarity)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip);
133*4882a593Smuzhiyun u32 value;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (polarity == PWM_POLARITY_NORMAL)
138*4882a593Smuzhiyun value &= ~BERLIN_PWM_INVERT_POLARITY;
139*4882a593Smuzhiyun else
140*4882a593Smuzhiyun value |= BERLIN_PWM_INVERT_POLARITY;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
berlin_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm_dev)147*4882a593Smuzhiyun static int berlin_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm_dev)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip);
150*4882a593Smuzhiyun u32 value;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_EN);
153*4882a593Smuzhiyun value |= BERLIN_PWM_ENABLE;
154*4882a593Smuzhiyun berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_EN);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
berlin_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm_dev)159*4882a593Smuzhiyun static void berlin_pwm_disable(struct pwm_chip *chip,
160*4882a593Smuzhiyun struct pwm_device *pwm_dev)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip);
163*4882a593Smuzhiyun u32 value;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_EN);
166*4882a593Smuzhiyun value &= ~BERLIN_PWM_ENABLE;
167*4882a593Smuzhiyun berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_EN);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static const struct pwm_ops berlin_pwm_ops = {
171*4882a593Smuzhiyun .request = berlin_pwm_request,
172*4882a593Smuzhiyun .free = berlin_pwm_free,
173*4882a593Smuzhiyun .config = berlin_pwm_config,
174*4882a593Smuzhiyun .set_polarity = berlin_pwm_set_polarity,
175*4882a593Smuzhiyun .enable = berlin_pwm_enable,
176*4882a593Smuzhiyun .disable = berlin_pwm_disable,
177*4882a593Smuzhiyun .owner = THIS_MODULE,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun static const struct of_device_id berlin_pwm_match[] = {
181*4882a593Smuzhiyun { .compatible = "marvell,berlin-pwm" },
182*4882a593Smuzhiyun { },
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, berlin_pwm_match);
185*4882a593Smuzhiyun
berlin_pwm_probe(struct platform_device * pdev)186*4882a593Smuzhiyun static int berlin_pwm_probe(struct platform_device *pdev)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun struct berlin_pwm_chip *pwm;
189*4882a593Smuzhiyun struct resource *res;
190*4882a593Smuzhiyun int ret;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
193*4882a593Smuzhiyun if (!pwm)
194*4882a593Smuzhiyun return -ENOMEM;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
197*4882a593Smuzhiyun pwm->base = devm_ioremap_resource(&pdev->dev, res);
198*4882a593Smuzhiyun if (IS_ERR(pwm->base))
199*4882a593Smuzhiyun return PTR_ERR(pwm->base);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun pwm->clk = devm_clk_get(&pdev->dev, NULL);
202*4882a593Smuzhiyun if (IS_ERR(pwm->clk))
203*4882a593Smuzhiyun return PTR_ERR(pwm->clk);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun ret = clk_prepare_enable(pwm->clk);
206*4882a593Smuzhiyun if (ret)
207*4882a593Smuzhiyun return ret;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun pwm->chip.dev = &pdev->dev;
210*4882a593Smuzhiyun pwm->chip.ops = &berlin_pwm_ops;
211*4882a593Smuzhiyun pwm->chip.base = -1;
212*4882a593Smuzhiyun pwm->chip.npwm = 4;
213*4882a593Smuzhiyun pwm->chip.of_xlate = of_pwm_xlate_with_flags;
214*4882a593Smuzhiyun pwm->chip.of_pwm_n_cells = 3;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun ret = pwmchip_add(&pwm->chip);
217*4882a593Smuzhiyun if (ret < 0) {
218*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
219*4882a593Smuzhiyun clk_disable_unprepare(pwm->clk);
220*4882a593Smuzhiyun return ret;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun platform_set_drvdata(pdev, pwm);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun return 0;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
berlin_pwm_remove(struct platform_device * pdev)228*4882a593Smuzhiyun static int berlin_pwm_remove(struct platform_device *pdev)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun struct berlin_pwm_chip *pwm = platform_get_drvdata(pdev);
231*4882a593Smuzhiyun int ret;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun ret = pwmchip_remove(&pwm->chip);
234*4882a593Smuzhiyun clk_disable_unprepare(pwm->clk);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun return ret;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
berlin_pwm_suspend(struct device * dev)240*4882a593Smuzhiyun static int berlin_pwm_suspend(struct device *dev)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun struct berlin_pwm_chip *pwm = dev_get_drvdata(dev);
243*4882a593Smuzhiyun unsigned int i;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun for (i = 0; i < pwm->chip.npwm; i++) {
246*4882a593Smuzhiyun struct berlin_pwm_channel *channel;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun channel = pwm_get_chip_data(&pwm->chip.pwms[i]);
249*4882a593Smuzhiyun if (!channel)
250*4882a593Smuzhiyun continue;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun channel->enable = berlin_pwm_readl(pwm, i, BERLIN_PWM_ENABLE);
253*4882a593Smuzhiyun channel->ctrl = berlin_pwm_readl(pwm, i, BERLIN_PWM_CONTROL);
254*4882a593Smuzhiyun channel->duty = berlin_pwm_readl(pwm, i, BERLIN_PWM_DUTY);
255*4882a593Smuzhiyun channel->tcnt = berlin_pwm_readl(pwm, i, BERLIN_PWM_TCNT);
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun clk_disable_unprepare(pwm->clk);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun return 0;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
berlin_pwm_resume(struct device * dev)263*4882a593Smuzhiyun static int berlin_pwm_resume(struct device *dev)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct berlin_pwm_chip *pwm = dev_get_drvdata(dev);
266*4882a593Smuzhiyun unsigned int i;
267*4882a593Smuzhiyun int ret;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun ret = clk_prepare_enable(pwm->clk);
270*4882a593Smuzhiyun if (ret)
271*4882a593Smuzhiyun return ret;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun for (i = 0; i < pwm->chip.npwm; i++) {
274*4882a593Smuzhiyun struct berlin_pwm_channel *channel;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun channel = pwm_get_chip_data(&pwm->chip.pwms[i]);
277*4882a593Smuzhiyun if (!channel)
278*4882a593Smuzhiyun continue;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun berlin_pwm_writel(pwm, i, channel->ctrl, BERLIN_PWM_CONTROL);
281*4882a593Smuzhiyun berlin_pwm_writel(pwm, i, channel->duty, BERLIN_PWM_DUTY);
282*4882a593Smuzhiyun berlin_pwm_writel(pwm, i, channel->tcnt, BERLIN_PWM_TCNT);
283*4882a593Smuzhiyun berlin_pwm_writel(pwm, i, channel->enable, BERLIN_PWM_ENABLE);
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun return 0;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun #endif
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(berlin_pwm_pm_ops, berlin_pwm_suspend,
291*4882a593Smuzhiyun berlin_pwm_resume);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun static struct platform_driver berlin_pwm_driver = {
294*4882a593Smuzhiyun .probe = berlin_pwm_probe,
295*4882a593Smuzhiyun .remove = berlin_pwm_remove,
296*4882a593Smuzhiyun .driver = {
297*4882a593Smuzhiyun .name = "berlin-pwm",
298*4882a593Smuzhiyun .of_match_table = berlin_pwm_match,
299*4882a593Smuzhiyun .pm = &berlin_pwm_pm_ops,
300*4882a593Smuzhiyun },
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun module_platform_driver(berlin_pwm_driver);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
305*4882a593Smuzhiyun MODULE_DESCRIPTION("Marvell Berlin PWM driver");
306*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
307