1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/pwm.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define PWM_CONTROL 0x000
15*4882a593Smuzhiyun #define PWM_CONTROL_SHIFT(x) ((x) * 8)
16*4882a593Smuzhiyun #define PWM_CONTROL_MASK 0xff
17*4882a593Smuzhiyun #define PWM_MODE 0x80 /* set timer in PWM mode */
18*4882a593Smuzhiyun #define PWM_ENABLE (1 << 0)
19*4882a593Smuzhiyun #define PWM_POLARITY (1 << 4)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define PERIOD(x) (((x) * 0x10) + 0x10)
22*4882a593Smuzhiyun #define DUTY(x) (((x) * 0x10) + 0x14)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define PERIOD_MIN 0x2
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct bcm2835_pwm {
27*4882a593Smuzhiyun struct pwm_chip chip;
28*4882a593Smuzhiyun struct device *dev;
29*4882a593Smuzhiyun void __iomem *base;
30*4882a593Smuzhiyun struct clk *clk;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
to_bcm2835_pwm(struct pwm_chip * chip)33*4882a593Smuzhiyun static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun return container_of(chip, struct bcm2835_pwm, chip);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
bcm2835_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)38*4882a593Smuzhiyun static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
41*4882a593Smuzhiyun u32 value;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun value = readl(pc->base + PWM_CONTROL);
44*4882a593Smuzhiyun value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
45*4882a593Smuzhiyun value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
46*4882a593Smuzhiyun writel(value, pc->base + PWM_CONTROL);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
bcm2835_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)51*4882a593Smuzhiyun static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
54*4882a593Smuzhiyun u32 value;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun value = readl(pc->base + PWM_CONTROL);
57*4882a593Smuzhiyun value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
58*4882a593Smuzhiyun writel(value, pc->base + PWM_CONTROL);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
bcm2835_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)61*4882a593Smuzhiyun static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
62*4882a593Smuzhiyun int duty_ns, int period_ns)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
65*4882a593Smuzhiyun unsigned long rate = clk_get_rate(pc->clk);
66*4882a593Smuzhiyun unsigned long scaler;
67*4882a593Smuzhiyun u32 period;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if (!rate) {
70*4882a593Smuzhiyun dev_err(pc->dev, "failed to get clock rate\n");
71*4882a593Smuzhiyun return -EINVAL;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun scaler = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate);
75*4882a593Smuzhiyun period = DIV_ROUND_CLOSEST(period_ns, scaler);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (period < PERIOD_MIN)
78*4882a593Smuzhiyun return -EINVAL;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun writel(DIV_ROUND_CLOSEST(duty_ns, scaler),
81*4882a593Smuzhiyun pc->base + DUTY(pwm->hwpwm));
82*4882a593Smuzhiyun writel(period, pc->base + PERIOD(pwm->hwpwm));
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
bcm2835_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)87*4882a593Smuzhiyun static int bcm2835_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
90*4882a593Smuzhiyun u32 value;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun value = readl(pc->base + PWM_CONTROL);
93*4882a593Smuzhiyun value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
94*4882a593Smuzhiyun writel(value, pc->base + PWM_CONTROL);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
bcm2835_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)99*4882a593Smuzhiyun static void bcm2835_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
102*4882a593Smuzhiyun u32 value;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun value = readl(pc->base + PWM_CONTROL);
105*4882a593Smuzhiyun value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
106*4882a593Smuzhiyun writel(value, pc->base + PWM_CONTROL);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
bcm2835_set_polarity(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)109*4882a593Smuzhiyun static int bcm2835_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
110*4882a593Smuzhiyun enum pwm_polarity polarity)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
113*4882a593Smuzhiyun u32 value;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun value = readl(pc->base + PWM_CONTROL);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun if (polarity == PWM_POLARITY_NORMAL)
118*4882a593Smuzhiyun value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
119*4882a593Smuzhiyun else
120*4882a593Smuzhiyun value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun writel(value, pc->base + PWM_CONTROL);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static const struct pwm_ops bcm2835_pwm_ops = {
128*4882a593Smuzhiyun .request = bcm2835_pwm_request,
129*4882a593Smuzhiyun .free = bcm2835_pwm_free,
130*4882a593Smuzhiyun .config = bcm2835_pwm_config,
131*4882a593Smuzhiyun .enable = bcm2835_pwm_enable,
132*4882a593Smuzhiyun .disable = bcm2835_pwm_disable,
133*4882a593Smuzhiyun .set_polarity = bcm2835_set_polarity,
134*4882a593Smuzhiyun .owner = THIS_MODULE,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
bcm2835_pwm_probe(struct platform_device * pdev)137*4882a593Smuzhiyun static int bcm2835_pwm_probe(struct platform_device *pdev)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct bcm2835_pwm *pc;
140*4882a593Smuzhiyun struct resource *res;
141*4882a593Smuzhiyun int ret;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
144*4882a593Smuzhiyun if (!pc)
145*4882a593Smuzhiyun return -ENOMEM;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun pc->dev = &pdev->dev;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
150*4882a593Smuzhiyun pc->base = devm_ioremap_resource(&pdev->dev, res);
151*4882a593Smuzhiyun if (IS_ERR(pc->base))
152*4882a593Smuzhiyun return PTR_ERR(pc->base);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun pc->clk = devm_clk_get(&pdev->dev, NULL);
155*4882a593Smuzhiyun if (IS_ERR(pc->clk))
156*4882a593Smuzhiyun return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
157*4882a593Smuzhiyun "clock not found\n");
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun ret = clk_prepare_enable(pc->clk);
160*4882a593Smuzhiyun if (ret)
161*4882a593Smuzhiyun return ret;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun pc->chip.dev = &pdev->dev;
164*4882a593Smuzhiyun pc->chip.ops = &bcm2835_pwm_ops;
165*4882a593Smuzhiyun pc->chip.base = -1;
166*4882a593Smuzhiyun pc->chip.npwm = 2;
167*4882a593Smuzhiyun pc->chip.of_xlate = of_pwm_xlate_with_flags;
168*4882a593Smuzhiyun pc->chip.of_pwm_n_cells = 3;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun platform_set_drvdata(pdev, pc);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun ret = pwmchip_add(&pc->chip);
173*4882a593Smuzhiyun if (ret < 0)
174*4882a593Smuzhiyun goto add_fail;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun return 0;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun add_fail:
179*4882a593Smuzhiyun clk_disable_unprepare(pc->clk);
180*4882a593Smuzhiyun return ret;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
bcm2835_pwm_remove(struct platform_device * pdev)183*4882a593Smuzhiyun static int bcm2835_pwm_remove(struct platform_device *pdev)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun struct bcm2835_pwm *pc = platform_get_drvdata(pdev);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun clk_disable_unprepare(pc->clk);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return pwmchip_remove(&pc->chip);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static const struct of_device_id bcm2835_pwm_of_match[] = {
193*4882a593Smuzhiyun { .compatible = "brcm,bcm2835-pwm", },
194*4882a593Smuzhiyun { /* sentinel */ }
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun static struct platform_driver bcm2835_pwm_driver = {
199*4882a593Smuzhiyun .driver = {
200*4882a593Smuzhiyun .name = "bcm2835-pwm",
201*4882a593Smuzhiyun .of_match_table = bcm2835_pwm_of_match,
202*4882a593Smuzhiyun },
203*4882a593Smuzhiyun .probe = bcm2835_pwm_probe,
204*4882a593Smuzhiyun .remove = bcm2835_pwm_remove,
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun module_platform_driver(bcm2835_pwm_driver);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
209*4882a593Smuzhiyun MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
210*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
211