xref: /OK3568_Linux_fs/kernel/drivers/ptp/ptp_clockmatrix.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4*4882a593Smuzhiyun  * synchronization devices.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun #ifndef PTP_IDTCLOCKMATRIX_H
9*4882a593Smuzhiyun #define PTP_IDTCLOCKMATRIX_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/ktime.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include "idt8a340_reg.h"
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define FW_FILENAME	"idtcm.bin"
16*4882a593Smuzhiyun #define MAX_TOD		(4)
17*4882a593Smuzhiyun #define MAX_PLL		(8)
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define TOD_MASK_ADDR		(0xFFA5)
22*4882a593Smuzhiyun #define DEFAULT_TOD_MASK	(0x04)
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
25*4882a593Smuzhiyun #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define TOD0_PTP_PLL_ADDR		(0xFFA8)
28*4882a593Smuzhiyun #define TOD1_PTP_PLL_ADDR		(0xFFA9)
29*4882a593Smuzhiyun #define TOD2_PTP_PLL_ADDR		(0xFFAA)
30*4882a593Smuzhiyun #define TOD3_PTP_PLL_ADDR		(0xFFAB)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define TOD0_OUT_ALIGN_MASK_ADDR	(0xFFB0)
33*4882a593Smuzhiyun #define TOD1_OUT_ALIGN_MASK_ADDR	(0xFFB2)
34*4882a593Smuzhiyun #define TOD2_OUT_ALIGN_MASK_ADDR	(0xFFB4)
35*4882a593Smuzhiyun #define TOD3_OUT_ALIGN_MASK_ADDR	(0xFFB6)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define DEFAULT_OUTPUT_MASK_PLL0	(0x003)
38*4882a593Smuzhiyun #define DEFAULT_OUTPUT_MASK_PLL1	(0x00c)
39*4882a593Smuzhiyun #define DEFAULT_OUTPUT_MASK_PLL2	(0x030)
40*4882a593Smuzhiyun #define DEFAULT_OUTPUT_MASK_PLL3	(0x0c0)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define DEFAULT_TOD0_PTP_PLL		(0)
43*4882a593Smuzhiyun #define DEFAULT_TOD1_PTP_PLL		(1)
44*4882a593Smuzhiyun #define DEFAULT_TOD2_PTP_PLL		(2)
45*4882a593Smuzhiyun #define DEFAULT_TOD3_PTP_PLL		(3)
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define POST_SM_RESET_DELAY_MS		(3000)
48*4882a593Smuzhiyun #define PHASE_PULL_IN_THRESHOLD_NS	(150000)
49*4882a593Smuzhiyun #define PHASE_PULL_IN_THRESHOLD_NS_V487	(15000)
50*4882a593Smuzhiyun #define TOD_WRITE_OVERHEAD_COUNT_MAX	(2)
51*4882a593Smuzhiyun #define TOD_BYTE_COUNT			(11)
52*4882a593Smuzhiyun #define WR_PHASE_SETUP_MS		(5000)
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define OUTPUT_MODULE_FROM_INDEX(index)	(OUTPUT_0 + (index) * 0x10)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define PEROUT_ENABLE_OUTPUT_MASK		(0xdeadbeef)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define IDTCM_MAX_WRITE_COUNT			(512)
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* Values of DPLL_N.DPLL_MODE.PLL_MODE */
61*4882a593Smuzhiyun enum pll_mode {
62*4882a593Smuzhiyun 	PLL_MODE_MIN = 0,
63*4882a593Smuzhiyun 	PLL_MODE_NORMAL = PLL_MODE_MIN,
64*4882a593Smuzhiyun 	PLL_MODE_WRITE_PHASE = 1,
65*4882a593Smuzhiyun 	PLL_MODE_WRITE_FREQUENCY = 2,
66*4882a593Smuzhiyun 	PLL_MODE_GPIO_INC_DEC = 3,
67*4882a593Smuzhiyun 	PLL_MODE_SYNTHESIS = 4,
68*4882a593Smuzhiyun 	PLL_MODE_PHASE_MEASUREMENT = 5,
69*4882a593Smuzhiyun 	PLL_MODE_DISABLED = 6,
70*4882a593Smuzhiyun 	PLL_MODE_MAX = PLL_MODE_DISABLED,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun enum hw_tod_write_trig_sel {
74*4882a593Smuzhiyun 	HW_TOD_WR_TRIG_SEL_MIN = 0,
75*4882a593Smuzhiyun 	HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
76*4882a593Smuzhiyun 	HW_TOD_WR_TRIG_SEL_RESERVED = 1,
77*4882a593Smuzhiyun 	HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
78*4882a593Smuzhiyun 	HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
79*4882a593Smuzhiyun 	HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
80*4882a593Smuzhiyun 	HW_TOD_WR_TRIG_SEL_GPIO = 5,
81*4882a593Smuzhiyun 	HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
82*4882a593Smuzhiyun 	WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /* 4.8.7 only */
86*4882a593Smuzhiyun enum scsr_tod_write_trig_sel {
87*4882a593Smuzhiyun 	SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
88*4882a593Smuzhiyun 	SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
89*4882a593Smuzhiyun 	SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
90*4882a593Smuzhiyun 	SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
91*4882a593Smuzhiyun 	SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
92*4882a593Smuzhiyun 	SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
93*4882a593Smuzhiyun 	SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
94*4882a593Smuzhiyun 	SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* 4.8.7 only */
98*4882a593Smuzhiyun enum scsr_tod_write_type_sel {
99*4882a593Smuzhiyun 	SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
100*4882a593Smuzhiyun 	SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
101*4882a593Smuzhiyun 	SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
102*4882a593Smuzhiyun 	SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun struct idtcm;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun struct idtcm_channel {
108*4882a593Smuzhiyun 	struct ptp_clock_info	caps;
109*4882a593Smuzhiyun 	struct ptp_clock	*ptp_clock;
110*4882a593Smuzhiyun 	struct idtcm		*idtcm;
111*4882a593Smuzhiyun 	u16			dpll_phase;
112*4882a593Smuzhiyun 	u16			dpll_freq;
113*4882a593Smuzhiyun 	u16			dpll_n;
114*4882a593Smuzhiyun 	u16			dpll_ctrl_n;
115*4882a593Smuzhiyun 	u16			dpll_phase_pull_in;
116*4882a593Smuzhiyun 	u16			tod_read_primary;
117*4882a593Smuzhiyun 	u16			tod_write;
118*4882a593Smuzhiyun 	u16			tod_n;
119*4882a593Smuzhiyun 	u16			hw_dpll_n;
120*4882a593Smuzhiyun 	enum pll_mode		pll_mode;
121*4882a593Smuzhiyun 	u8			pll;
122*4882a593Smuzhiyun 	u16			output_mask;
123*4882a593Smuzhiyun 	int			write_phase_ready;
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun struct idtcm {
127*4882a593Smuzhiyun 	struct idtcm_channel	channel[MAX_TOD];
128*4882a593Smuzhiyun 	struct i2c_client	*client;
129*4882a593Smuzhiyun 	u8			page_offset;
130*4882a593Smuzhiyun 	u8			tod_mask;
131*4882a593Smuzhiyun 	char			version[16];
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	/* Overhead calculation for adjtime */
134*4882a593Smuzhiyun 	u8			calculate_overhead_flag;
135*4882a593Smuzhiyun 	s64			tod_write_overhead_ns;
136*4882a593Smuzhiyun 	ktime_t			start_time;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	/* Protects I2C read/modify/write registers from concurrent access */
139*4882a593Smuzhiyun 	struct mutex		reg_lock;
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun struct idtcm_fwrc {
143*4882a593Smuzhiyun 	u8 hiaddr;
144*4882a593Smuzhiyun 	u8 loaddr;
145*4882a593Smuzhiyun 	u8 value;
146*4882a593Smuzhiyun 	u8 reserved;
147*4882a593Smuzhiyun } __packed;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun #endif /* PTP_IDTCLOCKMATRIX_H */
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