1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef BQ25980_CHARGER_H 5*4882a593Smuzhiyun #define BQ25980_CHARGER_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define BQ25980_MANUFACTURER "Texas Instruments" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define BQ25980_BATOVP 0x0 10*4882a593Smuzhiyun #define BQ25980_BATOVP_ALM 0x1 11*4882a593Smuzhiyun #define BQ25980_BATOCP 0x2 12*4882a593Smuzhiyun #define BQ25980_BATOCP_ALM 0x3 13*4882a593Smuzhiyun #define BQ25980_BATUCP_ALM 0x4 14*4882a593Smuzhiyun #define BQ25980_CHRGR_CTRL_1 0x5 15*4882a593Smuzhiyun #define BQ25980_BUSOVP 0x6 16*4882a593Smuzhiyun #define BQ25980_BUSOVP_ALM 0x7 17*4882a593Smuzhiyun #define BQ25980_BUSOCP 0x8 18*4882a593Smuzhiyun #define BQ25980_BUSOCP_ALM 0x9 19*4882a593Smuzhiyun #define BQ25980_TEMP_CONTROL 0xA 20*4882a593Smuzhiyun #define BQ25980_TDIE_ALM 0xB 21*4882a593Smuzhiyun #define BQ25980_TSBUS_FLT 0xC 22*4882a593Smuzhiyun #define BQ25980_TSBAT_FLG 0xD 23*4882a593Smuzhiyun #define BQ25980_VAC_CONTROL 0xE 24*4882a593Smuzhiyun #define BQ25980_CHRGR_CTRL_2 0xF 25*4882a593Smuzhiyun #define BQ25980_CHRGR_CTRL_3 0x10 26*4882a593Smuzhiyun #define BQ25980_CHRGR_CTRL_4 0x11 27*4882a593Smuzhiyun #define BQ25980_CHRGR_CTRL_5 0x12 28*4882a593Smuzhiyun #define BQ25980_STAT1 0x13 29*4882a593Smuzhiyun #define BQ25980_STAT2 0x14 30*4882a593Smuzhiyun #define BQ25980_STAT3 0x15 31*4882a593Smuzhiyun #define BQ25980_STAT4 0x16 32*4882a593Smuzhiyun #define BQ25980_STAT5 0x17 33*4882a593Smuzhiyun #define BQ25980_FLAG1 0x18 34*4882a593Smuzhiyun #define BQ25980_FLAG2 0x19 35*4882a593Smuzhiyun #define BQ25980_FLAG3 0x1A 36*4882a593Smuzhiyun #define BQ25980_FLAG4 0x1B 37*4882a593Smuzhiyun #define BQ25980_FLAG5 0x1C 38*4882a593Smuzhiyun #define BQ25980_MASK1 0x1D 39*4882a593Smuzhiyun #define BQ25980_MASK2 0x1E 40*4882a593Smuzhiyun #define BQ25980_MASK3 0x1F 41*4882a593Smuzhiyun #define BQ25980_MASK4 0x20 42*4882a593Smuzhiyun #define BQ25980_MASK5 0x21 43*4882a593Smuzhiyun #define BQ25980_DEVICE_INFO 0x22 44*4882a593Smuzhiyun #define BQ25980_ADC_CONTROL1 0x23 45*4882a593Smuzhiyun #define BQ25980_ADC_CONTROL2 0x24 46*4882a593Smuzhiyun #define BQ25980_IBUS_ADC_MSB 0x25 47*4882a593Smuzhiyun #define BQ25980_IBUS_ADC_LSB 0x26 48*4882a593Smuzhiyun #define BQ25980_VBUS_ADC_MSB 0x27 49*4882a593Smuzhiyun #define BQ25980_VBUS_ADC_LSB 0x28 50*4882a593Smuzhiyun #define BQ25980_VAC1_ADC_MSB 0x29 51*4882a593Smuzhiyun #define BQ25980_VAC1_ADC_LSB 0x2A 52*4882a593Smuzhiyun #define BQ25980_VAC2_ADC_MSB 0x2B 53*4882a593Smuzhiyun #define BQ25980_VAC2_ADC_LSB 0x2C 54*4882a593Smuzhiyun #define BQ25980_VOUT_ADC_MSB 0x2D 55*4882a593Smuzhiyun #define BQ25980_VOUT_ADC_LSB 0x2E 56*4882a593Smuzhiyun #define BQ25980_VBAT_ADC_MSB 0x2F 57*4882a593Smuzhiyun #define BQ25980_VBAT_ADC_LSB 0x30 58*4882a593Smuzhiyun #define BQ25980_IBAT_ADC_MSB 0x31 59*4882a593Smuzhiyun #define BQ25980_IBAT_ADC_LSB 0x32 60*4882a593Smuzhiyun #define BQ25980_TSBUS_ADC_MSB 0x33 61*4882a593Smuzhiyun #define BQ25980_TSBUS_ADC_LSB 0x34 62*4882a593Smuzhiyun #define BQ25980_TSBAT_ADC_MSB 0x35 63*4882a593Smuzhiyun #define BQ25980_TSBAT_ADC_LSB 0x36 64*4882a593Smuzhiyun #define BQ25980_TDIE_ADC_MSB 0x37 65*4882a593Smuzhiyun #define BQ25980_TDIE_ADC_LSB 0x38 66*4882a593Smuzhiyun #define BQ25980_DEGLITCH_TIME 0x39 67*4882a593Smuzhiyun #define BQ25980_CHRGR_CTRL_6 0x3A 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define BQ25980_BUSOCP_STEP_uA 250000 70*4882a593Smuzhiyun #define BQ25980_BUSOCP_OFFSET_uA 1000000 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define BQ25980_BUSOCP_DFLT_uA 4250000 73*4882a593Smuzhiyun #define BQ25975_BUSOCP_DFLT_uA 4250000 74*4882a593Smuzhiyun #define BQ25960_BUSOCP_DFLT_uA 3250000 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define BQ25980_BUSOCP_MIN_uA 1000000 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define BQ25980_BUSOCP_SC_MAX_uA 5750000 79*4882a593Smuzhiyun #define BQ25975_BUSOCP_SC_MAX_uA 5750000 80*4882a593Smuzhiyun #define BQ25960_BUSOCP_SC_MAX_uA 3750000 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define BQ25980_BUSOCP_BYP_MAX_uA 8500000 83*4882a593Smuzhiyun #define BQ25975_BUSOCP_BYP_MAX_uA 8500000 84*4882a593Smuzhiyun #define BQ25960_BUSOCP_BYP_MAX_uA 5750000 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define BQ25980_BUSOVP_SC_STEP_uV 100000 87*4882a593Smuzhiyun #define BQ25975_BUSOVP_SC_STEP_uV 50000 88*4882a593Smuzhiyun #define BQ25960_BUSOVP_SC_STEP_uV 50000 89*4882a593Smuzhiyun #define BQ25980_BUSOVP_SC_OFFSET_uV 14000000 90*4882a593Smuzhiyun #define BQ25975_BUSOVP_SC_OFFSET_uV 7000000 91*4882a593Smuzhiyun #define BQ25960_BUSOVP_SC_OFFSET_uV 7000000 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define BQ25980_BUSOVP_BYP_STEP_uV 50000 94*4882a593Smuzhiyun #define BQ25975_BUSOVP_BYP_STEP_uV 25000 95*4882a593Smuzhiyun #define BQ25960_BUSOVP_BYP_STEP_uV 25000 96*4882a593Smuzhiyun #define BQ25980_BUSOVP_BYP_OFFSET_uV 7000000 97*4882a593Smuzhiyun #define BQ25975_BUSOVP_BYP_OFFSET_uV 3500000 98*4882a593Smuzhiyun #define BQ25960_BUSOVP_BYP_OFFSET_uV 3500000 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define BQ25980_BUSOVP_DFLT_uV 17800000 101*4882a593Smuzhiyun #define BQ25980_BUSOVP_BYPASS_DFLT_uV 8900000 102*4882a593Smuzhiyun #define BQ25975_BUSOVP_DFLT_uV 8900000 103*4882a593Smuzhiyun #define BQ25975_BUSOVP_BYPASS_DFLT_uV 4450000 104*4882a593Smuzhiyun #define BQ25960_BUSOVP_DFLT_uV 8900000 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define BQ25980_BUSOVP_SC_MIN_uV 14000000 107*4882a593Smuzhiyun #define BQ25975_BUSOVP_SC_MIN_uV 7000000 108*4882a593Smuzhiyun #define BQ25960_BUSOVP_SC_MIN_uV 7000000 109*4882a593Smuzhiyun #define BQ25980_BUSOVP_BYP_MIN_uV 7000000 110*4882a593Smuzhiyun #define BQ25975_BUSOVP_BYP_MIN_uV 3500000 111*4882a593Smuzhiyun #define BQ25960_BUSOVP_BYP_MIN_uV 3500000 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define BQ25980_BUSOVP_SC_MAX_uV 22000000 114*4882a593Smuzhiyun #define BQ25975_BUSOVP_SC_MAX_uV 12750000 115*4882a593Smuzhiyun #define BQ25960_BUSOVP_SC_MAX_uV 12750000 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define BQ25980_BUSOVP_BYP_MAX_uV 12750000 118*4882a593Smuzhiyun #define BQ25975_BUSOVP_BYP_MAX_uV 6500000 119*4882a593Smuzhiyun #define BQ25960_BUSOVP_BYP_MAX_uV 6500000 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define BQ25980_BATOVP_STEP_uV 20000 122*4882a593Smuzhiyun #define BQ25975_BATOVP_STEP_uV 10000 123*4882a593Smuzhiyun #define BQ25960_BATOVP_STEP_uV 10000 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define BQ25980_BATOVP_OFFSET_uV 7000000 126*4882a593Smuzhiyun #define BQ25975_BATOVP_OFFSET_uV 3500000 127*4882a593Smuzhiyun #define BQ25960_BATOVP_OFFSET_uV 3500000 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define BQ25980_BATOVP_DFLT_uV 14000000 130*4882a593Smuzhiyun #define BQ25975_BATOVP_DFLT_uV 8900000 131*4882a593Smuzhiyun #define BQ25960_BATOVP_DFLT_uV 8900000 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define BQ25980_BATOVP_MIN_uV 7000000 134*4882a593Smuzhiyun #define BQ25975_BATOVP_MIN_uV 3500000 135*4882a593Smuzhiyun #define BQ25960_BATOVP_MIN_uV 3500000 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define BQ25980_BATOVP_MAX_uV 9540000 138*4882a593Smuzhiyun #define BQ25975_BATOVP_MAX_uV 4770000 139*4882a593Smuzhiyun #define BQ25960_BATOVP_MAX_uV 4770000 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define BQ25980_BATOCP_STEP_uA 100000 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define BQ25980_BATOCP_MASK GENMASK(6, 0) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define BQ25980_BATOCP_DFLT_uA 8100000 146*4882a593Smuzhiyun #define BQ25960_BATOCP_DFLT_uA 6100000 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define BQ25980_BATOCP_MIN_uA 2000000 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define BQ25980_BATOCP_MAX_uA 11000000 151*4882a593Smuzhiyun #define BQ25975_BATOCP_MAX_uA 11000000 152*4882a593Smuzhiyun #define BQ25960_BATOCP_MAX_uA 7000000 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define BQ25980_ENABLE_HIZ 0xff 155*4882a593Smuzhiyun #define BQ25980_DISABLE_HIZ 0x0 156*4882a593Smuzhiyun #define BQ25980_EN_BYPASS BIT(3) 157*4882a593Smuzhiyun #define BQ25980_STAT1_OVP_MASK (BIT(6) | BIT(5) | BIT(0)) 158*4882a593Smuzhiyun #define BQ25980_STAT3_OVP_MASK (BIT(7) | BIT(6)) 159*4882a593Smuzhiyun #define BQ25980_STAT1_OCP_MASK BIT(3) 160*4882a593Smuzhiyun #define BQ25980_STAT2_OCP_MASK (BIT(6) | BIT(1)) 161*4882a593Smuzhiyun #define BQ25980_STAT4_TFLT_MASK GENMASK(5, 1) 162*4882a593Smuzhiyun #define BQ25980_WD_STAT BIT(0) 163*4882a593Smuzhiyun #define BQ25980_PRESENT_MASK GENMASK(4, 2) 164*4882a593Smuzhiyun #define BQ25980_CHG_EN BIT(4) 165*4882a593Smuzhiyun #define BQ25980_EN_HIZ BIT(6) 166*4882a593Smuzhiyun #define BQ25980_ADC_EN BIT(7) 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #define BQ25980_ADC_VOLT_STEP_uV 1000 169*4882a593Smuzhiyun #define BQ25980_ADC_CURR_STEP_uA 1000 170*4882a593Smuzhiyun #define BQ25980_ADC_POLARITY_BIT BIT(7) 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define BQ25980_WATCHDOG_MASK GENMASK(4, 3) 173*4882a593Smuzhiyun #define BQ25980_WATCHDOG_DIS BIT(2) 174*4882a593Smuzhiyun #define BQ25980_WATCHDOG_MAX 300000 175*4882a593Smuzhiyun #define BQ25980_WATCHDOG_MIN 0 176*4882a593Smuzhiyun #define BQ25980_NUM_WD_VAL 4 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #endif /* BQ25980_CHARGER_H */ 179