1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // BQ25980 Battery Charger Driver
3*4882a593Smuzhiyun // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/err.h>
6*4882a593Smuzhiyun #include <linux/i2c.h>
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/interrupt.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
12*4882a593Smuzhiyun #include <linux/power_supply.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/device.h>
17*4882a593Smuzhiyun #include <linux/moduleparam.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include "bq25980_charger.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct bq25980_state {
23*4882a593Smuzhiyun bool dischg;
24*4882a593Smuzhiyun bool ovp;
25*4882a593Smuzhiyun bool ocp;
26*4882a593Smuzhiyun bool wdt;
27*4882a593Smuzhiyun bool tflt;
28*4882a593Smuzhiyun bool online;
29*4882a593Smuzhiyun bool ce;
30*4882a593Smuzhiyun bool hiz;
31*4882a593Smuzhiyun bool bypass;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun u32 vbat_adc;
34*4882a593Smuzhiyun u32 vsys_adc;
35*4882a593Smuzhiyun u32 ibat_adc;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun enum bq25980_id {
39*4882a593Smuzhiyun BQ25980,
40*4882a593Smuzhiyun BQ25975,
41*4882a593Smuzhiyun BQ25960,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct bq25980_chip_info {
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun int model_id;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun const struct regmap_config *regmap_config;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun int busocp_def;
51*4882a593Smuzhiyun int busocp_sc_max;
52*4882a593Smuzhiyun int busocp_byp_max;
53*4882a593Smuzhiyun int busocp_sc_min;
54*4882a593Smuzhiyun int busocp_byp_min;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun int busovp_sc_def;
57*4882a593Smuzhiyun int busovp_byp_def;
58*4882a593Smuzhiyun int busovp_sc_step;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun int busovp_sc_offset;
61*4882a593Smuzhiyun int busovp_byp_step;
62*4882a593Smuzhiyun int busovp_byp_offset;
63*4882a593Smuzhiyun int busovp_sc_min;
64*4882a593Smuzhiyun int busovp_sc_max;
65*4882a593Smuzhiyun int busovp_byp_min;
66*4882a593Smuzhiyun int busovp_byp_max;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun int batovp_def;
69*4882a593Smuzhiyun int batovp_max;
70*4882a593Smuzhiyun int batovp_min;
71*4882a593Smuzhiyun int batovp_step;
72*4882a593Smuzhiyun int batovp_offset;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun int batocp_def;
75*4882a593Smuzhiyun int batocp_max;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun struct bq25980_init_data {
79*4882a593Smuzhiyun u32 ichg;
80*4882a593Smuzhiyun u32 bypass_ilim;
81*4882a593Smuzhiyun u32 sc_ilim;
82*4882a593Smuzhiyun u32 vreg;
83*4882a593Smuzhiyun u32 iterm;
84*4882a593Smuzhiyun u32 iprechg;
85*4882a593Smuzhiyun u32 bypass_vlim;
86*4882a593Smuzhiyun u32 sc_vlim;
87*4882a593Smuzhiyun u32 ichg_max;
88*4882a593Smuzhiyun u32 vreg_max;
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct bq25980_device {
92*4882a593Smuzhiyun struct i2c_client *client;
93*4882a593Smuzhiyun struct device *dev;
94*4882a593Smuzhiyun struct power_supply *charger;
95*4882a593Smuzhiyun struct power_supply *battery;
96*4882a593Smuzhiyun struct mutex lock;
97*4882a593Smuzhiyun struct regmap *regmap;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun char model_name[I2C_NAME_SIZE];
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct bq25980_init_data init_data;
102*4882a593Smuzhiyun const struct bq25980_chip_info *chip_info;
103*4882a593Smuzhiyun struct bq25980_state state;
104*4882a593Smuzhiyun int watchdog_timer;
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static struct reg_default bq25980_reg_defs[] = {
108*4882a593Smuzhiyun {BQ25980_BATOVP, 0x5A},
109*4882a593Smuzhiyun {BQ25980_BATOVP_ALM, 0x46},
110*4882a593Smuzhiyun {BQ25980_BATOCP, 0x51},
111*4882a593Smuzhiyun {BQ25980_BATOCP_ALM, 0x50},
112*4882a593Smuzhiyun {BQ25980_BATUCP_ALM, 0x28},
113*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_1, 0x0},
114*4882a593Smuzhiyun {BQ25980_BUSOVP, 0x26},
115*4882a593Smuzhiyun {BQ25980_BUSOVP_ALM, 0x22},
116*4882a593Smuzhiyun {BQ25980_BUSOCP, 0xD},
117*4882a593Smuzhiyun {BQ25980_BUSOCP_ALM, 0xC},
118*4882a593Smuzhiyun {BQ25980_TEMP_CONTROL, 0x30},
119*4882a593Smuzhiyun {BQ25980_TDIE_ALM, 0xC8},
120*4882a593Smuzhiyun {BQ25980_TSBUS_FLT, 0x15},
121*4882a593Smuzhiyun {BQ25980_TSBAT_FLG, 0x15},
122*4882a593Smuzhiyun {BQ25980_VAC_CONTROL, 0x0},
123*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_2, 0x0},
124*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_3, 0x20},
125*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_4, 0x1D},
126*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_5, 0x18},
127*4882a593Smuzhiyun {BQ25980_STAT1, 0x0},
128*4882a593Smuzhiyun {BQ25980_STAT2, 0x0},
129*4882a593Smuzhiyun {BQ25980_STAT3, 0x0},
130*4882a593Smuzhiyun {BQ25980_STAT4, 0x0},
131*4882a593Smuzhiyun {BQ25980_STAT5, 0x0},
132*4882a593Smuzhiyun {BQ25980_FLAG1, 0x0},
133*4882a593Smuzhiyun {BQ25980_FLAG2, 0x0},
134*4882a593Smuzhiyun {BQ25980_FLAG3, 0x0},
135*4882a593Smuzhiyun {BQ25980_FLAG4, 0x0},
136*4882a593Smuzhiyun {BQ25980_FLAG5, 0x0},
137*4882a593Smuzhiyun {BQ25980_MASK1, 0x0},
138*4882a593Smuzhiyun {BQ25980_MASK2, 0x0},
139*4882a593Smuzhiyun {BQ25980_MASK3, 0x0},
140*4882a593Smuzhiyun {BQ25980_MASK4, 0x0},
141*4882a593Smuzhiyun {BQ25980_MASK5, 0x0},
142*4882a593Smuzhiyun {BQ25980_DEVICE_INFO, 0x8},
143*4882a593Smuzhiyun {BQ25980_ADC_CONTROL1, 0x0},
144*4882a593Smuzhiyun {BQ25980_ADC_CONTROL2, 0x0},
145*4882a593Smuzhiyun {BQ25980_IBUS_ADC_LSB, 0x0},
146*4882a593Smuzhiyun {BQ25980_IBUS_ADC_MSB, 0x0},
147*4882a593Smuzhiyun {BQ25980_VBUS_ADC_LSB, 0x0},
148*4882a593Smuzhiyun {BQ25980_VBUS_ADC_MSB, 0x0},
149*4882a593Smuzhiyun {BQ25980_VAC1_ADC_LSB, 0x0},
150*4882a593Smuzhiyun {BQ25980_VAC2_ADC_LSB, 0x0},
151*4882a593Smuzhiyun {BQ25980_VOUT_ADC_LSB, 0x0},
152*4882a593Smuzhiyun {BQ25980_VBAT_ADC_LSB, 0x0},
153*4882a593Smuzhiyun {BQ25980_IBAT_ADC_MSB, 0x0},
154*4882a593Smuzhiyun {BQ25980_IBAT_ADC_LSB, 0x0},
155*4882a593Smuzhiyun {BQ25980_TSBUS_ADC_LSB, 0x0},
156*4882a593Smuzhiyun {BQ25980_TSBAT_ADC_LSB, 0x0},
157*4882a593Smuzhiyun {BQ25980_TDIE_ADC_LSB, 0x0},
158*4882a593Smuzhiyun {BQ25980_DEGLITCH_TIME, 0x0},
159*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_6, 0x0},
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static struct reg_default bq25975_reg_defs[] = {
163*4882a593Smuzhiyun {BQ25980_BATOVP, 0x5A},
164*4882a593Smuzhiyun {BQ25980_BATOVP_ALM, 0x46},
165*4882a593Smuzhiyun {BQ25980_BATOCP, 0x51},
166*4882a593Smuzhiyun {BQ25980_BATOCP_ALM, 0x50},
167*4882a593Smuzhiyun {BQ25980_BATUCP_ALM, 0x28},
168*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_1, 0x0},
169*4882a593Smuzhiyun {BQ25980_BUSOVP, 0x26},
170*4882a593Smuzhiyun {BQ25980_BUSOVP_ALM, 0x22},
171*4882a593Smuzhiyun {BQ25980_BUSOCP, 0xD},
172*4882a593Smuzhiyun {BQ25980_BUSOCP_ALM, 0xC},
173*4882a593Smuzhiyun {BQ25980_TEMP_CONTROL, 0x30},
174*4882a593Smuzhiyun {BQ25980_TDIE_ALM, 0xC8},
175*4882a593Smuzhiyun {BQ25980_TSBUS_FLT, 0x15},
176*4882a593Smuzhiyun {BQ25980_TSBAT_FLG, 0x15},
177*4882a593Smuzhiyun {BQ25980_VAC_CONTROL, 0x0},
178*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_2, 0x0},
179*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_3, 0x20},
180*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_4, 0x1D},
181*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_5, 0x18},
182*4882a593Smuzhiyun {BQ25980_STAT1, 0x0},
183*4882a593Smuzhiyun {BQ25980_STAT2, 0x0},
184*4882a593Smuzhiyun {BQ25980_STAT3, 0x0},
185*4882a593Smuzhiyun {BQ25980_STAT4, 0x0},
186*4882a593Smuzhiyun {BQ25980_STAT5, 0x0},
187*4882a593Smuzhiyun {BQ25980_FLAG1, 0x0},
188*4882a593Smuzhiyun {BQ25980_FLAG2, 0x0},
189*4882a593Smuzhiyun {BQ25980_FLAG3, 0x0},
190*4882a593Smuzhiyun {BQ25980_FLAG4, 0x0},
191*4882a593Smuzhiyun {BQ25980_FLAG5, 0x0},
192*4882a593Smuzhiyun {BQ25980_MASK1, 0x0},
193*4882a593Smuzhiyun {BQ25980_MASK2, 0x0},
194*4882a593Smuzhiyun {BQ25980_MASK3, 0x0},
195*4882a593Smuzhiyun {BQ25980_MASK4, 0x0},
196*4882a593Smuzhiyun {BQ25980_MASK5, 0x0},
197*4882a593Smuzhiyun {BQ25980_DEVICE_INFO, 0x8},
198*4882a593Smuzhiyun {BQ25980_ADC_CONTROL1, 0x0},
199*4882a593Smuzhiyun {BQ25980_ADC_CONTROL2, 0x0},
200*4882a593Smuzhiyun {BQ25980_IBUS_ADC_LSB, 0x0},
201*4882a593Smuzhiyun {BQ25980_IBUS_ADC_MSB, 0x0},
202*4882a593Smuzhiyun {BQ25980_VBUS_ADC_LSB, 0x0},
203*4882a593Smuzhiyun {BQ25980_VBUS_ADC_MSB, 0x0},
204*4882a593Smuzhiyun {BQ25980_VAC1_ADC_LSB, 0x0},
205*4882a593Smuzhiyun {BQ25980_VAC2_ADC_LSB, 0x0},
206*4882a593Smuzhiyun {BQ25980_VOUT_ADC_LSB, 0x0},
207*4882a593Smuzhiyun {BQ25980_VBAT_ADC_LSB, 0x0},
208*4882a593Smuzhiyun {BQ25980_IBAT_ADC_MSB, 0x0},
209*4882a593Smuzhiyun {BQ25980_IBAT_ADC_LSB, 0x0},
210*4882a593Smuzhiyun {BQ25980_TSBUS_ADC_LSB, 0x0},
211*4882a593Smuzhiyun {BQ25980_TSBAT_ADC_LSB, 0x0},
212*4882a593Smuzhiyun {BQ25980_TDIE_ADC_LSB, 0x0},
213*4882a593Smuzhiyun {BQ25980_DEGLITCH_TIME, 0x0},
214*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_6, 0x0},
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static struct reg_default bq25960_reg_defs[] = {
218*4882a593Smuzhiyun {BQ25980_BATOVP, 0x5A},
219*4882a593Smuzhiyun {BQ25980_BATOVP_ALM, 0x46},
220*4882a593Smuzhiyun {BQ25980_BATOCP, 0x51},
221*4882a593Smuzhiyun {BQ25980_BATOCP_ALM, 0x50},
222*4882a593Smuzhiyun {BQ25980_BATUCP_ALM, 0x28},
223*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_1, 0x0},
224*4882a593Smuzhiyun {BQ25980_BUSOVP, 0x26},
225*4882a593Smuzhiyun {BQ25980_BUSOVP_ALM, 0x22},
226*4882a593Smuzhiyun {BQ25980_BUSOCP, 0xD},
227*4882a593Smuzhiyun {BQ25980_BUSOCP_ALM, 0xC},
228*4882a593Smuzhiyun {BQ25980_TEMP_CONTROL, 0x30},
229*4882a593Smuzhiyun {BQ25980_TDIE_ALM, 0xC8},
230*4882a593Smuzhiyun {BQ25980_TSBUS_FLT, 0x15},
231*4882a593Smuzhiyun {BQ25980_TSBAT_FLG, 0x15},
232*4882a593Smuzhiyun {BQ25980_VAC_CONTROL, 0x0},
233*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_2, 0x0},
234*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_3, 0x20},
235*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_4, 0x1D},
236*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_5, 0x18},
237*4882a593Smuzhiyun {BQ25980_STAT1, 0x0},
238*4882a593Smuzhiyun {BQ25980_STAT2, 0x0},
239*4882a593Smuzhiyun {BQ25980_STAT3, 0x0},
240*4882a593Smuzhiyun {BQ25980_STAT4, 0x0},
241*4882a593Smuzhiyun {BQ25980_STAT5, 0x0},
242*4882a593Smuzhiyun {BQ25980_FLAG1, 0x0},
243*4882a593Smuzhiyun {BQ25980_FLAG2, 0x0},
244*4882a593Smuzhiyun {BQ25980_FLAG3, 0x0},
245*4882a593Smuzhiyun {BQ25980_FLAG4, 0x0},
246*4882a593Smuzhiyun {BQ25980_FLAG5, 0x0},
247*4882a593Smuzhiyun {BQ25980_MASK1, 0x0},
248*4882a593Smuzhiyun {BQ25980_MASK2, 0x0},
249*4882a593Smuzhiyun {BQ25980_MASK3, 0x0},
250*4882a593Smuzhiyun {BQ25980_MASK4, 0x0},
251*4882a593Smuzhiyun {BQ25980_MASK5, 0x0},
252*4882a593Smuzhiyun {BQ25980_DEVICE_INFO, 0x8},
253*4882a593Smuzhiyun {BQ25980_ADC_CONTROL1, 0x0},
254*4882a593Smuzhiyun {BQ25980_ADC_CONTROL2, 0x0},
255*4882a593Smuzhiyun {BQ25980_IBUS_ADC_LSB, 0x0},
256*4882a593Smuzhiyun {BQ25980_IBUS_ADC_MSB, 0x0},
257*4882a593Smuzhiyun {BQ25980_VBUS_ADC_LSB, 0x0},
258*4882a593Smuzhiyun {BQ25980_VBUS_ADC_MSB, 0x0},
259*4882a593Smuzhiyun {BQ25980_VAC1_ADC_LSB, 0x0},
260*4882a593Smuzhiyun {BQ25980_VAC2_ADC_LSB, 0x0},
261*4882a593Smuzhiyun {BQ25980_VOUT_ADC_LSB, 0x0},
262*4882a593Smuzhiyun {BQ25980_VBAT_ADC_LSB, 0x0},
263*4882a593Smuzhiyun {BQ25980_IBAT_ADC_MSB, 0x0},
264*4882a593Smuzhiyun {BQ25980_IBAT_ADC_LSB, 0x0},
265*4882a593Smuzhiyun {BQ25980_TSBUS_ADC_LSB, 0x0},
266*4882a593Smuzhiyun {BQ25980_TSBAT_ADC_LSB, 0x0},
267*4882a593Smuzhiyun {BQ25980_TDIE_ADC_LSB, 0x0},
268*4882a593Smuzhiyun {BQ25980_DEGLITCH_TIME, 0x0},
269*4882a593Smuzhiyun {BQ25980_CHRGR_CTRL_6, 0x0},
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun static int bq25980_watchdog_time[BQ25980_NUM_WD_VAL] = {5000, 10000, 50000,
273*4882a593Smuzhiyun 300000};
274*4882a593Smuzhiyun
bq25980_get_input_curr_lim(struct bq25980_device * bq)275*4882a593Smuzhiyun static int bq25980_get_input_curr_lim(struct bq25980_device *bq)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun unsigned int busocp_reg_code;
278*4882a593Smuzhiyun int ret;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_BUSOCP, &busocp_reg_code);
281*4882a593Smuzhiyun if (ret)
282*4882a593Smuzhiyun return ret;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun return (busocp_reg_code * BQ25980_BUSOCP_STEP_uA) + BQ25980_BUSOCP_OFFSET_uA;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
bq25980_set_hiz(struct bq25980_device * bq,int setting)287*4882a593Smuzhiyun static int bq25980_set_hiz(struct bq25980_device *bq, int setting)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun return regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
290*4882a593Smuzhiyun BQ25980_EN_HIZ, setting);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
bq25980_set_input_curr_lim(struct bq25980_device * bq,int busocp)293*4882a593Smuzhiyun static int bq25980_set_input_curr_lim(struct bq25980_device *bq, int busocp)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun unsigned int busocp_reg_code;
296*4882a593Smuzhiyun int ret;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun if (!busocp)
299*4882a593Smuzhiyun return bq25980_set_hiz(bq, BQ25980_ENABLE_HIZ);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun bq25980_set_hiz(bq, BQ25980_DISABLE_HIZ);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun if (busocp < BQ25980_BUSOCP_MIN_uA)
304*4882a593Smuzhiyun busocp = BQ25980_BUSOCP_MIN_uA;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun if (bq->state.bypass)
307*4882a593Smuzhiyun busocp = min(busocp, bq->chip_info->busocp_sc_max);
308*4882a593Smuzhiyun else
309*4882a593Smuzhiyun busocp = min(busocp, bq->chip_info->busocp_byp_max);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun busocp_reg_code = (busocp - BQ25980_BUSOCP_OFFSET_uA)
312*4882a593Smuzhiyun / BQ25980_BUSOCP_STEP_uA;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun ret = regmap_write(bq->regmap, BQ25980_BUSOCP, busocp_reg_code);
315*4882a593Smuzhiyun if (ret)
316*4882a593Smuzhiyun return ret;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun return regmap_write(bq->regmap, BQ25980_BUSOCP_ALM, busocp_reg_code);
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
bq25980_get_input_volt_lim(struct bq25980_device * bq)321*4882a593Smuzhiyun static int bq25980_get_input_volt_lim(struct bq25980_device *bq)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun unsigned int busovp_reg_code;
324*4882a593Smuzhiyun unsigned int busovp_offset;
325*4882a593Smuzhiyun unsigned int busovp_step;
326*4882a593Smuzhiyun int ret;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun if (bq->state.bypass) {
329*4882a593Smuzhiyun busovp_step = bq->chip_info->busovp_byp_step;
330*4882a593Smuzhiyun busovp_offset = bq->chip_info->busovp_byp_offset;
331*4882a593Smuzhiyun } else {
332*4882a593Smuzhiyun busovp_step = bq->chip_info->busovp_sc_step;
333*4882a593Smuzhiyun busovp_offset = bq->chip_info->busovp_sc_offset;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_BUSOVP, &busovp_reg_code);
337*4882a593Smuzhiyun if (ret)
338*4882a593Smuzhiyun return ret;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun return (busovp_reg_code * busovp_step) + busovp_offset;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
bq25980_set_input_volt_lim(struct bq25980_device * bq,int busovp)343*4882a593Smuzhiyun static int bq25980_set_input_volt_lim(struct bq25980_device *bq, int busovp)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun unsigned int busovp_reg_code;
346*4882a593Smuzhiyun unsigned int busovp_step;
347*4882a593Smuzhiyun unsigned int busovp_offset;
348*4882a593Smuzhiyun int ret;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun if (bq->state.bypass) {
351*4882a593Smuzhiyun busovp_step = bq->chip_info->busovp_byp_step;
352*4882a593Smuzhiyun busovp_offset = bq->chip_info->busovp_byp_offset;
353*4882a593Smuzhiyun if (busovp > bq->chip_info->busovp_byp_max)
354*4882a593Smuzhiyun busovp = bq->chip_info->busovp_byp_max;
355*4882a593Smuzhiyun else if (busovp < bq->chip_info->busovp_byp_min)
356*4882a593Smuzhiyun busovp = bq->chip_info->busovp_byp_min;
357*4882a593Smuzhiyun } else {
358*4882a593Smuzhiyun busovp_step = bq->chip_info->busovp_sc_step;
359*4882a593Smuzhiyun busovp_offset = bq->chip_info->busovp_sc_offset;
360*4882a593Smuzhiyun if (busovp > bq->chip_info->busovp_sc_max)
361*4882a593Smuzhiyun busovp = bq->chip_info->busovp_sc_max;
362*4882a593Smuzhiyun else if (busovp < bq->chip_info->busovp_sc_min)
363*4882a593Smuzhiyun busovp = bq->chip_info->busovp_sc_min;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun busovp_reg_code = (busovp - busovp_offset) / busovp_step;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun ret = regmap_write(bq->regmap, BQ25980_BUSOVP, busovp_reg_code);
369*4882a593Smuzhiyun if (ret)
370*4882a593Smuzhiyun return ret;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun return regmap_write(bq->regmap, BQ25980_BUSOVP_ALM, busovp_reg_code);
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
bq25980_get_const_charge_curr(struct bq25980_device * bq)375*4882a593Smuzhiyun static int bq25980_get_const_charge_curr(struct bq25980_device *bq)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun unsigned int batocp_reg_code;
378*4882a593Smuzhiyun int ret;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_BATOCP, &batocp_reg_code);
381*4882a593Smuzhiyun if (ret)
382*4882a593Smuzhiyun return ret;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun return (batocp_reg_code & BQ25980_BATOCP_MASK) *
385*4882a593Smuzhiyun BQ25980_BATOCP_STEP_uA;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
bq25980_set_const_charge_curr(struct bq25980_device * bq,int batocp)388*4882a593Smuzhiyun static int bq25980_set_const_charge_curr(struct bq25980_device *bq, int batocp)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun unsigned int batocp_reg_code;
391*4882a593Smuzhiyun int ret;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun batocp = max(batocp, BQ25980_BATOCP_MIN_uA);
394*4882a593Smuzhiyun batocp = min(batocp, bq->chip_info->batocp_max);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun batocp_reg_code = batocp / BQ25980_BATOCP_STEP_uA;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun ret = regmap_update_bits(bq->regmap, BQ25980_BATOCP,
399*4882a593Smuzhiyun BQ25980_BATOCP_MASK, batocp_reg_code);
400*4882a593Smuzhiyun if (ret)
401*4882a593Smuzhiyun return ret;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun return regmap_update_bits(bq->regmap, BQ25980_BATOCP_ALM,
404*4882a593Smuzhiyun BQ25980_BATOCP_MASK, batocp_reg_code);
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
bq25980_get_const_charge_volt(struct bq25980_device * bq)407*4882a593Smuzhiyun static int bq25980_get_const_charge_volt(struct bq25980_device *bq)
408*4882a593Smuzhiyun {
409*4882a593Smuzhiyun unsigned int batovp_reg_code;
410*4882a593Smuzhiyun int ret;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_BATOVP, &batovp_reg_code);
413*4882a593Smuzhiyun if (ret)
414*4882a593Smuzhiyun return ret;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun return ((batovp_reg_code * bq->chip_info->batovp_step) +
417*4882a593Smuzhiyun bq->chip_info->batovp_offset);
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
bq25980_set_const_charge_volt(struct bq25980_device * bq,int batovp)420*4882a593Smuzhiyun static int bq25980_set_const_charge_volt(struct bq25980_device *bq, int batovp)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun unsigned int batovp_reg_code;
423*4882a593Smuzhiyun int ret;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (batovp < bq->chip_info->batovp_min)
426*4882a593Smuzhiyun batovp = bq->chip_info->batovp_min;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (batovp > bq->chip_info->batovp_max)
429*4882a593Smuzhiyun batovp = bq->chip_info->batovp_max;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun batovp_reg_code = (batovp - bq->chip_info->batovp_offset) /
432*4882a593Smuzhiyun bq->chip_info->batovp_step;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun ret = regmap_write(bq->regmap, BQ25980_BATOVP, batovp_reg_code);
435*4882a593Smuzhiyun if (ret)
436*4882a593Smuzhiyun return ret;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun return regmap_write(bq->regmap, BQ25980_BATOVP_ALM, batovp_reg_code);
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
bq25980_set_bypass(struct bq25980_device * bq,bool en_bypass)441*4882a593Smuzhiyun static int bq25980_set_bypass(struct bq25980_device *bq, bool en_bypass)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun int ret;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun if (en_bypass)
446*4882a593Smuzhiyun ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
447*4882a593Smuzhiyun BQ25980_EN_BYPASS, BQ25980_EN_BYPASS);
448*4882a593Smuzhiyun else
449*4882a593Smuzhiyun ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
450*4882a593Smuzhiyun BQ25980_EN_BYPASS, en_bypass);
451*4882a593Smuzhiyun if (ret)
452*4882a593Smuzhiyun return ret;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun bq->state.bypass = en_bypass;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun return bq->state.bypass;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
bq25980_set_chg_en(struct bq25980_device * bq,bool en_chg)459*4882a593Smuzhiyun static int bq25980_set_chg_en(struct bq25980_device *bq, bool en_chg)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun int ret;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun if (en_chg)
464*4882a593Smuzhiyun ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
465*4882a593Smuzhiyun BQ25980_CHG_EN, BQ25980_CHG_EN);
466*4882a593Smuzhiyun else
467*4882a593Smuzhiyun ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
468*4882a593Smuzhiyun BQ25980_CHG_EN, en_chg);
469*4882a593Smuzhiyun if (ret)
470*4882a593Smuzhiyun return ret;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun bq->state.ce = en_chg;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun return 0;
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun
bq25980_get_adc_ibus(struct bq25980_device * bq)477*4882a593Smuzhiyun static int bq25980_get_adc_ibus(struct bq25980_device *bq)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun int ibus_adc_lsb, ibus_adc_msb;
480*4882a593Smuzhiyun u16 ibus_adc;
481*4882a593Smuzhiyun int ret;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_IBUS_ADC_MSB, &ibus_adc_msb);
484*4882a593Smuzhiyun if (ret)
485*4882a593Smuzhiyun return ret;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_IBUS_ADC_LSB, &ibus_adc_lsb);
488*4882a593Smuzhiyun if (ret)
489*4882a593Smuzhiyun return ret;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun ibus_adc = (ibus_adc_msb << 8) | ibus_adc_lsb;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun if (ibus_adc_msb & BQ25980_ADC_POLARITY_BIT)
494*4882a593Smuzhiyun return ((ibus_adc ^ 0xffff) + 1) * BQ25980_ADC_CURR_STEP_uA;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun return ibus_adc * BQ25980_ADC_CURR_STEP_uA;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
bq25980_get_adc_vbus(struct bq25980_device * bq)499*4882a593Smuzhiyun static int bq25980_get_adc_vbus(struct bq25980_device *bq)
500*4882a593Smuzhiyun {
501*4882a593Smuzhiyun int vbus_adc_lsb, vbus_adc_msb;
502*4882a593Smuzhiyun u16 vbus_adc;
503*4882a593Smuzhiyun int ret;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_VBUS_ADC_MSB, &vbus_adc_msb);
506*4882a593Smuzhiyun if (ret)
507*4882a593Smuzhiyun return ret;
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_VBUS_ADC_LSB, &vbus_adc_lsb);
510*4882a593Smuzhiyun if (ret)
511*4882a593Smuzhiyun return ret;
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun vbus_adc = (vbus_adc_msb << 8) | vbus_adc_lsb;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun return vbus_adc * BQ25980_ADC_VOLT_STEP_uV;
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun
bq25980_get_ibat_adc(struct bq25980_device * bq)518*4882a593Smuzhiyun static int bq25980_get_ibat_adc(struct bq25980_device *bq)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun int ret;
521*4882a593Smuzhiyun int ibat_adc_lsb, ibat_adc_msb;
522*4882a593Smuzhiyun int ibat_adc;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_IBAT_ADC_MSB, &ibat_adc_msb);
525*4882a593Smuzhiyun if (ret)
526*4882a593Smuzhiyun return ret;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_IBAT_ADC_LSB, &ibat_adc_lsb);
529*4882a593Smuzhiyun if (ret)
530*4882a593Smuzhiyun return ret;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun ibat_adc = (ibat_adc_msb << 8) | ibat_adc_lsb;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun if (ibat_adc_msb & BQ25980_ADC_POLARITY_BIT)
535*4882a593Smuzhiyun return ((ibat_adc ^ 0xffff) + 1) * BQ25980_ADC_CURR_STEP_uA;
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun return ibat_adc * BQ25980_ADC_CURR_STEP_uA;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun
bq25980_get_adc_vbat(struct bq25980_device * bq)540*4882a593Smuzhiyun static int bq25980_get_adc_vbat(struct bq25980_device *bq)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun int vsys_adc_lsb, vsys_adc_msb;
543*4882a593Smuzhiyun u16 vsys_adc;
544*4882a593Smuzhiyun int ret;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_VBAT_ADC_MSB, &vsys_adc_msb);
547*4882a593Smuzhiyun if (ret)
548*4882a593Smuzhiyun return ret;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_VBAT_ADC_LSB, &vsys_adc_lsb);
551*4882a593Smuzhiyun if (ret)
552*4882a593Smuzhiyun return ret;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun vsys_adc = (vsys_adc_msb << 8) | vsys_adc_lsb;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun return vsys_adc * BQ25980_ADC_VOLT_STEP_uV;
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun
bq25980_get_state(struct bq25980_device * bq,struct bq25980_state * state)559*4882a593Smuzhiyun static int bq25980_get_state(struct bq25980_device *bq,
560*4882a593Smuzhiyun struct bq25980_state *state)
561*4882a593Smuzhiyun {
562*4882a593Smuzhiyun unsigned int chg_ctrl_2;
563*4882a593Smuzhiyun unsigned int stat1;
564*4882a593Smuzhiyun unsigned int stat2;
565*4882a593Smuzhiyun unsigned int stat3;
566*4882a593Smuzhiyun unsigned int stat4;
567*4882a593Smuzhiyun unsigned int ibat_adc_msb;
568*4882a593Smuzhiyun int ret;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_STAT1, &stat1);
571*4882a593Smuzhiyun if (ret)
572*4882a593Smuzhiyun return ret;
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_STAT2, &stat2);
575*4882a593Smuzhiyun if (ret)
576*4882a593Smuzhiyun return ret;
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_STAT3, &stat3);
579*4882a593Smuzhiyun if (ret)
580*4882a593Smuzhiyun return ret;
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_STAT4, &stat4);
583*4882a593Smuzhiyun if (ret)
584*4882a593Smuzhiyun return ret;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_CHRGR_CTRL_2, &chg_ctrl_2);
587*4882a593Smuzhiyun if (ret)
588*4882a593Smuzhiyun return ret;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun ret = regmap_read(bq->regmap, BQ25980_IBAT_ADC_MSB, &ibat_adc_msb);
591*4882a593Smuzhiyun if (ret)
592*4882a593Smuzhiyun return ret;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun state->dischg = ibat_adc_msb & BQ25980_ADC_POLARITY_BIT;
595*4882a593Smuzhiyun state->ovp = (stat1 & BQ25980_STAT1_OVP_MASK) |
596*4882a593Smuzhiyun (stat3 & BQ25980_STAT3_OVP_MASK);
597*4882a593Smuzhiyun state->ocp = (stat1 & BQ25980_STAT1_OCP_MASK) |
598*4882a593Smuzhiyun (stat2 & BQ25980_STAT2_OCP_MASK);
599*4882a593Smuzhiyun state->tflt = stat4 & BQ25980_STAT4_TFLT_MASK;
600*4882a593Smuzhiyun state->wdt = stat4 & BQ25980_WD_STAT;
601*4882a593Smuzhiyun state->online = stat3 & BQ25980_PRESENT_MASK;
602*4882a593Smuzhiyun state->ce = chg_ctrl_2 & BQ25980_CHG_EN;
603*4882a593Smuzhiyun state->hiz = chg_ctrl_2 & BQ25980_EN_HIZ;
604*4882a593Smuzhiyun state->bypass = chg_ctrl_2 & BQ25980_EN_BYPASS;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun return 0;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun
bq25980_get_battery_property(struct power_supply * psy,enum power_supply_property psp,union power_supply_propval * val)609*4882a593Smuzhiyun static int bq25980_get_battery_property(struct power_supply *psy,
610*4882a593Smuzhiyun enum power_supply_property psp,
611*4882a593Smuzhiyun union power_supply_propval *val)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun struct bq25980_device *bq = power_supply_get_drvdata(psy);
614*4882a593Smuzhiyun int ret = 0;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun switch (psp) {
617*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
618*4882a593Smuzhiyun val->intval = bq->init_data.ichg_max;
619*4882a593Smuzhiyun break;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX:
622*4882a593Smuzhiyun val->intval = bq->init_data.vreg_max;
623*4882a593Smuzhiyun break;
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CURRENT_NOW:
626*4882a593Smuzhiyun ret = bq25980_get_ibat_adc(bq);
627*4882a593Smuzhiyun val->intval = ret;
628*4882a593Smuzhiyun break;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun case POWER_SUPPLY_PROP_VOLTAGE_NOW:
631*4882a593Smuzhiyun ret = bq25980_get_adc_vbat(bq);
632*4882a593Smuzhiyun if (ret < 0)
633*4882a593Smuzhiyun return ret;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun val->intval = ret;
636*4882a593Smuzhiyun break;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun default:
639*4882a593Smuzhiyun return -EINVAL;
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun return ret;
643*4882a593Smuzhiyun }
644*4882a593Smuzhiyun
bq25980_set_charger_property(struct power_supply * psy,enum power_supply_property prop,const union power_supply_propval * val)645*4882a593Smuzhiyun static int bq25980_set_charger_property(struct power_supply *psy,
646*4882a593Smuzhiyun enum power_supply_property prop,
647*4882a593Smuzhiyun const union power_supply_propval *val)
648*4882a593Smuzhiyun {
649*4882a593Smuzhiyun struct bq25980_device *bq = power_supply_get_drvdata(psy);
650*4882a593Smuzhiyun int ret = -EINVAL;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun switch (prop) {
653*4882a593Smuzhiyun case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
654*4882a593Smuzhiyun ret = bq25980_set_input_curr_lim(bq, val->intval);
655*4882a593Smuzhiyun if (ret)
656*4882a593Smuzhiyun return ret;
657*4882a593Smuzhiyun break;
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
660*4882a593Smuzhiyun ret = bq25980_set_input_volt_lim(bq, val->intval);
661*4882a593Smuzhiyun if (ret)
662*4882a593Smuzhiyun return ret;
663*4882a593Smuzhiyun break;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CHARGE_TYPE:
666*4882a593Smuzhiyun ret = bq25980_set_bypass(bq, val->intval);
667*4882a593Smuzhiyun if (ret)
668*4882a593Smuzhiyun return ret;
669*4882a593Smuzhiyun break;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun case POWER_SUPPLY_PROP_STATUS:
672*4882a593Smuzhiyun ret = bq25980_set_chg_en(bq, val->intval);
673*4882a593Smuzhiyun if (ret)
674*4882a593Smuzhiyun return ret;
675*4882a593Smuzhiyun break;
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
678*4882a593Smuzhiyun ret = bq25980_set_const_charge_curr(bq, val->intval);
679*4882a593Smuzhiyun if (ret)
680*4882a593Smuzhiyun return ret;
681*4882a593Smuzhiyun break;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
684*4882a593Smuzhiyun ret = bq25980_set_const_charge_volt(bq, val->intval);
685*4882a593Smuzhiyun if (ret)
686*4882a593Smuzhiyun return ret;
687*4882a593Smuzhiyun break;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun default:
690*4882a593Smuzhiyun return -EINVAL;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun return ret;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
bq25980_get_charger_property(struct power_supply * psy,enum power_supply_property psp,union power_supply_propval * val)696*4882a593Smuzhiyun static int bq25980_get_charger_property(struct power_supply *psy,
697*4882a593Smuzhiyun enum power_supply_property psp,
698*4882a593Smuzhiyun union power_supply_propval *val)
699*4882a593Smuzhiyun {
700*4882a593Smuzhiyun struct bq25980_device *bq = power_supply_get_drvdata(psy);
701*4882a593Smuzhiyun struct bq25980_state state;
702*4882a593Smuzhiyun int ret = 0;
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun mutex_lock(&bq->lock);
705*4882a593Smuzhiyun ret = bq25980_get_state(bq, &state);
706*4882a593Smuzhiyun mutex_unlock(&bq->lock);
707*4882a593Smuzhiyun if (ret)
708*4882a593Smuzhiyun return ret;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun switch (psp) {
711*4882a593Smuzhiyun case POWER_SUPPLY_PROP_MANUFACTURER:
712*4882a593Smuzhiyun val->strval = BQ25980_MANUFACTURER;
713*4882a593Smuzhiyun break;
714*4882a593Smuzhiyun case POWER_SUPPLY_PROP_MODEL_NAME:
715*4882a593Smuzhiyun val->strval = bq->model_name;
716*4882a593Smuzhiyun break;
717*4882a593Smuzhiyun case POWER_SUPPLY_PROP_ONLINE:
718*4882a593Smuzhiyun val->intval = state.online;
719*4882a593Smuzhiyun break;
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
722*4882a593Smuzhiyun ret = bq25980_get_input_volt_lim(bq);
723*4882a593Smuzhiyun if (ret < 0)
724*4882a593Smuzhiyun return ret;
725*4882a593Smuzhiyun val->intval = ret;
726*4882a593Smuzhiyun break;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
729*4882a593Smuzhiyun ret = bq25980_get_input_curr_lim(bq);
730*4882a593Smuzhiyun if (ret < 0)
731*4882a593Smuzhiyun return ret;
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun val->intval = ret;
734*4882a593Smuzhiyun break;
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun case POWER_SUPPLY_PROP_HEALTH:
737*4882a593Smuzhiyun val->intval = POWER_SUPPLY_HEALTH_GOOD;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun if (state.tflt)
740*4882a593Smuzhiyun val->intval = POWER_SUPPLY_HEALTH_OVERHEAT;
741*4882a593Smuzhiyun else if (state.ovp)
742*4882a593Smuzhiyun val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE;
743*4882a593Smuzhiyun else if (state.ocp)
744*4882a593Smuzhiyun val->intval = POWER_SUPPLY_HEALTH_OVERCURRENT;
745*4882a593Smuzhiyun else if (state.wdt)
746*4882a593Smuzhiyun val->intval =
747*4882a593Smuzhiyun POWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE;
748*4882a593Smuzhiyun break;
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun case POWER_SUPPLY_PROP_STATUS:
751*4882a593Smuzhiyun val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun if ((state.ce) && (!state.hiz))
754*4882a593Smuzhiyun val->intval = POWER_SUPPLY_STATUS_CHARGING;
755*4882a593Smuzhiyun else if (state.dischg)
756*4882a593Smuzhiyun val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
757*4882a593Smuzhiyun else if (!state.ce)
758*4882a593Smuzhiyun val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
759*4882a593Smuzhiyun break;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CHARGE_TYPE:
762*4882a593Smuzhiyun val->intval = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun if (!state.ce)
765*4882a593Smuzhiyun val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE;
766*4882a593Smuzhiyun else if (state.bypass)
767*4882a593Smuzhiyun val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST;
768*4882a593Smuzhiyun else if (!state.bypass)
769*4882a593Smuzhiyun val->intval = POWER_SUPPLY_CHARGE_TYPE_STANDARD;
770*4882a593Smuzhiyun break;
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CURRENT_NOW:
773*4882a593Smuzhiyun ret = bq25980_get_adc_ibus(bq);
774*4882a593Smuzhiyun if (ret < 0)
775*4882a593Smuzhiyun return ret;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun val->intval = ret;
778*4882a593Smuzhiyun break;
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun case POWER_SUPPLY_PROP_VOLTAGE_NOW:
781*4882a593Smuzhiyun ret = bq25980_get_adc_vbus(bq);
782*4882a593Smuzhiyun if (ret < 0)
783*4882a593Smuzhiyun return ret;
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun val->intval = ret;
786*4882a593Smuzhiyun break;
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
789*4882a593Smuzhiyun ret = bq25980_get_const_charge_curr(bq);
790*4882a593Smuzhiyun if (ret < 0)
791*4882a593Smuzhiyun return ret;
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun val->intval = ret;
794*4882a593Smuzhiyun break;
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
797*4882a593Smuzhiyun ret = bq25980_get_const_charge_volt(bq);
798*4882a593Smuzhiyun if (ret < 0)
799*4882a593Smuzhiyun return ret;
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun val->intval = ret;
802*4882a593Smuzhiyun break;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun default:
805*4882a593Smuzhiyun return -EINVAL;
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun return ret;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun
bq25980_state_changed(struct bq25980_device * bq,struct bq25980_state * new_state)811*4882a593Smuzhiyun static bool bq25980_state_changed(struct bq25980_device *bq,
812*4882a593Smuzhiyun struct bq25980_state *new_state)
813*4882a593Smuzhiyun {
814*4882a593Smuzhiyun struct bq25980_state old_state;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun mutex_lock(&bq->lock);
817*4882a593Smuzhiyun old_state = bq->state;
818*4882a593Smuzhiyun mutex_unlock(&bq->lock);
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun return (old_state.dischg != new_state->dischg ||
821*4882a593Smuzhiyun old_state.ovp != new_state->ovp ||
822*4882a593Smuzhiyun old_state.ocp != new_state->ocp ||
823*4882a593Smuzhiyun old_state.online != new_state->online ||
824*4882a593Smuzhiyun old_state.wdt != new_state->wdt ||
825*4882a593Smuzhiyun old_state.tflt != new_state->tflt ||
826*4882a593Smuzhiyun old_state.ce != new_state->ce ||
827*4882a593Smuzhiyun old_state.hiz != new_state->hiz ||
828*4882a593Smuzhiyun old_state.bypass != new_state->bypass);
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun
bq25980_irq_handler_thread(int irq,void * private)831*4882a593Smuzhiyun static irqreturn_t bq25980_irq_handler_thread(int irq, void *private)
832*4882a593Smuzhiyun {
833*4882a593Smuzhiyun struct bq25980_device *bq = private;
834*4882a593Smuzhiyun struct bq25980_state state;
835*4882a593Smuzhiyun int ret;
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun ret = bq25980_get_state(bq, &state);
838*4882a593Smuzhiyun if (ret < 0)
839*4882a593Smuzhiyun goto irq_out;
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun if (!bq25980_state_changed(bq, &state))
842*4882a593Smuzhiyun goto irq_out;
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun mutex_lock(&bq->lock);
845*4882a593Smuzhiyun bq->state = state;
846*4882a593Smuzhiyun mutex_unlock(&bq->lock);
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun power_supply_changed(bq->charger);
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun irq_out:
851*4882a593Smuzhiyun return IRQ_HANDLED;
852*4882a593Smuzhiyun }
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun static enum power_supply_property bq25980_power_supply_props[] = {
855*4882a593Smuzhiyun POWER_SUPPLY_PROP_MANUFACTURER,
856*4882a593Smuzhiyun POWER_SUPPLY_PROP_MODEL_NAME,
857*4882a593Smuzhiyun POWER_SUPPLY_PROP_STATUS,
858*4882a593Smuzhiyun POWER_SUPPLY_PROP_ONLINE,
859*4882a593Smuzhiyun POWER_SUPPLY_PROP_HEALTH,
860*4882a593Smuzhiyun POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT,
861*4882a593Smuzhiyun POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
862*4882a593Smuzhiyun POWER_SUPPLY_PROP_CHARGE_TYPE,
863*4882a593Smuzhiyun POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
864*4882a593Smuzhiyun POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE,
865*4882a593Smuzhiyun POWER_SUPPLY_PROP_CURRENT_NOW,
866*4882a593Smuzhiyun POWER_SUPPLY_PROP_VOLTAGE_NOW,
867*4882a593Smuzhiyun };
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun static enum power_supply_property bq25980_battery_props[] = {
870*4882a593Smuzhiyun POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
871*4882a593Smuzhiyun POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX,
872*4882a593Smuzhiyun POWER_SUPPLY_PROP_CURRENT_NOW,
873*4882a593Smuzhiyun POWER_SUPPLY_PROP_VOLTAGE_NOW,
874*4882a593Smuzhiyun };
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun static char *bq25980_charger_supplied_to[] = {
877*4882a593Smuzhiyun "main-battery",
878*4882a593Smuzhiyun };
879*4882a593Smuzhiyun
bq25980_property_is_writeable(struct power_supply * psy,enum power_supply_property prop)880*4882a593Smuzhiyun static int bq25980_property_is_writeable(struct power_supply *psy,
881*4882a593Smuzhiyun enum power_supply_property prop)
882*4882a593Smuzhiyun {
883*4882a593Smuzhiyun switch (prop) {
884*4882a593Smuzhiyun case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
885*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
886*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
887*4882a593Smuzhiyun case POWER_SUPPLY_PROP_CHARGE_TYPE:
888*4882a593Smuzhiyun case POWER_SUPPLY_PROP_STATUS:
889*4882a593Smuzhiyun case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
890*4882a593Smuzhiyun return true;
891*4882a593Smuzhiyun default:
892*4882a593Smuzhiyun return false;
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun static const struct power_supply_desc bq25980_power_supply_desc = {
897*4882a593Smuzhiyun .name = "bq25980-charger",
898*4882a593Smuzhiyun .type = POWER_SUPPLY_TYPE_MAINS,
899*4882a593Smuzhiyun .properties = bq25980_power_supply_props,
900*4882a593Smuzhiyun .num_properties = ARRAY_SIZE(bq25980_power_supply_props),
901*4882a593Smuzhiyun .get_property = bq25980_get_charger_property,
902*4882a593Smuzhiyun .set_property = bq25980_set_charger_property,
903*4882a593Smuzhiyun .property_is_writeable = bq25980_property_is_writeable,
904*4882a593Smuzhiyun };
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun static struct power_supply_desc bq25980_battery_desc = {
907*4882a593Smuzhiyun .name = "bq25980-battery",
908*4882a593Smuzhiyun .type = POWER_SUPPLY_TYPE_BATTERY,
909*4882a593Smuzhiyun .get_property = bq25980_get_battery_property,
910*4882a593Smuzhiyun .properties = bq25980_battery_props,
911*4882a593Smuzhiyun .num_properties = ARRAY_SIZE(bq25980_battery_props),
912*4882a593Smuzhiyun .property_is_writeable = bq25980_property_is_writeable,
913*4882a593Smuzhiyun };
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun
bq25980_is_volatile_reg(struct device * dev,unsigned int reg)916*4882a593Smuzhiyun static bool bq25980_is_volatile_reg(struct device *dev, unsigned int reg)
917*4882a593Smuzhiyun {
918*4882a593Smuzhiyun switch (reg) {
919*4882a593Smuzhiyun case BQ25980_CHRGR_CTRL_2:
920*4882a593Smuzhiyun case BQ25980_STAT1...BQ25980_FLAG5:
921*4882a593Smuzhiyun case BQ25980_ADC_CONTROL1...BQ25980_TDIE_ADC_LSB:
922*4882a593Smuzhiyun return true;
923*4882a593Smuzhiyun default:
924*4882a593Smuzhiyun return false;
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun static const struct regmap_config bq25980_regmap_config = {
929*4882a593Smuzhiyun .reg_bits = 8,
930*4882a593Smuzhiyun .val_bits = 8,
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun .max_register = BQ25980_CHRGR_CTRL_6,
933*4882a593Smuzhiyun .reg_defaults = bq25980_reg_defs,
934*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(bq25980_reg_defs),
935*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
936*4882a593Smuzhiyun .volatile_reg = bq25980_is_volatile_reg,
937*4882a593Smuzhiyun };
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun static const struct regmap_config bq25975_regmap_config = {
940*4882a593Smuzhiyun .reg_bits = 8,
941*4882a593Smuzhiyun .val_bits = 8,
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun .max_register = BQ25980_CHRGR_CTRL_6,
944*4882a593Smuzhiyun .reg_defaults = bq25975_reg_defs,
945*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(bq25975_reg_defs),
946*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
947*4882a593Smuzhiyun .volatile_reg = bq25980_is_volatile_reg,
948*4882a593Smuzhiyun };
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun static const struct regmap_config bq25960_regmap_config = {
951*4882a593Smuzhiyun .reg_bits = 8,
952*4882a593Smuzhiyun .val_bits = 8,
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun .max_register = BQ25980_CHRGR_CTRL_6,
955*4882a593Smuzhiyun .reg_defaults = bq25960_reg_defs,
956*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(bq25960_reg_defs),
957*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
958*4882a593Smuzhiyun .volatile_reg = bq25980_is_volatile_reg,
959*4882a593Smuzhiyun };
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun static const struct bq25980_chip_info bq25980_chip_info_tbl[] = {
962*4882a593Smuzhiyun [BQ25980] = {
963*4882a593Smuzhiyun .model_id = BQ25980,
964*4882a593Smuzhiyun .regmap_config = &bq25980_regmap_config,
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun .busocp_def = BQ25980_BUSOCP_DFLT_uA,
967*4882a593Smuzhiyun .busocp_sc_min = BQ25960_BUSOCP_SC_MAX_uA,
968*4882a593Smuzhiyun .busocp_sc_max = BQ25980_BUSOCP_SC_MAX_uA,
969*4882a593Smuzhiyun .busocp_byp_max = BQ25980_BUSOCP_BYP_MAX_uA,
970*4882a593Smuzhiyun .busocp_byp_min = BQ25980_BUSOCP_MIN_uA,
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun .busovp_sc_def = BQ25980_BUSOVP_DFLT_uV,
973*4882a593Smuzhiyun .busovp_byp_def = BQ25980_BUSOVP_BYPASS_DFLT_uV,
974*4882a593Smuzhiyun .busovp_sc_step = BQ25980_BUSOVP_SC_STEP_uV,
975*4882a593Smuzhiyun .busovp_sc_offset = BQ25980_BUSOVP_SC_OFFSET_uV,
976*4882a593Smuzhiyun .busovp_byp_step = BQ25980_BUSOVP_BYP_STEP_uV,
977*4882a593Smuzhiyun .busovp_byp_offset = BQ25980_BUSOVP_BYP_OFFSET_uV,
978*4882a593Smuzhiyun .busovp_sc_min = BQ25980_BUSOVP_SC_MIN_uV,
979*4882a593Smuzhiyun .busovp_sc_max = BQ25980_BUSOVP_SC_MAX_uV,
980*4882a593Smuzhiyun .busovp_byp_min = BQ25980_BUSOVP_BYP_MIN_uV,
981*4882a593Smuzhiyun .busovp_byp_max = BQ25980_BUSOVP_BYP_MAX_uV,
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun .batovp_def = BQ25980_BATOVP_DFLT_uV,
984*4882a593Smuzhiyun .batovp_max = BQ25980_BATOVP_MAX_uV,
985*4882a593Smuzhiyun .batovp_min = BQ25980_BATOVP_MIN_uV,
986*4882a593Smuzhiyun .batovp_step = BQ25980_BATOVP_STEP_uV,
987*4882a593Smuzhiyun .batovp_offset = BQ25980_BATOVP_OFFSET_uV,
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun .batocp_def = BQ25980_BATOCP_DFLT_uA,
990*4882a593Smuzhiyun .batocp_max = BQ25980_BATOCP_MAX_uA,
991*4882a593Smuzhiyun },
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun [BQ25975] = {
994*4882a593Smuzhiyun .model_id = BQ25975,
995*4882a593Smuzhiyun .regmap_config = &bq25975_regmap_config,
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun .busocp_def = BQ25975_BUSOCP_DFLT_uA,
998*4882a593Smuzhiyun .busocp_sc_min = BQ25975_BUSOCP_SC_MAX_uA,
999*4882a593Smuzhiyun .busocp_sc_max = BQ25975_BUSOCP_SC_MAX_uA,
1000*4882a593Smuzhiyun .busocp_byp_min = BQ25980_BUSOCP_MIN_uA,
1001*4882a593Smuzhiyun .busocp_byp_max = BQ25975_BUSOCP_BYP_MAX_uA,
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun .busovp_sc_def = BQ25975_BUSOVP_DFLT_uV,
1004*4882a593Smuzhiyun .busovp_byp_def = BQ25975_BUSOVP_BYPASS_DFLT_uV,
1005*4882a593Smuzhiyun .busovp_sc_step = BQ25975_BUSOVP_SC_STEP_uV,
1006*4882a593Smuzhiyun .busovp_sc_offset = BQ25975_BUSOVP_SC_OFFSET_uV,
1007*4882a593Smuzhiyun .busovp_byp_step = BQ25975_BUSOVP_BYP_STEP_uV,
1008*4882a593Smuzhiyun .busovp_byp_offset = BQ25975_BUSOVP_BYP_OFFSET_uV,
1009*4882a593Smuzhiyun .busovp_sc_min = BQ25975_BUSOVP_SC_MIN_uV,
1010*4882a593Smuzhiyun .busovp_sc_max = BQ25975_BUSOVP_SC_MAX_uV,
1011*4882a593Smuzhiyun .busovp_byp_min = BQ25975_BUSOVP_BYP_MIN_uV,
1012*4882a593Smuzhiyun .busovp_byp_max = BQ25975_BUSOVP_BYP_MAX_uV,
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun .batovp_def = BQ25975_BATOVP_DFLT_uV,
1015*4882a593Smuzhiyun .batovp_max = BQ25975_BATOVP_MAX_uV,
1016*4882a593Smuzhiyun .batovp_min = BQ25975_BATOVP_MIN_uV,
1017*4882a593Smuzhiyun .batovp_step = BQ25975_BATOVP_STEP_uV,
1018*4882a593Smuzhiyun .batovp_offset = BQ25975_BATOVP_OFFSET_uV,
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun .batocp_def = BQ25980_BATOCP_DFLT_uA,
1021*4882a593Smuzhiyun .batocp_max = BQ25980_BATOCP_MAX_uA,
1022*4882a593Smuzhiyun },
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun [BQ25960] = {
1025*4882a593Smuzhiyun .model_id = BQ25960,
1026*4882a593Smuzhiyun .regmap_config = &bq25960_regmap_config,
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun .busocp_def = BQ25960_BUSOCP_DFLT_uA,
1029*4882a593Smuzhiyun .busocp_sc_min = BQ25960_BUSOCP_SC_MAX_uA,
1030*4882a593Smuzhiyun .busocp_sc_max = BQ25960_BUSOCP_SC_MAX_uA,
1031*4882a593Smuzhiyun .busocp_byp_min = BQ25960_BUSOCP_SC_MAX_uA,
1032*4882a593Smuzhiyun .busocp_byp_max = BQ25960_BUSOCP_BYP_MAX_uA,
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun .busovp_sc_def = BQ25975_BUSOVP_DFLT_uV,
1035*4882a593Smuzhiyun .busovp_byp_def = BQ25975_BUSOVP_BYPASS_DFLT_uV,
1036*4882a593Smuzhiyun .busovp_sc_step = BQ25960_BUSOVP_SC_STEP_uV,
1037*4882a593Smuzhiyun .busovp_sc_offset = BQ25960_BUSOVP_SC_OFFSET_uV,
1038*4882a593Smuzhiyun .busovp_byp_step = BQ25960_BUSOVP_BYP_STEP_uV,
1039*4882a593Smuzhiyun .busovp_byp_offset = BQ25960_BUSOVP_BYP_OFFSET_uV,
1040*4882a593Smuzhiyun .busovp_sc_min = BQ25960_BUSOVP_SC_MIN_uV,
1041*4882a593Smuzhiyun .busovp_sc_max = BQ25960_BUSOVP_SC_MAX_uV,
1042*4882a593Smuzhiyun .busovp_byp_min = BQ25960_BUSOVP_BYP_MIN_uV,
1043*4882a593Smuzhiyun .busovp_byp_max = BQ25960_BUSOVP_BYP_MAX_uV,
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun .batovp_def = BQ25960_BATOVP_DFLT_uV,
1046*4882a593Smuzhiyun .batovp_max = BQ25960_BATOVP_MAX_uV,
1047*4882a593Smuzhiyun .batovp_min = BQ25960_BATOVP_MIN_uV,
1048*4882a593Smuzhiyun .batovp_step = BQ25960_BATOVP_STEP_uV,
1049*4882a593Smuzhiyun .batovp_offset = BQ25960_BATOVP_OFFSET_uV,
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun .batocp_def = BQ25960_BATOCP_DFLT_uA,
1052*4882a593Smuzhiyun .batocp_max = BQ25960_BATOCP_MAX_uA,
1053*4882a593Smuzhiyun },
1054*4882a593Smuzhiyun };
1055*4882a593Smuzhiyun
bq25980_power_supply_init(struct bq25980_device * bq,struct device * dev)1056*4882a593Smuzhiyun static int bq25980_power_supply_init(struct bq25980_device *bq,
1057*4882a593Smuzhiyun struct device *dev)
1058*4882a593Smuzhiyun {
1059*4882a593Smuzhiyun struct power_supply_config psy_cfg = { .drv_data = bq,
1060*4882a593Smuzhiyun .of_node = dev->of_node, };
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun psy_cfg.supplied_to = bq25980_charger_supplied_to;
1063*4882a593Smuzhiyun psy_cfg.num_supplicants = ARRAY_SIZE(bq25980_charger_supplied_to);
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun bq->charger = devm_power_supply_register(bq->dev,
1066*4882a593Smuzhiyun &bq25980_power_supply_desc,
1067*4882a593Smuzhiyun &psy_cfg);
1068*4882a593Smuzhiyun if (IS_ERR(bq->charger))
1069*4882a593Smuzhiyun return -EINVAL;
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun bq->battery = devm_power_supply_register(bq->dev,
1072*4882a593Smuzhiyun &bq25980_battery_desc,
1073*4882a593Smuzhiyun &psy_cfg);
1074*4882a593Smuzhiyun if (IS_ERR(bq->battery))
1075*4882a593Smuzhiyun return -EINVAL;
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun return 0;
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun
bq25980_hw_init(struct bq25980_device * bq)1080*4882a593Smuzhiyun static int bq25980_hw_init(struct bq25980_device *bq)
1081*4882a593Smuzhiyun {
1082*4882a593Smuzhiyun struct power_supply_battery_info bat_info = { };
1083*4882a593Smuzhiyun int wd_reg_val = BQ25980_WATCHDOG_DIS;
1084*4882a593Smuzhiyun int wd_max_val = BQ25980_NUM_WD_VAL - 1;
1085*4882a593Smuzhiyun int ret = 0;
1086*4882a593Smuzhiyun int curr_val;
1087*4882a593Smuzhiyun int volt_val;
1088*4882a593Smuzhiyun int i;
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun if (bq->watchdog_timer) {
1091*4882a593Smuzhiyun if (bq->watchdog_timer >= bq25980_watchdog_time[wd_max_val])
1092*4882a593Smuzhiyun wd_reg_val = wd_max_val;
1093*4882a593Smuzhiyun else {
1094*4882a593Smuzhiyun for (i = 0; i < wd_max_val; i++) {
1095*4882a593Smuzhiyun if (bq->watchdog_timer > bq25980_watchdog_time[i] &&
1096*4882a593Smuzhiyun bq->watchdog_timer < bq25980_watchdog_time[i + 1]) {
1097*4882a593Smuzhiyun wd_reg_val = i;
1098*4882a593Smuzhiyun break;
1099*4882a593Smuzhiyun }
1100*4882a593Smuzhiyun }
1101*4882a593Smuzhiyun }
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_3,
1105*4882a593Smuzhiyun BQ25980_WATCHDOG_MASK, wd_reg_val);
1106*4882a593Smuzhiyun if (ret)
1107*4882a593Smuzhiyun return ret;
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun ret = power_supply_get_battery_info(bq->charger, &bat_info);
1110*4882a593Smuzhiyun if (ret) {
1111*4882a593Smuzhiyun dev_warn(bq->dev, "battery info missing\n");
1112*4882a593Smuzhiyun return -EINVAL;
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun bq->init_data.ichg_max = bat_info.constant_charge_current_max_ua;
1116*4882a593Smuzhiyun bq->init_data.vreg_max = bat_info.constant_charge_voltage_max_uv;
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun if (bq->state.bypass) {
1119*4882a593Smuzhiyun ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
1120*4882a593Smuzhiyun BQ25980_EN_BYPASS, BQ25980_EN_BYPASS);
1121*4882a593Smuzhiyun if (ret)
1122*4882a593Smuzhiyun return ret;
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun curr_val = bq->init_data.bypass_ilim;
1125*4882a593Smuzhiyun volt_val = bq->init_data.bypass_vlim;
1126*4882a593Smuzhiyun } else {
1127*4882a593Smuzhiyun curr_val = bq->init_data.sc_ilim;
1128*4882a593Smuzhiyun volt_val = bq->init_data.sc_vlim;
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun ret = bq25980_set_input_curr_lim(bq, curr_val);
1132*4882a593Smuzhiyun if (ret)
1133*4882a593Smuzhiyun return ret;
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun ret = bq25980_set_input_volt_lim(bq, volt_val);
1136*4882a593Smuzhiyun if (ret)
1137*4882a593Smuzhiyun return ret;
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun return regmap_update_bits(bq->regmap, BQ25980_ADC_CONTROL1,
1140*4882a593Smuzhiyun BQ25980_ADC_EN, BQ25980_ADC_EN);
1141*4882a593Smuzhiyun }
1142*4882a593Smuzhiyun
bq25980_parse_dt(struct bq25980_device * bq)1143*4882a593Smuzhiyun static int bq25980_parse_dt(struct bq25980_device *bq)
1144*4882a593Smuzhiyun {
1145*4882a593Smuzhiyun int ret;
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun ret = device_property_read_u32(bq->dev, "ti,watchdog-timeout-ms",
1148*4882a593Smuzhiyun &bq->watchdog_timer);
1149*4882a593Smuzhiyun if (ret)
1150*4882a593Smuzhiyun bq->watchdog_timer = BQ25980_WATCHDOG_MIN;
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun if (bq->watchdog_timer > BQ25980_WATCHDOG_MAX ||
1153*4882a593Smuzhiyun bq->watchdog_timer < BQ25980_WATCHDOG_MIN)
1154*4882a593Smuzhiyun return -EINVAL;
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun ret = device_property_read_u32(bq->dev,
1157*4882a593Smuzhiyun "ti,sc-ovp-limit-microvolt",
1158*4882a593Smuzhiyun &bq->init_data.sc_vlim);
1159*4882a593Smuzhiyun if (ret)
1160*4882a593Smuzhiyun bq->init_data.sc_vlim = bq->chip_info->busovp_sc_def;
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun if (bq->init_data.sc_vlim > bq->chip_info->busovp_sc_max ||
1163*4882a593Smuzhiyun bq->init_data.sc_vlim < bq->chip_info->busovp_sc_min) {
1164*4882a593Smuzhiyun dev_err(bq->dev, "SC ovp limit is out of range\n");
1165*4882a593Smuzhiyun return -EINVAL;
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun ret = device_property_read_u32(bq->dev,
1169*4882a593Smuzhiyun "ti,sc-ocp-limit-microamp",
1170*4882a593Smuzhiyun &bq->init_data.sc_ilim);
1171*4882a593Smuzhiyun if (ret)
1172*4882a593Smuzhiyun bq->init_data.sc_ilim = bq->chip_info->busocp_def;
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun if (bq->init_data.sc_ilim > bq->chip_info->busocp_sc_max ||
1175*4882a593Smuzhiyun bq->init_data.sc_ilim < bq->chip_info->busocp_sc_min) {
1176*4882a593Smuzhiyun dev_err(bq->dev, "SC ocp limit is out of range\n");
1177*4882a593Smuzhiyun return -EINVAL;
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun ret = device_property_read_u32(bq->dev,
1181*4882a593Smuzhiyun "ti,bypass-ovp-limit-microvolt",
1182*4882a593Smuzhiyun &bq->init_data.bypass_vlim);
1183*4882a593Smuzhiyun if (ret)
1184*4882a593Smuzhiyun bq->init_data.bypass_vlim = bq->chip_info->busovp_byp_def;
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun if (bq->init_data.bypass_vlim > bq->chip_info->busovp_byp_max ||
1187*4882a593Smuzhiyun bq->init_data.bypass_vlim < bq->chip_info->busovp_byp_min) {
1188*4882a593Smuzhiyun dev_err(bq->dev, "Bypass ovp limit is out of range\n");
1189*4882a593Smuzhiyun return -EINVAL;
1190*4882a593Smuzhiyun }
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun ret = device_property_read_u32(bq->dev,
1193*4882a593Smuzhiyun "ti,bypass-ocp-limit-microamp",
1194*4882a593Smuzhiyun &bq->init_data.bypass_ilim);
1195*4882a593Smuzhiyun if (ret)
1196*4882a593Smuzhiyun bq->init_data.bypass_ilim = bq->chip_info->busocp_def;
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun if (bq->init_data.bypass_ilim > bq->chip_info->busocp_byp_max ||
1199*4882a593Smuzhiyun bq->init_data.bypass_ilim < bq->chip_info->busocp_byp_min) {
1200*4882a593Smuzhiyun dev_err(bq->dev, "Bypass ocp limit is out of range\n");
1201*4882a593Smuzhiyun return -EINVAL;
1202*4882a593Smuzhiyun }
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun bq->state.bypass = device_property_read_bool(bq->dev,
1206*4882a593Smuzhiyun "ti,bypass-enable");
1207*4882a593Smuzhiyun return 0;
1208*4882a593Smuzhiyun }
1209*4882a593Smuzhiyun
bq25980_probe(struct i2c_client * client,const struct i2c_device_id * id)1210*4882a593Smuzhiyun static int bq25980_probe(struct i2c_client *client,
1211*4882a593Smuzhiyun const struct i2c_device_id *id)
1212*4882a593Smuzhiyun {
1213*4882a593Smuzhiyun struct device *dev = &client->dev;
1214*4882a593Smuzhiyun struct bq25980_device *bq;
1215*4882a593Smuzhiyun int ret;
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun bq = devm_kzalloc(dev, sizeof(*bq), GFP_KERNEL);
1218*4882a593Smuzhiyun if (!bq)
1219*4882a593Smuzhiyun return -ENOMEM;
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun bq->client = client;
1222*4882a593Smuzhiyun bq->dev = dev;
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun mutex_init(&bq->lock);
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun strncpy(bq->model_name, id->name, I2C_NAME_SIZE);
1227*4882a593Smuzhiyun bq->chip_info = &bq25980_chip_info_tbl[id->driver_data];
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun bq->regmap = devm_regmap_init_i2c(client,
1230*4882a593Smuzhiyun bq->chip_info->regmap_config);
1231*4882a593Smuzhiyun if (IS_ERR(bq->regmap)) {
1232*4882a593Smuzhiyun dev_err(dev, "Failed to allocate register map\n");
1233*4882a593Smuzhiyun return PTR_ERR(bq->regmap);
1234*4882a593Smuzhiyun }
1235*4882a593Smuzhiyun
1236*4882a593Smuzhiyun i2c_set_clientdata(client, bq);
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun ret = bq25980_parse_dt(bq);
1239*4882a593Smuzhiyun if (ret) {
1240*4882a593Smuzhiyun dev_err(dev, "Failed to read device tree properties%d\n", ret);
1241*4882a593Smuzhiyun return ret;
1242*4882a593Smuzhiyun }
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun if (client->irq) {
1245*4882a593Smuzhiyun ret = devm_request_threaded_irq(dev, client->irq, NULL,
1246*4882a593Smuzhiyun bq25980_irq_handler_thread,
1247*4882a593Smuzhiyun IRQF_TRIGGER_FALLING |
1248*4882a593Smuzhiyun IRQF_ONESHOT,
1249*4882a593Smuzhiyun dev_name(&client->dev), bq);
1250*4882a593Smuzhiyun if (ret)
1251*4882a593Smuzhiyun return ret;
1252*4882a593Smuzhiyun }
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun ret = bq25980_power_supply_init(bq, dev);
1255*4882a593Smuzhiyun if (ret) {
1256*4882a593Smuzhiyun dev_err(dev, "Failed to register power supply\n");
1257*4882a593Smuzhiyun return ret;
1258*4882a593Smuzhiyun }
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun ret = bq25980_hw_init(bq);
1261*4882a593Smuzhiyun if (ret) {
1262*4882a593Smuzhiyun dev_err(dev, "Cannot initialize the chip.\n");
1263*4882a593Smuzhiyun return ret;
1264*4882a593Smuzhiyun }
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun return 0;
1267*4882a593Smuzhiyun }
1268*4882a593Smuzhiyun
1269*4882a593Smuzhiyun static const struct i2c_device_id bq25980_i2c_ids[] = {
1270*4882a593Smuzhiyun { "bq25980", BQ25980 },
1271*4882a593Smuzhiyun { "bq25975", BQ25975 },
1272*4882a593Smuzhiyun { "bq25975", BQ25975 },
1273*4882a593Smuzhiyun {},
1274*4882a593Smuzhiyun };
1275*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, bq25980_i2c_ids);
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun static const struct of_device_id bq25980_of_match[] = {
1278*4882a593Smuzhiyun { .compatible = "ti,bq25980", .data = (void *)BQ25980 },
1279*4882a593Smuzhiyun { .compatible = "ti,bq25975", .data = (void *)BQ25975 },
1280*4882a593Smuzhiyun { .compatible = "ti,bq25960", .data = (void *)BQ25960 },
1281*4882a593Smuzhiyun { },
1282*4882a593Smuzhiyun };
1283*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bq25980_of_match);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun static struct i2c_driver bq25980_driver = {
1286*4882a593Smuzhiyun .driver = {
1287*4882a593Smuzhiyun .name = "bq25980-charger",
1288*4882a593Smuzhiyun .of_match_table = bq25980_of_match,
1289*4882a593Smuzhiyun },
1290*4882a593Smuzhiyun .probe = bq25980_probe,
1291*4882a593Smuzhiyun .id_table = bq25980_i2c_ids,
1292*4882a593Smuzhiyun };
1293*4882a593Smuzhiyun module_i2c_driver(bq25980_driver);
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1296*4882a593Smuzhiyun MODULE_AUTHOR("Ricardo Rivera-Matos <r-rivera-matos@ti.com>");
1297*4882a593Smuzhiyun MODULE_DESCRIPTION("bq25980 charger driver");
1298*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1299