1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Broadcom
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
6*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
10*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11*4882a593Smuzhiyun * GNU General Public License for more details.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/of_address.h>
16*4882a593Smuzhiyun #include <linux/of_platform.h>
17*4882a593Smuzhiyun #include <linux/reboot.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define RSTMGR_REG_WR_ACCESS_OFFSET 0
20*4882a593Smuzhiyun #define RSTMGR_REG_CHIP_SOFT_RST_OFFSET 4
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define RSTMGR_WR_PASSWORD 0xa5a5
23*4882a593Smuzhiyun #define RSTMGR_WR_PASSWORD_SHIFT 8
24*4882a593Smuzhiyun #define RSTMGR_WR_ACCESS_ENABLE 1
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static void __iomem *kona_reset_base;
27*4882a593Smuzhiyun
kona_reset_handler(struct notifier_block * this,unsigned long mode,void * cmd)28*4882a593Smuzhiyun static int kona_reset_handler(struct notifier_block *this,
29*4882a593Smuzhiyun unsigned long mode, void *cmd)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * A soft reset is triggered by writing a 0 to bit 0 of the soft reset
33*4882a593Smuzhiyun * register. To write to that register we must first write the password
34*4882a593Smuzhiyun * and the enable bit in the write access enable register.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun writel((RSTMGR_WR_PASSWORD << RSTMGR_WR_PASSWORD_SHIFT) |
37*4882a593Smuzhiyun RSTMGR_WR_ACCESS_ENABLE,
38*4882a593Smuzhiyun kona_reset_base + RSTMGR_REG_WR_ACCESS_OFFSET);
39*4882a593Smuzhiyun writel(0, kona_reset_base + RSTMGR_REG_CHIP_SOFT_RST_OFFSET);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return NOTIFY_DONE;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun static struct notifier_block kona_reset_nb = {
45*4882a593Smuzhiyun .notifier_call = kona_reset_handler,
46*4882a593Smuzhiyun .priority = 128,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
kona_reset_probe(struct platform_device * pdev)49*4882a593Smuzhiyun static int kona_reset_probe(struct platform_device *pdev)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun kona_reset_base = devm_ioremap_resource(&pdev->dev, res);
54*4882a593Smuzhiyun if (IS_ERR(kona_reset_base))
55*4882a593Smuzhiyun return PTR_ERR(kona_reset_base);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return register_restart_handler(&kona_reset_nb);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct of_device_id of_match[] = {
61*4882a593Smuzhiyun { .compatible = "brcm,bcm21664-resetmgr" },
62*4882a593Smuzhiyun {},
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static struct platform_driver bcm_kona_reset_driver = {
66*4882a593Smuzhiyun .probe = kona_reset_probe,
67*4882a593Smuzhiyun .driver = {
68*4882a593Smuzhiyun .name = "brcm-kona-reset",
69*4882a593Smuzhiyun .of_match_table = of_match,
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun builtin_platform_driver(bcm_kona_reset_driver);
74