1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Atmel AT91 SAM9 SoCs reset code
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2007 Atmel Corporation.
5*4882a593Smuzhiyun * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6*4882a593Smuzhiyun * Copyright (C) 2014 Free Electrons
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
9*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
10*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_address.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/printk.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <soc/at91/at91sam9_ddrsdr.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
24*4882a593Smuzhiyun #define AT91_SHDW_SHDW BIT(0) /* Shut Down command */
25*4882a593Smuzhiyun #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
28*4882a593Smuzhiyun #define AT91_SHDW_WKMODE0 GENMASK(2, 0) /* Wake-up 0 Mode Selection */
29*4882a593Smuzhiyun #define AT91_SHDW_CPTWK0_MAX 0xf /* Maximum Counter On Wake Up 0 */
30*4882a593Smuzhiyun #define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
31*4882a593Smuzhiyun #define AT91_SHDW_CPTWK0_(x) ((x) << 4)
32*4882a593Smuzhiyun #define AT91_SHDW_RTTWKEN BIT(16) /* Real Time Timer Wake-up Enable */
33*4882a593Smuzhiyun #define AT91_SHDW_RTCWKEN BIT(17) /* Real Time Clock Wake-up Enable */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
36*4882a593Smuzhiyun #define AT91_SHDW_WAKEUP0 BIT(0) /* Wake-up 0 Status */
37*4882a593Smuzhiyun #define AT91_SHDW_RTTWK BIT(16) /* Real-time Timer Wake-up */
38*4882a593Smuzhiyun #define AT91_SHDW_RTCWK BIT(17) /* Real-time Clock Wake-up [SAM9RL] */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun enum wakeup_type {
41*4882a593Smuzhiyun AT91_SHDW_WKMODE0_NONE = 0,
42*4882a593Smuzhiyun AT91_SHDW_WKMODE0_HIGH = 1,
43*4882a593Smuzhiyun AT91_SHDW_WKMODE0_LOW = 2,
44*4882a593Smuzhiyun AT91_SHDW_WKMODE0_ANYLEVEL = 3,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const char *shdwc_wakeup_modes[] = {
48*4882a593Smuzhiyun [AT91_SHDW_WKMODE0_NONE] = "none",
49*4882a593Smuzhiyun [AT91_SHDW_WKMODE0_HIGH] = "high",
50*4882a593Smuzhiyun [AT91_SHDW_WKMODE0_LOW] = "low",
51*4882a593Smuzhiyun [AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static struct shdwc {
55*4882a593Smuzhiyun struct clk *sclk;
56*4882a593Smuzhiyun void __iomem *shdwc_base;
57*4882a593Smuzhiyun void __iomem *mpddrc_base;
58*4882a593Smuzhiyun } at91_shdwc;
59*4882a593Smuzhiyun
at91_wakeup_status(struct platform_device * pdev)60*4882a593Smuzhiyun static void __init at91_wakeup_status(struct platform_device *pdev)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun const char *reason;
63*4882a593Smuzhiyun u32 reg = readl(at91_shdwc.shdwc_base + AT91_SHDW_SR);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Simple power-on, just bail out */
66*4882a593Smuzhiyun if (!reg)
67*4882a593Smuzhiyun return;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if (reg & AT91_SHDW_RTTWK)
70*4882a593Smuzhiyun reason = "RTT";
71*4882a593Smuzhiyun else if (reg & AT91_SHDW_RTCWK)
72*4882a593Smuzhiyun reason = "RTC";
73*4882a593Smuzhiyun else
74*4882a593Smuzhiyun reason = "unknown";
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun dev_info(&pdev->dev, "Wake-Up source: %s\n", reason);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
at91_poweroff(void)79*4882a593Smuzhiyun static void at91_poweroff(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun asm volatile(
82*4882a593Smuzhiyun /* Align to cache lines */
83*4882a593Smuzhiyun ".balign 32\n\t"
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Ensure AT91_SHDW_CR is in the TLB by reading it */
86*4882a593Smuzhiyun " ldr r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Power down SDRAM0 */
89*4882a593Smuzhiyun " tst %0, #0\n\t"
90*4882a593Smuzhiyun " beq 1f\n\t"
91*4882a593Smuzhiyun " str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
92*4882a593Smuzhiyun /* Shutdown CPU */
93*4882a593Smuzhiyun "1: str %3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun " b .\n\t"
96*4882a593Smuzhiyun :
97*4882a593Smuzhiyun : "r" (at91_shdwc.mpddrc_base),
98*4882a593Smuzhiyun "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
99*4882a593Smuzhiyun "r" (at91_shdwc.shdwc_base),
100*4882a593Smuzhiyun "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
101*4882a593Smuzhiyun : "r6");
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
at91_poweroff_get_wakeup_mode(struct device_node * np)104*4882a593Smuzhiyun static int at91_poweroff_get_wakeup_mode(struct device_node *np)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun const char *pm;
107*4882a593Smuzhiyun unsigned int i;
108*4882a593Smuzhiyun int err;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
111*4882a593Smuzhiyun if (err < 0)
112*4882a593Smuzhiyun return AT91_SHDW_WKMODE0_ANYLEVEL;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
115*4882a593Smuzhiyun if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
116*4882a593Smuzhiyun return i;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return -ENODEV;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
at91_poweroff_dt_set_wakeup_mode(struct platform_device * pdev)121*4882a593Smuzhiyun static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
124*4882a593Smuzhiyun int wakeup_mode;
125*4882a593Smuzhiyun u32 mode = 0, tmp;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun wakeup_mode = at91_poweroff_get_wakeup_mode(np);
128*4882a593Smuzhiyun if (wakeup_mode < 0) {
129*4882a593Smuzhiyun dev_warn(&pdev->dev, "shdwc unknown wakeup mode\n");
130*4882a593Smuzhiyun return;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun if (!of_property_read_u32(np, "atmel,wakeup-counter", &tmp)) {
134*4882a593Smuzhiyun if (tmp > AT91_SHDW_CPTWK0_MAX) {
135*4882a593Smuzhiyun dev_warn(&pdev->dev,
136*4882a593Smuzhiyun "shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
137*4882a593Smuzhiyun tmp, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
138*4882a593Smuzhiyun tmp = AT91_SHDW_CPTWK0_MAX;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun mode |= AT91_SHDW_CPTWK0_(tmp);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
144*4882a593Smuzhiyun mode |= AT91_SHDW_RTCWKEN;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
147*4882a593Smuzhiyun mode |= AT91_SHDW_RTTWKEN;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun writel(wakeup_mode | mode, at91_shdwc.shdwc_base + AT91_SHDW_MR);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
at91_poweroff_probe(struct platform_device * pdev)152*4882a593Smuzhiyun static int __init at91_poweroff_probe(struct platform_device *pdev)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct resource *res;
155*4882a593Smuzhiyun struct device_node *np;
156*4882a593Smuzhiyun u32 ddr_type;
157*4882a593Smuzhiyun int ret;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
160*4882a593Smuzhiyun at91_shdwc.shdwc_base = devm_ioremap_resource(&pdev->dev, res);
161*4882a593Smuzhiyun if (IS_ERR(at91_shdwc.shdwc_base))
162*4882a593Smuzhiyun return PTR_ERR(at91_shdwc.shdwc_base);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL);
165*4882a593Smuzhiyun if (IS_ERR(at91_shdwc.sclk))
166*4882a593Smuzhiyun return PTR_ERR(at91_shdwc.sclk);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun ret = clk_prepare_enable(at91_shdwc.sclk);
169*4882a593Smuzhiyun if (ret) {
170*4882a593Smuzhiyun dev_err(&pdev->dev, "Could not enable slow clock\n");
171*4882a593Smuzhiyun return ret;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun at91_wakeup_status(pdev);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun if (pdev->dev.of_node)
177*4882a593Smuzhiyun at91_poweroff_dt_set_wakeup_mode(pdev);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
180*4882a593Smuzhiyun if (np) {
181*4882a593Smuzhiyun at91_shdwc.mpddrc_base = of_iomap(np, 0);
182*4882a593Smuzhiyun of_node_put(np);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun if (!at91_shdwc.mpddrc_base) {
185*4882a593Smuzhiyun ret = -ENOMEM;
186*4882a593Smuzhiyun goto clk_disable;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun ddr_type = readl(at91_shdwc.mpddrc_base + AT91_DDRSDRC_MDR) &
190*4882a593Smuzhiyun AT91_DDRSDRC_MD;
191*4882a593Smuzhiyun if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
192*4882a593Smuzhiyun ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
193*4882a593Smuzhiyun iounmap(at91_shdwc.mpddrc_base);
194*4882a593Smuzhiyun at91_shdwc.mpddrc_base = NULL;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun pm_power_off = at91_poweroff;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return 0;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun clk_disable:
203*4882a593Smuzhiyun clk_disable_unprepare(at91_shdwc.sclk);
204*4882a593Smuzhiyun return ret;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
at91_poweroff_remove(struct platform_device * pdev)207*4882a593Smuzhiyun static int __exit at91_poweroff_remove(struct platform_device *pdev)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun if (pm_power_off == at91_poweroff)
210*4882a593Smuzhiyun pm_power_off = NULL;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun if (at91_shdwc.mpddrc_base)
213*4882a593Smuzhiyun iounmap(at91_shdwc.mpddrc_base);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun clk_disable_unprepare(at91_shdwc.sclk);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun return 0;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun static const struct of_device_id at91_poweroff_of_match[] = {
221*4882a593Smuzhiyun { .compatible = "atmel,at91sam9260-shdwc", },
222*4882a593Smuzhiyun { .compatible = "atmel,at91sam9rl-shdwc", },
223*4882a593Smuzhiyun { .compatible = "atmel,at91sam9x5-shdwc", },
224*4882a593Smuzhiyun { /*sentinel*/ }
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, at91_poweroff_of_match);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static struct platform_driver at91_poweroff_driver = {
229*4882a593Smuzhiyun .remove = __exit_p(at91_poweroff_remove),
230*4882a593Smuzhiyun .driver = {
231*4882a593Smuzhiyun .name = "at91-poweroff",
232*4882a593Smuzhiyun .of_match_table = at91_poweroff_of_match,
233*4882a593Smuzhiyun },
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun module_platform_driver_probe(at91_poweroff_driver, at91_poweroff_probe);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun MODULE_AUTHOR("Atmel Corporation");
238*4882a593Smuzhiyun MODULE_DESCRIPTION("Shutdown driver for Atmel SoCs");
239*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
240