1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Intel P-Unit Mailbox IPC mechanism
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2015 Intel Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * The heart of the P-Unit is the Foxton microcontroller and its firmware,
8*4882a593Smuzhiyun * which provide mailbox interface for power management usage.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/bitops.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <asm/intel_punit_ipc.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* IPC Mailbox registers */
23*4882a593Smuzhiyun #define OFFSET_DATA_LOW 0x0
24*4882a593Smuzhiyun #define OFFSET_DATA_HIGH 0x4
25*4882a593Smuzhiyun /* bit field of interface register */
26*4882a593Smuzhiyun #define CMD_RUN BIT(31)
27*4882a593Smuzhiyun #define CMD_ERRCODE_MASK GENMASK(7, 0)
28*4882a593Smuzhiyun #define CMD_PARA1_SHIFT 8
29*4882a593Smuzhiyun #define CMD_PARA2_SHIFT 16
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define CMD_TIMEOUT_SECONDS 1
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun enum {
34*4882a593Smuzhiyun BASE_DATA = 0,
35*4882a593Smuzhiyun BASE_IFACE,
36*4882a593Smuzhiyun BASE_MAX,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun typedef struct {
40*4882a593Smuzhiyun struct device *dev;
41*4882a593Smuzhiyun struct mutex lock;
42*4882a593Smuzhiyun int irq;
43*4882a593Smuzhiyun struct completion cmd_complete;
44*4882a593Smuzhiyun /* base of interface and data registers */
45*4882a593Smuzhiyun void __iomem *base[RESERVED_IPC][BASE_MAX];
46*4882a593Smuzhiyun IPC_TYPE type;
47*4882a593Smuzhiyun } IPC_DEV;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static IPC_DEV *punit_ipcdev;
50*4882a593Smuzhiyun
ipc_read_status(IPC_DEV * ipcdev,IPC_TYPE type)51*4882a593Smuzhiyun static inline u32 ipc_read_status(IPC_DEV *ipcdev, IPC_TYPE type)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun return readl(ipcdev->base[type][BASE_IFACE]);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
ipc_write_cmd(IPC_DEV * ipcdev,IPC_TYPE type,u32 cmd)56*4882a593Smuzhiyun static inline void ipc_write_cmd(IPC_DEV *ipcdev, IPC_TYPE type, u32 cmd)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun writel(cmd, ipcdev->base[type][BASE_IFACE]);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
ipc_read_data_low(IPC_DEV * ipcdev,IPC_TYPE type)61*4882a593Smuzhiyun static inline u32 ipc_read_data_low(IPC_DEV *ipcdev, IPC_TYPE type)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
ipc_read_data_high(IPC_DEV * ipcdev,IPC_TYPE type)66*4882a593Smuzhiyun static inline u32 ipc_read_data_high(IPC_DEV *ipcdev, IPC_TYPE type)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
ipc_write_data_low(IPC_DEV * ipcdev,IPC_TYPE type,u32 data)71*4882a593Smuzhiyun static inline void ipc_write_data_low(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
ipc_write_data_high(IPC_DEV * ipcdev,IPC_TYPE type,u32 data)76*4882a593Smuzhiyun static inline void ipc_write_data_high(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
ipc_err_string(int error)81*4882a593Smuzhiyun static const char *ipc_err_string(int error)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun if (error == IPC_PUNIT_ERR_SUCCESS)
84*4882a593Smuzhiyun return "no error";
85*4882a593Smuzhiyun else if (error == IPC_PUNIT_ERR_INVALID_CMD)
86*4882a593Smuzhiyun return "invalid command";
87*4882a593Smuzhiyun else if (error == IPC_PUNIT_ERR_INVALID_PARAMETER)
88*4882a593Smuzhiyun return "invalid parameter";
89*4882a593Smuzhiyun else if (error == IPC_PUNIT_ERR_CMD_TIMEOUT)
90*4882a593Smuzhiyun return "command timeout";
91*4882a593Smuzhiyun else if (error == IPC_PUNIT_ERR_CMD_LOCKED)
92*4882a593Smuzhiyun return "command locked";
93*4882a593Smuzhiyun else if (error == IPC_PUNIT_ERR_INVALID_VR_ID)
94*4882a593Smuzhiyun return "invalid vr id";
95*4882a593Smuzhiyun else if (error == IPC_PUNIT_ERR_VR_ERR)
96*4882a593Smuzhiyun return "vr error";
97*4882a593Smuzhiyun else
98*4882a593Smuzhiyun return "unknown error";
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
intel_punit_ipc_check_status(IPC_DEV * ipcdev,IPC_TYPE type)101*4882a593Smuzhiyun static int intel_punit_ipc_check_status(IPC_DEV *ipcdev, IPC_TYPE type)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun int loops = CMD_TIMEOUT_SECONDS * USEC_PER_SEC;
104*4882a593Smuzhiyun int errcode;
105*4882a593Smuzhiyun int status;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun if (ipcdev->irq) {
108*4882a593Smuzhiyun if (!wait_for_completion_timeout(&ipcdev->cmd_complete,
109*4882a593Smuzhiyun CMD_TIMEOUT_SECONDS * HZ)) {
110*4882a593Smuzhiyun dev_err(ipcdev->dev, "IPC timed out\n");
111*4882a593Smuzhiyun return -ETIMEDOUT;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun } else {
114*4882a593Smuzhiyun while ((ipc_read_status(ipcdev, type) & CMD_RUN) && --loops)
115*4882a593Smuzhiyun udelay(1);
116*4882a593Smuzhiyun if (!loops) {
117*4882a593Smuzhiyun dev_err(ipcdev->dev, "IPC timed out\n");
118*4882a593Smuzhiyun return -ETIMEDOUT;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun status = ipc_read_status(ipcdev, type);
123*4882a593Smuzhiyun errcode = status & CMD_ERRCODE_MASK;
124*4882a593Smuzhiyun if (errcode) {
125*4882a593Smuzhiyun dev_err(ipcdev->dev, "IPC failed: %s, IPC_STS=0x%x\n",
126*4882a593Smuzhiyun ipc_err_string(errcode), status);
127*4882a593Smuzhiyun return -EIO;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun return 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /**
134*4882a593Smuzhiyun * intel_punit_ipc_simple_command() - Simple IPC command
135*4882a593Smuzhiyun * @cmd: IPC command code.
136*4882a593Smuzhiyun * @para1: First 8bit parameter, set 0 if not used.
137*4882a593Smuzhiyun * @para2: Second 8bit parameter, set 0 if not used.
138*4882a593Smuzhiyun *
139*4882a593Smuzhiyun * Send a IPC command to P-Unit when there is no data transaction
140*4882a593Smuzhiyun *
141*4882a593Smuzhiyun * Return: IPC error code or 0 on success.
142*4882a593Smuzhiyun */
intel_punit_ipc_simple_command(int cmd,int para1,int para2)143*4882a593Smuzhiyun int intel_punit_ipc_simple_command(int cmd, int para1, int para2)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun IPC_DEV *ipcdev = punit_ipcdev;
146*4882a593Smuzhiyun IPC_TYPE type;
147*4882a593Smuzhiyun u32 val;
148*4882a593Smuzhiyun int ret;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun mutex_lock(&ipcdev->lock);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun reinit_completion(&ipcdev->cmd_complete);
153*4882a593Smuzhiyun type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
156*4882a593Smuzhiyun val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
157*4882a593Smuzhiyun ipc_write_cmd(ipcdev, type, val);
158*4882a593Smuzhiyun ret = intel_punit_ipc_check_status(ipcdev, type);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun mutex_unlock(&ipcdev->lock);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return ret;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun EXPORT_SYMBOL(intel_punit_ipc_simple_command);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun /**
167*4882a593Smuzhiyun * intel_punit_ipc_command() - IPC command with data and pointers
168*4882a593Smuzhiyun * @cmd: IPC command code.
169*4882a593Smuzhiyun * @para1: First 8bit parameter, set 0 if not used.
170*4882a593Smuzhiyun * @para2: Second 8bit parameter, set 0 if not used.
171*4882a593Smuzhiyun * @in: Input data, 32bit for BIOS cmd, two 32bit for GTD and ISPD.
172*4882a593Smuzhiyun * @out: Output data.
173*4882a593Smuzhiyun *
174*4882a593Smuzhiyun * Send a IPC command to P-Unit with data transaction
175*4882a593Smuzhiyun *
176*4882a593Smuzhiyun * Return: IPC error code or 0 on success.
177*4882a593Smuzhiyun */
intel_punit_ipc_command(u32 cmd,u32 para1,u32 para2,u32 * in,u32 * out)178*4882a593Smuzhiyun int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun IPC_DEV *ipcdev = punit_ipcdev;
181*4882a593Smuzhiyun IPC_TYPE type;
182*4882a593Smuzhiyun u32 val;
183*4882a593Smuzhiyun int ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun mutex_lock(&ipcdev->lock);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun reinit_completion(&ipcdev->cmd_complete);
188*4882a593Smuzhiyun type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun if (in) {
191*4882a593Smuzhiyun ipc_write_data_low(ipcdev, type, *in);
192*4882a593Smuzhiyun if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
193*4882a593Smuzhiyun ipc_write_data_high(ipcdev, type, *++in);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
197*4882a593Smuzhiyun val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
198*4882a593Smuzhiyun ipc_write_cmd(ipcdev, type, val);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun ret = intel_punit_ipc_check_status(ipcdev, type);
201*4882a593Smuzhiyun if (ret)
202*4882a593Smuzhiyun goto out;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun if (out) {
205*4882a593Smuzhiyun *out = ipc_read_data_low(ipcdev, type);
206*4882a593Smuzhiyun if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
207*4882a593Smuzhiyun *++out = ipc_read_data_high(ipcdev, type);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun out:
211*4882a593Smuzhiyun mutex_unlock(&ipcdev->lock);
212*4882a593Smuzhiyun return ret;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(intel_punit_ipc_command);
215*4882a593Smuzhiyun
intel_punit_ioc(int irq,void * dev_id)216*4882a593Smuzhiyun static irqreturn_t intel_punit_ioc(int irq, void *dev_id)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun IPC_DEV *ipcdev = dev_id;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun complete(&ipcdev->cmd_complete);
221*4882a593Smuzhiyun return IRQ_HANDLED;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
intel_punit_get_bars(struct platform_device * pdev)224*4882a593Smuzhiyun static int intel_punit_get_bars(struct platform_device *pdev)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun void __iomem *addr;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /*
229*4882a593Smuzhiyun * The following resources are required
230*4882a593Smuzhiyun * - BIOS_IPC BASE_DATA
231*4882a593Smuzhiyun * - BIOS_IPC BASE_IFACE
232*4882a593Smuzhiyun */
233*4882a593Smuzhiyun addr = devm_platform_ioremap_resource(pdev, 0);
234*4882a593Smuzhiyun if (IS_ERR(addr))
235*4882a593Smuzhiyun return PTR_ERR(addr);
236*4882a593Smuzhiyun punit_ipcdev->base[BIOS_IPC][BASE_DATA] = addr;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun addr = devm_platform_ioremap_resource(pdev, 1);
239*4882a593Smuzhiyun if (IS_ERR(addr))
240*4882a593Smuzhiyun return PTR_ERR(addr);
241*4882a593Smuzhiyun punit_ipcdev->base[BIOS_IPC][BASE_IFACE] = addr;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /*
244*4882a593Smuzhiyun * The following resources are optional
245*4882a593Smuzhiyun * - ISPDRIVER_IPC BASE_DATA
246*4882a593Smuzhiyun * - ISPDRIVER_IPC BASE_IFACE
247*4882a593Smuzhiyun * - GTDRIVER_IPC BASE_DATA
248*4882a593Smuzhiyun * - GTDRIVER_IPC BASE_IFACE
249*4882a593Smuzhiyun */
250*4882a593Smuzhiyun addr = devm_platform_ioremap_resource(pdev, 2);
251*4882a593Smuzhiyun if (!IS_ERR(addr))
252*4882a593Smuzhiyun punit_ipcdev->base[ISPDRIVER_IPC][BASE_DATA] = addr;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun addr = devm_platform_ioremap_resource(pdev, 3);
255*4882a593Smuzhiyun if (!IS_ERR(addr))
256*4882a593Smuzhiyun punit_ipcdev->base[ISPDRIVER_IPC][BASE_IFACE] = addr;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun addr = devm_platform_ioremap_resource(pdev, 4);
259*4882a593Smuzhiyun if (!IS_ERR(addr))
260*4882a593Smuzhiyun punit_ipcdev->base[GTDRIVER_IPC][BASE_DATA] = addr;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun addr = devm_platform_ioremap_resource(pdev, 5);
263*4882a593Smuzhiyun if (!IS_ERR(addr))
264*4882a593Smuzhiyun punit_ipcdev->base[GTDRIVER_IPC][BASE_IFACE] = addr;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun return 0;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
intel_punit_ipc_probe(struct platform_device * pdev)269*4882a593Smuzhiyun static int intel_punit_ipc_probe(struct platform_device *pdev)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun int irq, ret;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun punit_ipcdev = devm_kzalloc(&pdev->dev,
274*4882a593Smuzhiyun sizeof(*punit_ipcdev), GFP_KERNEL);
275*4882a593Smuzhiyun if (!punit_ipcdev)
276*4882a593Smuzhiyun return -ENOMEM;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun platform_set_drvdata(pdev, punit_ipcdev);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun irq = platform_get_irq_optional(pdev, 0);
281*4882a593Smuzhiyun if (irq < 0) {
282*4882a593Smuzhiyun dev_warn(&pdev->dev, "Invalid IRQ, using polling mode\n");
283*4882a593Smuzhiyun } else {
284*4882a593Smuzhiyun ret = devm_request_irq(&pdev->dev, irq, intel_punit_ioc,
285*4882a593Smuzhiyun IRQF_NO_SUSPEND, "intel_punit_ipc",
286*4882a593Smuzhiyun &punit_ipcdev);
287*4882a593Smuzhiyun if (ret) {
288*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request irq: %d\n", irq);
289*4882a593Smuzhiyun return ret;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun punit_ipcdev->irq = irq;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun ret = intel_punit_get_bars(pdev);
295*4882a593Smuzhiyun if (ret)
296*4882a593Smuzhiyun return ret;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun punit_ipcdev->dev = &pdev->dev;
299*4882a593Smuzhiyun mutex_init(&punit_ipcdev->lock);
300*4882a593Smuzhiyun init_completion(&punit_ipcdev->cmd_complete);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun return 0;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
intel_punit_ipc_remove(struct platform_device * pdev)305*4882a593Smuzhiyun static int intel_punit_ipc_remove(struct platform_device *pdev)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun return 0;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun static const struct acpi_device_id punit_ipc_acpi_ids[] = {
311*4882a593Smuzhiyun { "INT34D4", 0 },
312*4882a593Smuzhiyun { }
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, punit_ipc_acpi_ids);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun static struct platform_driver intel_punit_ipc_driver = {
317*4882a593Smuzhiyun .probe = intel_punit_ipc_probe,
318*4882a593Smuzhiyun .remove = intel_punit_ipc_remove,
319*4882a593Smuzhiyun .driver = {
320*4882a593Smuzhiyun .name = "intel_punit_ipc",
321*4882a593Smuzhiyun .acpi_match_table = punit_ipc_acpi_ids,
322*4882a593Smuzhiyun },
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun
intel_punit_ipc_init(void)325*4882a593Smuzhiyun static int __init intel_punit_ipc_init(void)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun return platform_driver_register(&intel_punit_ipc_driver);
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
intel_punit_ipc_exit(void)330*4882a593Smuzhiyun static void __exit intel_punit_ipc_exit(void)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun platform_driver_unregister(&intel_punit_ipc_driver);
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
336*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel P-Unit IPC driver");
337*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun /* Some modules are dependent on this, so init earlier */
340*4882a593Smuzhiyun fs_initcall(intel_punit_ipc_init);
341*4882a593Smuzhiyun module_exit(intel_punit_ipc_exit);
342