1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel MID platform thermal driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011 Intel Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Durgadoss R <durgadoss.r@intel.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define pr_fmt(fmt) "intel_mid_thermal: " fmt
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/err.h>
14*4882a593Smuzhiyun #include <linux/mfd/intel_msic.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/param.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun #include <linux/pm.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/thermal.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Number of thermal sensors */
23*4882a593Smuzhiyun #define MSIC_THERMAL_SENSORS 4
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* ADC1 - thermal registers */
26*4882a593Smuzhiyun #define MSIC_ADC_ENBL 0x10
27*4882a593Smuzhiyun #define MSIC_ADC_START 0x08
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define MSIC_ADCTHERM_ENBL 0x04
30*4882a593Smuzhiyun #define MSIC_ADCRRDATA_ENBL 0x05
31*4882a593Smuzhiyun #define MSIC_CHANL_MASK_VAL 0x0F
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define MSIC_STOPBIT_MASK 16
34*4882a593Smuzhiyun #define MSIC_ADCTHERM_MASK 4
35*4882a593Smuzhiyun /* Number of ADC channels */
36*4882a593Smuzhiyun #define ADC_CHANLS_MAX 15
37*4882a593Smuzhiyun #define ADC_LOOP_MAX (ADC_CHANLS_MAX - MSIC_THERMAL_SENSORS)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* ADC channel code values */
40*4882a593Smuzhiyun #define SKIN_SENSOR0_CODE 0x08
41*4882a593Smuzhiyun #define SKIN_SENSOR1_CODE 0x09
42*4882a593Smuzhiyun #define SYS_SENSOR_CODE 0x0A
43*4882a593Smuzhiyun #define MSIC_DIE_SENSOR_CODE 0x03
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define SKIN_THERM_SENSOR0 0
46*4882a593Smuzhiyun #define SKIN_THERM_SENSOR1 1
47*4882a593Smuzhiyun #define SYS_THERM_SENSOR2 2
48*4882a593Smuzhiyun #define MSIC_DIE_THERM_SENSOR3 3
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* ADC code range */
51*4882a593Smuzhiyun #define ADC_MAX 977
52*4882a593Smuzhiyun #define ADC_MIN 162
53*4882a593Smuzhiyun #define ADC_VAL0C 887
54*4882a593Smuzhiyun #define ADC_VAL20C 720
55*4882a593Smuzhiyun #define ADC_VAL40C 508
56*4882a593Smuzhiyun #define ADC_VAL60C 315
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* ADC base addresses */
59*4882a593Smuzhiyun #define ADC_CHNL_START_ADDR INTEL_MSIC_ADC1ADDR0 /* increments by 1 */
60*4882a593Smuzhiyun #define ADC_DATA_START_ADDR INTEL_MSIC_ADC1SNS0H /* increments by 2 */
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* MSIC die attributes */
63*4882a593Smuzhiyun #define MSIC_DIE_ADC_MIN 488
64*4882a593Smuzhiyun #define MSIC_DIE_ADC_MAX 1004
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* This holds the address of the first free ADC channel,
67*4882a593Smuzhiyun * among the 15 channels
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun static int channel_index;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct platform_info {
72*4882a593Smuzhiyun struct platform_device *pdev;
73*4882a593Smuzhiyun struct thermal_zone_device *tzd[MSIC_THERMAL_SENSORS];
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun struct thermal_device_info {
77*4882a593Smuzhiyun unsigned int chnl_addr;
78*4882a593Smuzhiyun int direct;
79*4882a593Smuzhiyun /* This holds the current temperature in millidegree celsius */
80*4882a593Smuzhiyun long curr_temp;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /**
84*4882a593Smuzhiyun * to_msic_die_temp - converts adc_val to msic_die temperature
85*4882a593Smuzhiyun * @adc_val: ADC value to be converted
86*4882a593Smuzhiyun *
87*4882a593Smuzhiyun * Can sleep
88*4882a593Smuzhiyun */
to_msic_die_temp(uint16_t adc_val)89*4882a593Smuzhiyun static int to_msic_die_temp(uint16_t adc_val)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun return (368 * (adc_val) / 1000) - 220;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /**
95*4882a593Smuzhiyun * is_valid_adc - checks whether the adc code is within the defined range
96*4882a593Smuzhiyun * @min: minimum value for the sensor
97*4882a593Smuzhiyun * @max: maximum value for the sensor
98*4882a593Smuzhiyun *
99*4882a593Smuzhiyun * Can sleep
100*4882a593Smuzhiyun */
is_valid_adc(uint16_t adc_val,uint16_t min,uint16_t max)101*4882a593Smuzhiyun static int is_valid_adc(uint16_t adc_val, uint16_t min, uint16_t max)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun return (adc_val >= min) && (adc_val <= max);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /**
107*4882a593Smuzhiyun * adc_to_temp - converts the ADC code to temperature in C
108*4882a593Smuzhiyun * @direct: true if ths channel is direct index
109*4882a593Smuzhiyun * @adc_val: the adc_val that needs to be converted
110*4882a593Smuzhiyun * @tp: temperature return value
111*4882a593Smuzhiyun *
112*4882a593Smuzhiyun * Linear approximation is used to covert the skin adc value into temperature.
113*4882a593Smuzhiyun * This technique is used to avoid very long look-up table to get
114*4882a593Smuzhiyun * the appropriate temp value from ADC value.
115*4882a593Smuzhiyun * The adc code vs sensor temp curve is split into five parts
116*4882a593Smuzhiyun * to achieve very close approximate temp value with less than
117*4882a593Smuzhiyun * 0.5C error
118*4882a593Smuzhiyun */
adc_to_temp(int direct,uint16_t adc_val,int * tp)119*4882a593Smuzhiyun static int adc_to_temp(int direct, uint16_t adc_val, int *tp)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun int temp;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* Direct conversion for die temperature */
124*4882a593Smuzhiyun if (direct) {
125*4882a593Smuzhiyun if (is_valid_adc(adc_val, MSIC_DIE_ADC_MIN, MSIC_DIE_ADC_MAX)) {
126*4882a593Smuzhiyun *tp = to_msic_die_temp(adc_val) * 1000;
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun return -ERANGE;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if (!is_valid_adc(adc_val, ADC_MIN, ADC_MAX))
133*4882a593Smuzhiyun return -ERANGE;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* Linear approximation for skin temperature */
136*4882a593Smuzhiyun if (adc_val > ADC_VAL0C)
137*4882a593Smuzhiyun temp = 177 - (adc_val/5);
138*4882a593Smuzhiyun else if ((adc_val <= ADC_VAL0C) && (adc_val > ADC_VAL20C))
139*4882a593Smuzhiyun temp = 111 - (adc_val/8);
140*4882a593Smuzhiyun else if ((adc_val <= ADC_VAL20C) && (adc_val > ADC_VAL40C))
141*4882a593Smuzhiyun temp = 92 - (adc_val/10);
142*4882a593Smuzhiyun else if ((adc_val <= ADC_VAL40C) && (adc_val > ADC_VAL60C))
143*4882a593Smuzhiyun temp = 91 - (adc_val/10);
144*4882a593Smuzhiyun else
145*4882a593Smuzhiyun temp = 112 - (adc_val/6);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* Convert temperature in celsius to milli degree celsius */
148*4882a593Smuzhiyun *tp = temp * 1000;
149*4882a593Smuzhiyun return 0;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /**
153*4882a593Smuzhiyun * mid_read_temp - read sensors for temperature
154*4882a593Smuzhiyun * @temp: holds the current temperature for the sensor after reading
155*4882a593Smuzhiyun *
156*4882a593Smuzhiyun * reads the adc_code from the channel and converts it to real
157*4882a593Smuzhiyun * temperature. The converted value is stored in temp.
158*4882a593Smuzhiyun *
159*4882a593Smuzhiyun * Can sleep
160*4882a593Smuzhiyun */
mid_read_temp(struct thermal_zone_device * tzd,int * temp)161*4882a593Smuzhiyun static int mid_read_temp(struct thermal_zone_device *tzd, int *temp)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun struct thermal_device_info *td_info = tzd->devdata;
164*4882a593Smuzhiyun uint16_t adc_val, addr;
165*4882a593Smuzhiyun uint8_t data = 0;
166*4882a593Smuzhiyun int ret;
167*4882a593Smuzhiyun int curr_temp;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun addr = td_info->chnl_addr;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* Enable the msic for conversion before reading */
172*4882a593Smuzhiyun ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, MSIC_ADCRRDATA_ENBL);
173*4882a593Smuzhiyun if (ret)
174*4882a593Smuzhiyun return ret;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* Re-toggle the RRDATARD bit (temporary workaround) */
177*4882a593Smuzhiyun ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, MSIC_ADCTHERM_ENBL);
178*4882a593Smuzhiyun if (ret)
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* Read the higher bits of data */
182*4882a593Smuzhiyun ret = intel_msic_reg_read(addr, &data);
183*4882a593Smuzhiyun if (ret)
184*4882a593Smuzhiyun return ret;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* Shift bits to accommodate the lower two data bits */
187*4882a593Smuzhiyun adc_val = (data << 2);
188*4882a593Smuzhiyun addr++;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun ret = intel_msic_reg_read(addr, &data);/* Read lower bits */
191*4882a593Smuzhiyun if (ret)
192*4882a593Smuzhiyun return ret;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* Adding lower two bits to the higher bits */
195*4882a593Smuzhiyun data &= 03;
196*4882a593Smuzhiyun adc_val += data;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* Convert ADC value to temperature */
199*4882a593Smuzhiyun ret = adc_to_temp(td_info->direct, adc_val, &curr_temp);
200*4882a593Smuzhiyun if (ret == 0)
201*4882a593Smuzhiyun *temp = td_info->curr_temp = curr_temp;
202*4882a593Smuzhiyun return ret;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /**
206*4882a593Smuzhiyun * configure_adc - enables/disables the ADC for conversion
207*4882a593Smuzhiyun * @val: zero: disables the ADC non-zero:enables the ADC
208*4882a593Smuzhiyun *
209*4882a593Smuzhiyun * Enable/Disable the ADC depending on the argument
210*4882a593Smuzhiyun *
211*4882a593Smuzhiyun * Can sleep
212*4882a593Smuzhiyun */
configure_adc(int val)213*4882a593Smuzhiyun static int configure_adc(int val)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun int ret;
216*4882a593Smuzhiyun uint8_t data;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL1, &data);
219*4882a593Smuzhiyun if (ret)
220*4882a593Smuzhiyun return ret;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (val) {
223*4882a593Smuzhiyun /* Enable and start the ADC */
224*4882a593Smuzhiyun data |= (MSIC_ADC_ENBL | MSIC_ADC_START);
225*4882a593Smuzhiyun } else {
226*4882a593Smuzhiyun /* Just stop the ADC */
227*4882a593Smuzhiyun data &= (~MSIC_ADC_START);
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun return intel_msic_reg_write(INTEL_MSIC_ADC1CNTL1, data);
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /**
233*4882a593Smuzhiyun * set_up_therm_channel - enable thermal channel for conversion
234*4882a593Smuzhiyun * @base_addr: index of free msic ADC channel
235*4882a593Smuzhiyun *
236*4882a593Smuzhiyun * Enable all the three channels for conversion
237*4882a593Smuzhiyun *
238*4882a593Smuzhiyun * Can sleep
239*4882a593Smuzhiyun */
set_up_therm_channel(u16 base_addr)240*4882a593Smuzhiyun static int set_up_therm_channel(u16 base_addr)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun int ret;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* Enable all the sensor channels */
245*4882a593Smuzhiyun ret = intel_msic_reg_write(base_addr, SKIN_SENSOR0_CODE);
246*4882a593Smuzhiyun if (ret)
247*4882a593Smuzhiyun return ret;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun ret = intel_msic_reg_write(base_addr + 1, SKIN_SENSOR1_CODE);
250*4882a593Smuzhiyun if (ret)
251*4882a593Smuzhiyun return ret;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun ret = intel_msic_reg_write(base_addr + 2, SYS_SENSOR_CODE);
254*4882a593Smuzhiyun if (ret)
255*4882a593Smuzhiyun return ret;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun /* Since this is the last channel, set the stop bit
258*4882a593Smuzhiyun * to 1 by ORing the DIE_SENSOR_CODE with 0x10 */
259*4882a593Smuzhiyun ret = intel_msic_reg_write(base_addr + 3,
260*4882a593Smuzhiyun (MSIC_DIE_SENSOR_CODE | 0x10));
261*4882a593Smuzhiyun if (ret)
262*4882a593Smuzhiyun return ret;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* Enable ADC and start it */
265*4882a593Smuzhiyun return configure_adc(1);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun /**
269*4882a593Smuzhiyun * reset_stopbit - sets the stop bit to 0 on the given channel
270*4882a593Smuzhiyun * @addr: address of the channel
271*4882a593Smuzhiyun *
272*4882a593Smuzhiyun * Can sleep
273*4882a593Smuzhiyun */
reset_stopbit(uint16_t addr)274*4882a593Smuzhiyun static int reset_stopbit(uint16_t addr)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun int ret;
277*4882a593Smuzhiyun uint8_t data;
278*4882a593Smuzhiyun ret = intel_msic_reg_read(addr, &data);
279*4882a593Smuzhiyun if (ret)
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun /* Set the stop bit to zero */
282*4882a593Smuzhiyun return intel_msic_reg_write(addr, (data & 0xEF));
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /**
286*4882a593Smuzhiyun * find_free_channel - finds an empty channel for conversion
287*4882a593Smuzhiyun *
288*4882a593Smuzhiyun * If the ADC is not enabled then start using 0th channel
289*4882a593Smuzhiyun * itself. Otherwise find an empty channel by looking for a
290*4882a593Smuzhiyun * channel in which the stopbit is set to 1. returns the index
291*4882a593Smuzhiyun * of the first free channel if succeeds or an error code.
292*4882a593Smuzhiyun *
293*4882a593Smuzhiyun * Context: can sleep
294*4882a593Smuzhiyun *
295*4882a593Smuzhiyun * FIXME: Ultimately the channel allocator will move into the intel_scu_ipc
296*4882a593Smuzhiyun * code.
297*4882a593Smuzhiyun */
find_free_channel(void)298*4882a593Smuzhiyun static int find_free_channel(void)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun int ret;
301*4882a593Smuzhiyun int i;
302*4882a593Smuzhiyun uint8_t data;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* check whether ADC is enabled */
305*4882a593Smuzhiyun ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL1, &data);
306*4882a593Smuzhiyun if (ret)
307*4882a593Smuzhiyun return ret;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun if ((data & MSIC_ADC_ENBL) == 0)
310*4882a593Smuzhiyun return 0;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /* ADC is already enabled; Looking for an empty channel */
313*4882a593Smuzhiyun for (i = 0; i < ADC_CHANLS_MAX; i++) {
314*4882a593Smuzhiyun ret = intel_msic_reg_read(ADC_CHNL_START_ADDR + i, &data);
315*4882a593Smuzhiyun if (ret)
316*4882a593Smuzhiyun return ret;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun if (data & MSIC_STOPBIT_MASK) {
319*4882a593Smuzhiyun ret = i;
320*4882a593Smuzhiyun break;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun return (ret > ADC_LOOP_MAX) ? (-EINVAL) : ret;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /**
327*4882a593Smuzhiyun * mid_initialize_adc - initializing the ADC
328*4882a593Smuzhiyun * @dev: our device structure
329*4882a593Smuzhiyun *
330*4882a593Smuzhiyun * Initialize the ADC for reading thermistor values. Can sleep.
331*4882a593Smuzhiyun */
mid_initialize_adc(struct device * dev)332*4882a593Smuzhiyun static int mid_initialize_adc(struct device *dev)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun u8 data;
335*4882a593Smuzhiyun u16 base_addr;
336*4882a593Smuzhiyun int ret;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /*
339*4882a593Smuzhiyun * Ensure that adctherm is disabled before we
340*4882a593Smuzhiyun * initialize the ADC
341*4882a593Smuzhiyun */
342*4882a593Smuzhiyun ret = intel_msic_reg_read(INTEL_MSIC_ADC1CNTL3, &data);
343*4882a593Smuzhiyun if (ret)
344*4882a593Smuzhiyun return ret;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun data &= ~MSIC_ADCTHERM_MASK;
347*4882a593Smuzhiyun ret = intel_msic_reg_write(INTEL_MSIC_ADC1CNTL3, data);
348*4882a593Smuzhiyun if (ret)
349*4882a593Smuzhiyun return ret;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun /* Index of the first channel in which the stop bit is set */
352*4882a593Smuzhiyun channel_index = find_free_channel();
353*4882a593Smuzhiyun if (channel_index < 0) {
354*4882a593Smuzhiyun dev_err(dev, "No free ADC channels");
355*4882a593Smuzhiyun return channel_index;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun base_addr = ADC_CHNL_START_ADDR + channel_index;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun if (!(channel_index == 0 || channel_index == ADC_LOOP_MAX)) {
361*4882a593Smuzhiyun /* Reset stop bit for channels other than 0 and 12 */
362*4882a593Smuzhiyun ret = reset_stopbit(base_addr);
363*4882a593Smuzhiyun if (ret)
364*4882a593Smuzhiyun return ret;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /* Index of the first free channel */
367*4882a593Smuzhiyun base_addr++;
368*4882a593Smuzhiyun channel_index++;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun ret = set_up_therm_channel(base_addr);
372*4882a593Smuzhiyun if (ret) {
373*4882a593Smuzhiyun dev_err(dev, "unable to enable ADC");
374*4882a593Smuzhiyun return ret;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun dev_dbg(dev, "ADC initialization successful");
377*4882a593Smuzhiyun return ret;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /**
381*4882a593Smuzhiyun * initialize_sensor - sets default temp and timer ranges
382*4882a593Smuzhiyun * @index: index of the sensor
383*4882a593Smuzhiyun *
384*4882a593Smuzhiyun * Context: can sleep
385*4882a593Smuzhiyun */
initialize_sensor(int index)386*4882a593Smuzhiyun static struct thermal_device_info *initialize_sensor(int index)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun struct thermal_device_info *td_info =
389*4882a593Smuzhiyun kzalloc(sizeof(struct thermal_device_info), GFP_KERNEL);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun if (!td_info)
392*4882a593Smuzhiyun return NULL;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun /* Set the base addr of the channel for this sensor */
395*4882a593Smuzhiyun td_info->chnl_addr = ADC_DATA_START_ADDR + 2 * (channel_index + index);
396*4882a593Smuzhiyun /* Sensor 3 is direct conversion */
397*4882a593Smuzhiyun if (index == 3)
398*4882a593Smuzhiyun td_info->direct = 1;
399*4882a593Smuzhiyun return td_info;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
403*4882a593Smuzhiyun /**
404*4882a593Smuzhiyun * mid_thermal_resume - resume routine
405*4882a593Smuzhiyun * @dev: device structure
406*4882a593Smuzhiyun *
407*4882a593Smuzhiyun * mid thermal resume: re-initializes the adc. Can sleep.
408*4882a593Smuzhiyun */
mid_thermal_resume(struct device * dev)409*4882a593Smuzhiyun static int mid_thermal_resume(struct device *dev)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun return mid_initialize_adc(dev);
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun /**
415*4882a593Smuzhiyun * mid_thermal_suspend - suspend routine
416*4882a593Smuzhiyun * @dev: device structure
417*4882a593Smuzhiyun *
418*4882a593Smuzhiyun * mid thermal suspend implements the suspend functionality
419*4882a593Smuzhiyun * by stopping the ADC. Can sleep.
420*4882a593Smuzhiyun */
mid_thermal_suspend(struct device * dev)421*4882a593Smuzhiyun static int mid_thermal_suspend(struct device *dev)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun /*
424*4882a593Smuzhiyun * This just stops the ADC and does not disable it.
425*4882a593Smuzhiyun * temporary workaround until we have a generic ADC driver.
426*4882a593Smuzhiyun * If 0 is passed, it disables the ADC.
427*4882a593Smuzhiyun */
428*4882a593Smuzhiyun return configure_adc(0);
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun #endif
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(mid_thermal_pm,
433*4882a593Smuzhiyun mid_thermal_suspend, mid_thermal_resume);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /**
436*4882a593Smuzhiyun * read_curr_temp - reads the current temperature and stores in temp
437*4882a593Smuzhiyun * @temp: holds the current temperature value after reading
438*4882a593Smuzhiyun *
439*4882a593Smuzhiyun * Can sleep
440*4882a593Smuzhiyun */
read_curr_temp(struct thermal_zone_device * tzd,int * temp)441*4882a593Smuzhiyun static int read_curr_temp(struct thermal_zone_device *tzd, int *temp)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun WARN_ON(tzd == NULL);
444*4882a593Smuzhiyun return mid_read_temp(tzd, temp);
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun /* Can't be const */
448*4882a593Smuzhiyun static struct thermal_zone_device_ops tzd_ops = {
449*4882a593Smuzhiyun .get_temp = read_curr_temp,
450*4882a593Smuzhiyun };
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun /**
453*4882a593Smuzhiyun * mid_thermal_probe - mfld thermal initialize
454*4882a593Smuzhiyun * @pdev: platform device structure
455*4882a593Smuzhiyun *
456*4882a593Smuzhiyun * mid thermal probe initializes the hardware and registers
457*4882a593Smuzhiyun * all the sensors with the generic thermal framework. Can sleep.
458*4882a593Smuzhiyun */
mid_thermal_probe(struct platform_device * pdev)459*4882a593Smuzhiyun static int mid_thermal_probe(struct platform_device *pdev)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun static char *name[MSIC_THERMAL_SENSORS] = {
462*4882a593Smuzhiyun "skin0", "skin1", "sys", "msicdie"
463*4882a593Smuzhiyun };
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun int ret;
466*4882a593Smuzhiyun int i;
467*4882a593Smuzhiyun struct platform_info *pinfo;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun pinfo = devm_kzalloc(&pdev->dev, sizeof(struct platform_info),
470*4882a593Smuzhiyun GFP_KERNEL);
471*4882a593Smuzhiyun if (!pinfo)
472*4882a593Smuzhiyun return -ENOMEM;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun /* Initializing the hardware */
475*4882a593Smuzhiyun ret = mid_initialize_adc(&pdev->dev);
476*4882a593Smuzhiyun if (ret) {
477*4882a593Smuzhiyun dev_err(&pdev->dev, "ADC init failed");
478*4882a593Smuzhiyun return ret;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun /* Register each sensor with the generic thermal framework*/
482*4882a593Smuzhiyun for (i = 0; i < MSIC_THERMAL_SENSORS; i++) {
483*4882a593Smuzhiyun struct thermal_device_info *td_info = initialize_sensor(i);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun if (!td_info) {
486*4882a593Smuzhiyun ret = -ENOMEM;
487*4882a593Smuzhiyun goto err;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun pinfo->tzd[i] = thermal_zone_device_register(name[i],
490*4882a593Smuzhiyun 0, 0, td_info, &tzd_ops, NULL, 0, 0);
491*4882a593Smuzhiyun if (IS_ERR(pinfo->tzd[i])) {
492*4882a593Smuzhiyun kfree(td_info);
493*4882a593Smuzhiyun ret = PTR_ERR(pinfo->tzd[i]);
494*4882a593Smuzhiyun goto err;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun ret = thermal_zone_device_enable(pinfo->tzd[i]);
497*4882a593Smuzhiyun if (ret) {
498*4882a593Smuzhiyun kfree(td_info);
499*4882a593Smuzhiyun thermal_zone_device_unregister(pinfo->tzd[i]);
500*4882a593Smuzhiyun goto err;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun pinfo->pdev = pdev;
505*4882a593Smuzhiyun platform_set_drvdata(pdev, pinfo);
506*4882a593Smuzhiyun return 0;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun err:
509*4882a593Smuzhiyun while (--i >= 0) {
510*4882a593Smuzhiyun kfree(pinfo->tzd[i]->devdata);
511*4882a593Smuzhiyun thermal_zone_device_unregister(pinfo->tzd[i]);
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun configure_adc(0);
514*4882a593Smuzhiyun return ret;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun /**
518*4882a593Smuzhiyun * mid_thermal_remove - mfld thermal finalize
519*4882a593Smuzhiyun * @dev: platform device structure
520*4882a593Smuzhiyun *
521*4882a593Smuzhiyun * MLFD thermal remove unregisters all the sensors from the generic
522*4882a593Smuzhiyun * thermal framework. Can sleep.
523*4882a593Smuzhiyun */
mid_thermal_remove(struct platform_device * pdev)524*4882a593Smuzhiyun static int mid_thermal_remove(struct platform_device *pdev)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun int i;
527*4882a593Smuzhiyun struct platform_info *pinfo = platform_get_drvdata(pdev);
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun for (i = 0; i < MSIC_THERMAL_SENSORS; i++) {
530*4882a593Smuzhiyun kfree(pinfo->tzd[i]->devdata);
531*4882a593Smuzhiyun thermal_zone_device_unregister(pinfo->tzd[i]);
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* Stop the ADC */
535*4882a593Smuzhiyun return configure_adc(0);
536*4882a593Smuzhiyun }
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun #define DRIVER_NAME "msic_thermal"
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun static const struct platform_device_id therm_id_table[] = {
541*4882a593Smuzhiyun { DRIVER_NAME, 1 },
542*4882a593Smuzhiyun { }
543*4882a593Smuzhiyun };
544*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, therm_id_table);
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun static struct platform_driver mid_thermal_driver = {
547*4882a593Smuzhiyun .driver = {
548*4882a593Smuzhiyun .name = DRIVER_NAME,
549*4882a593Smuzhiyun .pm = &mid_thermal_pm,
550*4882a593Smuzhiyun },
551*4882a593Smuzhiyun .probe = mid_thermal_probe,
552*4882a593Smuzhiyun .remove = mid_thermal_remove,
553*4882a593Smuzhiyun .id_table = therm_id_table,
554*4882a593Smuzhiyun };
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun module_platform_driver(mid_thermal_driver);
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun MODULE_AUTHOR("Durgadoss R <durgadoss.r@intel.com>");
559*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel Medfield Platform Thermal Driver");
560*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
561