xref: /OK3568_Linux_fs/kernel/drivers/platform/x86/intel_int0002_vgpio.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Intel INT0002 "Virtual GPIO" driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Loosely based on android x86 kernel code which is:
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright (c) 2014, Intel Corporation.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Author: Dyut Kumar Sil <dyut.k.sil@intel.com>
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * Some peripherals on Bay Trail and Cherry Trail platforms signal a Power
14*4882a593Smuzhiyun  * Management Event (PME) to the Power Management Controller (PMC) to wakeup
15*4882a593Smuzhiyun  * the system. When this happens software needs to clear the PME bus 0 status
16*4882a593Smuzhiyun  * bit in the GPE0a_STS register to avoid an IRQ storm on IRQ 9.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * This is modelled in ACPI through the INT0002 ACPI device, which is
19*4882a593Smuzhiyun  * called a "Virtual GPIO controller" in ACPI because it defines the event
20*4882a593Smuzhiyun  * handler to call when the PME triggers through _AEI and _L02 / _E02
21*4882a593Smuzhiyun  * methods as would be done for a real GPIO interrupt in ACPI. Note this
22*4882a593Smuzhiyun  * is a hack to define an AML event handler for the PME while using existing
23*4882a593Smuzhiyun  * ACPI mechanisms, this is not a real GPIO at all.
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * This driver will bind to the INT0002 device, and register as a GPIO
26*4882a593Smuzhiyun  * controller, letting gpiolib-acpi.c call the _L02 handler as it would
27*4882a593Smuzhiyun  * for a real GPIO controller.
28*4882a593Smuzhiyun  */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #include <linux/acpi.h>
31*4882a593Smuzhiyun #include <linux/bitmap.h>
32*4882a593Smuzhiyun #include <linux/gpio/driver.h>
33*4882a593Smuzhiyun #include <linux/interrupt.h>
34*4882a593Smuzhiyun #include <linux/io.h>
35*4882a593Smuzhiyun #include <linux/kernel.h>
36*4882a593Smuzhiyun #include <linux/module.h>
37*4882a593Smuzhiyun #include <linux/platform_device.h>
38*4882a593Smuzhiyun #include <linux/slab.h>
39*4882a593Smuzhiyun #include <linux/suspend.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #include <asm/cpu_device_id.h>
42*4882a593Smuzhiyun #include <asm/intel-family.h>
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define DRV_NAME			"INT0002 Virtual GPIO"
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* For some reason the virtual GPIO pin tied to the GPE is numbered pin 2 */
47*4882a593Smuzhiyun #define GPE0A_PME_B0_VIRT_GPIO_PIN	2
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define GPE0A_PME_B0_STS_BIT		BIT(13)
50*4882a593Smuzhiyun #define GPE0A_PME_B0_EN_BIT		BIT(13)
51*4882a593Smuzhiyun #define GPE0A_STS_PORT			0x420
52*4882a593Smuzhiyun #define GPE0A_EN_PORT			0x428
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun struct int0002_data {
55*4882a593Smuzhiyun 	struct gpio_chip chip;
56*4882a593Smuzhiyun 	int parent_irq;
57*4882a593Smuzhiyun 	int wake_enable_count;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun  * As this is not a real GPIO at all, but just a hack to model an event in
62*4882a593Smuzhiyun  * ACPI the get / set functions are dummy functions.
63*4882a593Smuzhiyun  */
64*4882a593Smuzhiyun 
int0002_gpio_get(struct gpio_chip * chip,unsigned int offset)65*4882a593Smuzhiyun static int int0002_gpio_get(struct gpio_chip *chip, unsigned int offset)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	return 0;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
int0002_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)70*4882a593Smuzhiyun static void int0002_gpio_set(struct gpio_chip *chip, unsigned int offset,
71*4882a593Smuzhiyun 			     int value)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
int0002_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)75*4882a593Smuzhiyun static int int0002_gpio_direction_output(struct gpio_chip *chip,
76*4882a593Smuzhiyun 					 unsigned int offset, int value)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
int0002_irq_ack(struct irq_data * data)81*4882a593Smuzhiyun static void int0002_irq_ack(struct irq_data *data)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun 	outl(GPE0A_PME_B0_STS_BIT, GPE0A_STS_PORT);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
int0002_irq_unmask(struct irq_data * data)86*4882a593Smuzhiyun static void int0002_irq_unmask(struct irq_data *data)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	u32 gpe_en_reg;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	gpe_en_reg = inl(GPE0A_EN_PORT);
91*4882a593Smuzhiyun 	gpe_en_reg |= GPE0A_PME_B0_EN_BIT;
92*4882a593Smuzhiyun 	outl(gpe_en_reg, GPE0A_EN_PORT);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
int0002_irq_mask(struct irq_data * data)95*4882a593Smuzhiyun static void int0002_irq_mask(struct irq_data *data)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	u32 gpe_en_reg;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	gpe_en_reg = inl(GPE0A_EN_PORT);
100*4882a593Smuzhiyun 	gpe_en_reg &= ~GPE0A_PME_B0_EN_BIT;
101*4882a593Smuzhiyun 	outl(gpe_en_reg, GPE0A_EN_PORT);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
int0002_irq_set_wake(struct irq_data * data,unsigned int on)104*4882a593Smuzhiyun static int int0002_irq_set_wake(struct irq_data *data, unsigned int on)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
107*4882a593Smuzhiyun 	struct int0002_data *int0002 = container_of(chip, struct int0002_data, chip);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	/*
110*4882a593Smuzhiyun 	 * Applying of the wakeup flag to our parent IRQ is delayed till system
111*4882a593Smuzhiyun 	 * suspend, because we only want to do this when using s2idle.
112*4882a593Smuzhiyun 	 */
113*4882a593Smuzhiyun 	if (on)
114*4882a593Smuzhiyun 		int0002->wake_enable_count++;
115*4882a593Smuzhiyun 	else
116*4882a593Smuzhiyun 		int0002->wake_enable_count--;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	return 0;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun 
int0002_irq(int irq,void * data)121*4882a593Smuzhiyun static irqreturn_t int0002_irq(int irq, void *data)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	struct gpio_chip *chip = data;
124*4882a593Smuzhiyun 	u32 gpe_sts_reg;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	gpe_sts_reg = inl(GPE0A_STS_PORT);
127*4882a593Smuzhiyun 	if (!(gpe_sts_reg & GPE0A_PME_B0_STS_BIT))
128*4882a593Smuzhiyun 		return IRQ_NONE;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	generic_handle_irq(irq_find_mapping(chip->irq.domain,
131*4882a593Smuzhiyun 					    GPE0A_PME_B0_VIRT_GPIO_PIN));
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	pm_wakeup_hard_event(chip->parent);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	return IRQ_HANDLED;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
int0002_check_wake(void * data)138*4882a593Smuzhiyun static bool int0002_check_wake(void *data)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	u32 gpe_sts_reg;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	gpe_sts_reg = inl(GPE0A_STS_PORT);
143*4882a593Smuzhiyun 	return (gpe_sts_reg & GPE0A_PME_B0_STS_BIT);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun static struct irq_chip int0002_irqchip = {
147*4882a593Smuzhiyun 	.name			= DRV_NAME,
148*4882a593Smuzhiyun 	.irq_ack		= int0002_irq_ack,
149*4882a593Smuzhiyun 	.irq_mask		= int0002_irq_mask,
150*4882a593Smuzhiyun 	.irq_unmask		= int0002_irq_unmask,
151*4882a593Smuzhiyun 	.irq_set_wake		= int0002_irq_set_wake,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun static const struct x86_cpu_id int0002_cpu_ids[] = {
155*4882a593Smuzhiyun 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
156*4882a593Smuzhiyun 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
157*4882a593Smuzhiyun 	{}
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
int0002_init_irq_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)160*4882a593Smuzhiyun static void int0002_init_irq_valid_mask(struct gpio_chip *chip,
161*4882a593Smuzhiyun 					unsigned long *valid_mask,
162*4882a593Smuzhiyun 					unsigned int ngpios)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	bitmap_clear(valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
int0002_probe(struct platform_device * pdev)167*4882a593Smuzhiyun static int int0002_probe(struct platform_device *pdev)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
170*4882a593Smuzhiyun 	const struct x86_cpu_id *cpu_id;
171*4882a593Smuzhiyun 	struct int0002_data *int0002;
172*4882a593Smuzhiyun 	struct gpio_irq_chip *girq;
173*4882a593Smuzhiyun 	struct gpio_chip *chip;
174*4882a593Smuzhiyun 	int irq, ret;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	/* Menlow has a different INT0002 device? <sigh> */
177*4882a593Smuzhiyun 	cpu_id = x86_match_cpu(int0002_cpu_ids);
178*4882a593Smuzhiyun 	if (!cpu_id)
179*4882a593Smuzhiyun 		return -ENODEV;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
182*4882a593Smuzhiyun 	if (irq < 0)
183*4882a593Smuzhiyun 		return irq;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	int0002 = devm_kzalloc(dev, sizeof(*int0002), GFP_KERNEL);
186*4882a593Smuzhiyun 	if (!int0002)
187*4882a593Smuzhiyun 		return -ENOMEM;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	int0002->parent_irq = irq;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	chip = &int0002->chip;
192*4882a593Smuzhiyun 	chip->label = DRV_NAME;
193*4882a593Smuzhiyun 	chip->parent = dev;
194*4882a593Smuzhiyun 	chip->owner = THIS_MODULE;
195*4882a593Smuzhiyun 	chip->get = int0002_gpio_get;
196*4882a593Smuzhiyun 	chip->set = int0002_gpio_set;
197*4882a593Smuzhiyun 	chip->direction_input = int0002_gpio_get;
198*4882a593Smuzhiyun 	chip->direction_output = int0002_gpio_direction_output;
199*4882a593Smuzhiyun 	chip->base = -1;
200*4882a593Smuzhiyun 	chip->ngpio = GPE0A_PME_B0_VIRT_GPIO_PIN + 1;
201*4882a593Smuzhiyun 	chip->irq.init_valid_mask = int0002_init_irq_valid_mask;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	/*
204*4882a593Smuzhiyun 	 * We directly request the irq here instead of passing a flow-handler
205*4882a593Smuzhiyun 	 * to gpiochip_set_chained_irqchip, because the irq is shared.
206*4882a593Smuzhiyun 	 * FIXME: augment this if we managed to pull handling of shared
207*4882a593Smuzhiyun 	 * IRQs into gpiolib.
208*4882a593Smuzhiyun 	 */
209*4882a593Smuzhiyun 	ret = devm_request_irq(dev, irq, int0002_irq,
210*4882a593Smuzhiyun 			       IRQF_SHARED, "INT0002", chip);
211*4882a593Smuzhiyun 	if (ret) {
212*4882a593Smuzhiyun 		dev_err(dev, "Error requesting IRQ %d: %d\n", irq, ret);
213*4882a593Smuzhiyun 		return ret;
214*4882a593Smuzhiyun 	}
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	girq = &chip->irq;
217*4882a593Smuzhiyun 	girq->chip = &int0002_irqchip;
218*4882a593Smuzhiyun 	/* This let us handle the parent IRQ in the driver */
219*4882a593Smuzhiyun 	girq->parent_handler = NULL;
220*4882a593Smuzhiyun 	girq->num_parents = 0;
221*4882a593Smuzhiyun 	girq->parents = NULL;
222*4882a593Smuzhiyun 	girq->default_type = IRQ_TYPE_NONE;
223*4882a593Smuzhiyun 	girq->handler = handle_edge_irq;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	ret = devm_gpiochip_add_data(dev, chip, NULL);
226*4882a593Smuzhiyun 	if (ret) {
227*4882a593Smuzhiyun 		dev_err(dev, "Error adding gpio chip: %d\n", ret);
228*4882a593Smuzhiyun 		return ret;
229*4882a593Smuzhiyun 	}
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	acpi_register_wakeup_handler(irq, int0002_check_wake, NULL);
232*4882a593Smuzhiyun 	device_init_wakeup(dev, true);
233*4882a593Smuzhiyun 	dev_set_drvdata(dev, int0002);
234*4882a593Smuzhiyun 	return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
int0002_remove(struct platform_device * pdev)237*4882a593Smuzhiyun static int int0002_remove(struct platform_device *pdev)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	device_init_wakeup(&pdev->dev, false);
240*4882a593Smuzhiyun 	acpi_unregister_wakeup_handler(int0002_check_wake, NULL);
241*4882a593Smuzhiyun 	return 0;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun 
int0002_suspend(struct device * dev)244*4882a593Smuzhiyun static int int0002_suspend(struct device *dev)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	struct int0002_data *int0002 = dev_get_drvdata(dev);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	/*
249*4882a593Smuzhiyun 	 * The INT0002 parent IRQ is often shared with the ACPI GPE IRQ, don't
250*4882a593Smuzhiyun 	 * muck with it when firmware based suspend is used, otherwise we may
251*4882a593Smuzhiyun 	 * cause spurious wakeups from firmware managed suspend.
252*4882a593Smuzhiyun 	 */
253*4882a593Smuzhiyun 	if (!pm_suspend_via_firmware() && int0002->wake_enable_count)
254*4882a593Smuzhiyun 		enable_irq_wake(int0002->parent_irq);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	return 0;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
int0002_resume(struct device * dev)259*4882a593Smuzhiyun static int int0002_resume(struct device *dev)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	struct int0002_data *int0002 = dev_get_drvdata(dev);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	if (!pm_suspend_via_firmware() && int0002->wake_enable_count)
264*4882a593Smuzhiyun 		disable_irq_wake(int0002->parent_irq);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	return 0;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun static const struct dev_pm_ops int0002_pm_ops = {
270*4882a593Smuzhiyun 	.suspend = int0002_suspend,
271*4882a593Smuzhiyun 	.resume = int0002_resume,
272*4882a593Smuzhiyun };
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun static const struct acpi_device_id int0002_acpi_ids[] = {
275*4882a593Smuzhiyun 	{ "INT0002", 0 },
276*4882a593Smuzhiyun 	{ },
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, int0002_acpi_ids);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun static struct platform_driver int0002_driver = {
281*4882a593Smuzhiyun 	.driver = {
282*4882a593Smuzhiyun 		.name			= DRV_NAME,
283*4882a593Smuzhiyun 		.acpi_match_table	= int0002_acpi_ids,
284*4882a593Smuzhiyun 		.pm			= &int0002_pm_ops,
285*4882a593Smuzhiyun 	},
286*4882a593Smuzhiyun 	.probe	= int0002_probe,
287*4882a593Smuzhiyun 	.remove	= int0002_remove,
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun module_platform_driver(int0002_driver);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
293*4882a593Smuzhiyun MODULE_DESCRIPTION("Intel INT0002 Virtual GPIO driver");
294*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
295