xref: /OK3568_Linux_fs/kernel/drivers/platform/x86/intel_bxtwc_tmu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Intel BXT Whiskey Cove PMIC TMU driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2016 Intel Corporation. All rights reserved.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This driver adds TMU (Time Management Unit) support for Intel BXT platform.
8*4882a593Smuzhiyun  * It enables the alarm wake-up functionality in the TMU unit of Whiskey Cove
9*4882a593Smuzhiyun  * PMIC.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/mfd/intel_soc_pmic.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define BXTWC_TMUIRQ		0x4fb6
19*4882a593Smuzhiyun #define BXTWC_MIRQLVL1		0x4e0e
20*4882a593Smuzhiyun #define BXTWC_MTMUIRQ_REG	0x4fb7
21*4882a593Smuzhiyun #define BXTWC_MIRQLVL1_MTMU	BIT(1)
22*4882a593Smuzhiyun #define BXTWC_TMU_WK_ALRM	BIT(1)
23*4882a593Smuzhiyun #define BXTWC_TMU_SYS_ALRM	BIT(2)
24*4882a593Smuzhiyun #define BXTWC_TMU_ALRM_MASK	(BXTWC_TMU_WK_ALRM | BXTWC_TMU_SYS_ALRM)
25*4882a593Smuzhiyun #define BXTWC_TMU_ALRM_IRQ	(BXTWC_TMU_WK_ALRM | BXTWC_TMU_SYS_ALRM)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun struct wcove_tmu {
28*4882a593Smuzhiyun 	int irq;
29*4882a593Smuzhiyun 	struct device *dev;
30*4882a593Smuzhiyun 	struct regmap *regmap;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
bxt_wcove_tmu_irq_handler(int irq,void * data)33*4882a593Smuzhiyun static irqreturn_t bxt_wcove_tmu_irq_handler(int irq, void *data)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun 	struct wcove_tmu *wctmu = data;
36*4882a593Smuzhiyun 	unsigned int tmu_irq;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	/* Read TMU interrupt reg */
39*4882a593Smuzhiyun 	regmap_read(wctmu->regmap, BXTWC_TMUIRQ, &tmu_irq);
40*4882a593Smuzhiyun 	if (tmu_irq & BXTWC_TMU_ALRM_IRQ) {
41*4882a593Smuzhiyun 		/* clear TMU irq */
42*4882a593Smuzhiyun 		regmap_write(wctmu->regmap, BXTWC_TMUIRQ, tmu_irq);
43*4882a593Smuzhiyun 		return IRQ_HANDLED;
44*4882a593Smuzhiyun 	}
45*4882a593Smuzhiyun 	return IRQ_NONE;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun 
bxt_wcove_tmu_probe(struct platform_device * pdev)48*4882a593Smuzhiyun static int bxt_wcove_tmu_probe(struct platform_device *pdev)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
51*4882a593Smuzhiyun 	struct regmap_irq_chip_data *regmap_irq_chip;
52*4882a593Smuzhiyun 	struct wcove_tmu *wctmu;
53*4882a593Smuzhiyun 	int ret, virq, irq;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	wctmu = devm_kzalloc(&pdev->dev, sizeof(*wctmu), GFP_KERNEL);
56*4882a593Smuzhiyun 	if (!wctmu)
57*4882a593Smuzhiyun 		return -ENOMEM;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	wctmu->dev = &pdev->dev;
60*4882a593Smuzhiyun 	wctmu->regmap = pmic->regmap;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
63*4882a593Smuzhiyun 	if (irq < 0)
64*4882a593Smuzhiyun 		return irq;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	regmap_irq_chip = pmic->irq_chip_data_tmu;
67*4882a593Smuzhiyun 	virq = regmap_irq_get_virq(regmap_irq_chip, irq);
68*4882a593Smuzhiyun 	if (virq < 0) {
69*4882a593Smuzhiyun 		dev_err(&pdev->dev,
70*4882a593Smuzhiyun 			"failed to get virtual interrupt=%d\n", irq);
71*4882a593Smuzhiyun 		return virq;
72*4882a593Smuzhiyun 	}
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(&pdev->dev, virq,
75*4882a593Smuzhiyun 					NULL, bxt_wcove_tmu_irq_handler,
76*4882a593Smuzhiyun 					IRQF_ONESHOT, "bxt_wcove_tmu", wctmu);
77*4882a593Smuzhiyun 	if (ret) {
78*4882a593Smuzhiyun 		dev_err(&pdev->dev, "request irq failed: %d,virq: %d\n",
79*4882a593Smuzhiyun 							ret, virq);
80*4882a593Smuzhiyun 		return ret;
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 	wctmu->irq = virq;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	/* Unmask TMU second level Wake & System alarm */
85*4882a593Smuzhiyun 	regmap_update_bits(wctmu->regmap, BXTWC_MTMUIRQ_REG,
86*4882a593Smuzhiyun 				  BXTWC_TMU_ALRM_MASK, 0);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	platform_set_drvdata(pdev, wctmu);
89*4882a593Smuzhiyun 	return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
bxt_wcove_tmu_remove(struct platform_device * pdev)92*4882a593Smuzhiyun static int bxt_wcove_tmu_remove(struct platform_device *pdev)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	struct wcove_tmu *wctmu = platform_get_drvdata(pdev);
95*4882a593Smuzhiyun 	unsigned int val;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	/* Mask TMU interrupts */
98*4882a593Smuzhiyun 	regmap_read(wctmu->regmap, BXTWC_MIRQLVL1, &val);
99*4882a593Smuzhiyun 	regmap_write(wctmu->regmap, BXTWC_MIRQLVL1,
100*4882a593Smuzhiyun 			val | BXTWC_MIRQLVL1_MTMU);
101*4882a593Smuzhiyun 	regmap_read(wctmu->regmap, BXTWC_MTMUIRQ_REG, &val);
102*4882a593Smuzhiyun 	regmap_write(wctmu->regmap, BXTWC_MTMUIRQ_REG,
103*4882a593Smuzhiyun 			val | BXTWC_TMU_ALRM_MASK);
104*4882a593Smuzhiyun 	return 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
bxtwc_tmu_suspend(struct device * dev)108*4882a593Smuzhiyun static int bxtwc_tmu_suspend(struct device *dev)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	struct wcove_tmu *wctmu = dev_get_drvdata(dev);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	enable_irq_wake(wctmu->irq);
113*4882a593Smuzhiyun 	return 0;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun 
bxtwc_tmu_resume(struct device * dev)116*4882a593Smuzhiyun static int bxtwc_tmu_resume(struct device *dev)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	struct wcove_tmu *wctmu = dev_get_drvdata(dev);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	disable_irq_wake(wctmu->irq);
121*4882a593Smuzhiyun 	return 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun #endif
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(bxtwc_tmu_pm_ops, bxtwc_tmu_suspend, bxtwc_tmu_resume);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun static const struct platform_device_id bxt_wcove_tmu_id_table[] = {
128*4882a593Smuzhiyun 	{ .name = "bxt_wcove_tmu" },
129*4882a593Smuzhiyun 	{},
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, bxt_wcove_tmu_id_table);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static struct platform_driver bxt_wcove_tmu_driver = {
134*4882a593Smuzhiyun 	.probe = bxt_wcove_tmu_probe,
135*4882a593Smuzhiyun 	.remove = bxt_wcove_tmu_remove,
136*4882a593Smuzhiyun 	.driver = {
137*4882a593Smuzhiyun 		.name = "bxt_wcove_tmu",
138*4882a593Smuzhiyun 		.pm     = &bxtwc_tmu_pm_ops,
139*4882a593Smuzhiyun 	},
140*4882a593Smuzhiyun 	.id_table = bxt_wcove_tmu_id_table,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun module_platform_driver(bxt_wcove_tmu_driver);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
146*4882a593Smuzhiyun MODULE_AUTHOR("Nilesh Bacchewar <nilesh.bacchewar@intel.com>");
147*4882a593Smuzhiyun MODULE_DESCRIPTION("BXT Whiskey Cove TMU Driver");
148