1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019, Mellanox Technologies. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __MLXBF_TMFIFO_REGS_H__ 7*4882a593Smuzhiyun #define __MLXBF_TMFIFO_REGS_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun #include <linux/bits.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_DATA 0x00 13*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_STS 0x08 14*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_STS__LENGTH 0x0001 15*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT 0 16*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH 9 17*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL 0 18*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0) 19*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0) 20*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL 0x10 21*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__LENGTH 0x0001 22*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT 0 23*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH 8 24*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL 128 25*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0) 26*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0) 27*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT 8 28*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH 8 29*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL 128 30*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0) 31*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8) 32*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT 32 33*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH 9 34*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL 256 35*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0) 36*4882a593Smuzhiyun #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32) 37*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_DATA 0x00 38*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_STS 0x08 39*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_STS__LENGTH 0x0001 40*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT 0 41*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH 9 42*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL 0 43*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0) 44*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0) 45*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL 0x10 46*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__LENGTH 0x0001 47*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT 0 48*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH 8 49*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL 128 50*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0) 51*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0) 52*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT 8 53*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH 8 54*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL 128 55*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0) 56*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8) 57*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT 32 58*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH 9 59*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL 256 60*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0) 61*4882a593Smuzhiyun #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */ 64