1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017 Sanechips Technology Co., Ltd. 4*4882a593Smuzhiyun * Copyright 2017 Linaro Ltd. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __PINCTRL_ZX_H 8*4882a593Smuzhiyun #define __PINCTRL_ZX_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /** 11*4882a593Smuzhiyun * struct zx_mux_desc - hardware mux descriptor 12*4882a593Smuzhiyun * @name: mux function name 13*4882a593Smuzhiyun * @muxval: mux register bit value 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct zx_mux_desc { 16*4882a593Smuzhiyun const char *name; 17*4882a593Smuzhiyun u8 muxval; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /** 21*4882a593Smuzhiyun * struct zx_pin_data - hardware per-pin data 22*4882a593Smuzhiyun * @aon_pin: whether it's an AON pin 23*4882a593Smuzhiyun * @offset: register offset within TOP pinmux controller 24*4882a593Smuzhiyun * @bitpos: bit position within TOP pinmux register 25*4882a593Smuzhiyun * @width: bit width within TOP pinmux register 26*4882a593Smuzhiyun * @coffset: pinconf register offset within AON controller 27*4882a593Smuzhiyun * @cbitpos: pinconf bit position within AON register 28*4882a593Smuzhiyun * @muxes: available mux function names and corresponding register values 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * Unlike TOP pinmux and AON pinconf registers which are arranged pretty 31*4882a593Smuzhiyun * arbitrarily, AON pinmux register bits are well organized per pin id, and 32*4882a593Smuzhiyun * each pin occupies two bits, so that we can calculate the AON register offset 33*4882a593Smuzhiyun * and bit position from pin id. Thus, we only need to define TOP pinmux and 34*4882a593Smuzhiyun * AON pinconf register data for the pin. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun struct zx_pin_data { 37*4882a593Smuzhiyun bool aon_pin; 38*4882a593Smuzhiyun u16 offset; 39*4882a593Smuzhiyun u16 bitpos; 40*4882a593Smuzhiyun u16 width; 41*4882a593Smuzhiyun u16 coffset; 42*4882a593Smuzhiyun u16 cbitpos; 43*4882a593Smuzhiyun struct zx_mux_desc *muxes; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct zx_pinctrl_soc_info { 47*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins; 48*4882a593Smuzhiyun unsigned int npins; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) { \ 52*4882a593Smuzhiyun .number = pin, \ 53*4882a593Smuzhiyun .name = #pin, \ 54*4882a593Smuzhiyun .drv_data = &(struct zx_pin_data) { \ 55*4882a593Smuzhiyun .aon_pin = false, \ 56*4882a593Smuzhiyun .offset = off, \ 57*4882a593Smuzhiyun .bitpos = bp, \ 58*4882a593Smuzhiyun .width = wd, \ 59*4882a593Smuzhiyun .coffset = coff, \ 60*4882a593Smuzhiyun .cbitpos = cbp, \ 61*4882a593Smuzhiyun .muxes = (struct zx_mux_desc[]) { \ 62*4882a593Smuzhiyun __VA_ARGS__, { } }, \ 63*4882a593Smuzhiyun }, \ 64*4882a593Smuzhiyun } 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define AON_PIN(pin, off, bp, wd, coff, cbp, ...) { \ 67*4882a593Smuzhiyun .number = pin, \ 68*4882a593Smuzhiyun .name = #pin, \ 69*4882a593Smuzhiyun .drv_data = &(struct zx_pin_data) { \ 70*4882a593Smuzhiyun .aon_pin = true, \ 71*4882a593Smuzhiyun .offset = off, \ 72*4882a593Smuzhiyun .bitpos = bp, \ 73*4882a593Smuzhiyun .width = wd, \ 74*4882a593Smuzhiyun .coffset = coff, \ 75*4882a593Smuzhiyun .cbitpos = cbp, \ 76*4882a593Smuzhiyun .muxes = (struct zx_mux_desc[]) { \ 77*4882a593Smuzhiyun __VA_ARGS__, { } }, \ 78*4882a593Smuzhiyun }, \ 79*4882a593Smuzhiyun } 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define TOP_MUX(_val, _name) { \ 84*4882a593Smuzhiyun .name = _name, \ 85*4882a593Smuzhiyun .muxval = _val, \ 86*4882a593Smuzhiyun } 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * When the flag is set, it's a mux configuration for an AON pin that sits in 90*4882a593Smuzhiyun * AON register. Otherwise, it's one for AON pin but sitting in TOP register. 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define AON_MUX_FLAG BIT(7) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define AON_MUX(_val, _name) { \ 95*4882a593Smuzhiyun .name = _name, \ 96*4882a593Smuzhiyun .muxval = _val | AON_MUX_FLAG, \ 97*4882a593Smuzhiyun } 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun int zx_pinctrl_init(struct platform_device *pdev, 100*4882a593Smuzhiyun struct zx_pinctrl_soc_info *info); 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* __PINCTRL_ZX_H */ 103