1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Pinctrl driver for the Wondermedia SoC's
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/gpio/driver.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_irq.h>
15*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
16*4882a593Smuzhiyun #include <linux/pinctrl/machine.h>
17*4882a593Smuzhiyun #include <linux/pinctrl/pinconf.h>
18*4882a593Smuzhiyun #include <linux/pinctrl/pinconf-generic.h>
19*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
20*4882a593Smuzhiyun #include <linux/pinctrl/pinmux.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "pinctrl-wmt.h"
25*4882a593Smuzhiyun
wmt_setbits(struct wmt_pinctrl_data * data,u32 reg,u32 mask)26*4882a593Smuzhiyun static inline void wmt_setbits(struct wmt_pinctrl_data *data, u32 reg,
27*4882a593Smuzhiyun u32 mask)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun u32 val;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun val = readl_relaxed(data->base + reg);
32*4882a593Smuzhiyun val |= mask;
33*4882a593Smuzhiyun writel_relaxed(val, data->base + reg);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
wmt_clearbits(struct wmt_pinctrl_data * data,u32 reg,u32 mask)36*4882a593Smuzhiyun static inline void wmt_clearbits(struct wmt_pinctrl_data *data, u32 reg,
37*4882a593Smuzhiyun u32 mask)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun u32 val;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun val = readl_relaxed(data->base + reg);
42*4882a593Smuzhiyun val &= ~mask;
43*4882a593Smuzhiyun writel_relaxed(val, data->base + reg);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun enum wmt_func_sel {
47*4882a593Smuzhiyun WMT_FSEL_GPIO_IN = 0,
48*4882a593Smuzhiyun WMT_FSEL_GPIO_OUT = 1,
49*4882a593Smuzhiyun WMT_FSEL_ALT = 2,
50*4882a593Smuzhiyun WMT_FSEL_COUNT = 3,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static const char * const wmt_functions[WMT_FSEL_COUNT] = {
54*4882a593Smuzhiyun [WMT_FSEL_GPIO_IN] = "gpio_in",
55*4882a593Smuzhiyun [WMT_FSEL_GPIO_OUT] = "gpio_out",
56*4882a593Smuzhiyun [WMT_FSEL_ALT] = "alt",
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
wmt_pmx_get_functions_count(struct pinctrl_dev * pctldev)59*4882a593Smuzhiyun static int wmt_pmx_get_functions_count(struct pinctrl_dev *pctldev)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun return WMT_FSEL_COUNT;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
wmt_pmx_get_function_name(struct pinctrl_dev * pctldev,unsigned selector)64*4882a593Smuzhiyun static const char *wmt_pmx_get_function_name(struct pinctrl_dev *pctldev,
65*4882a593Smuzhiyun unsigned selector)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun return wmt_functions[selector];
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
wmt_pmx_get_function_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)70*4882a593Smuzhiyun static int wmt_pmx_get_function_groups(struct pinctrl_dev *pctldev,
71*4882a593Smuzhiyun unsigned selector,
72*4882a593Smuzhiyun const char * const **groups,
73*4882a593Smuzhiyun unsigned * const num_groups)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* every pin does every function */
78*4882a593Smuzhiyun *groups = data->groups;
79*4882a593Smuzhiyun *num_groups = data->ngroups;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
wmt_set_pinmux(struct wmt_pinctrl_data * data,unsigned func,unsigned pin)84*4882a593Smuzhiyun static int wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func,
85*4882a593Smuzhiyun unsigned pin)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun u32 bank = WMT_BANK_FROM_PIN(pin);
88*4882a593Smuzhiyun u32 bit = WMT_BIT_FROM_PIN(pin);
89*4882a593Smuzhiyun u32 reg_en = data->banks[bank].reg_en;
90*4882a593Smuzhiyun u32 reg_dir = data->banks[bank].reg_dir;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (reg_dir == NO_REG) {
93*4882a593Smuzhiyun dev_err(data->dev, "pin:%d no direction register defined\n",
94*4882a593Smuzhiyun pin);
95*4882a593Smuzhiyun return -EINVAL;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /*
99*4882a593Smuzhiyun * If reg_en == NO_REG, we assume it is a dedicated GPIO and cannot be
100*4882a593Smuzhiyun * disabled (as on VT8500) and that no alternate function is available.
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun switch (func) {
103*4882a593Smuzhiyun case WMT_FSEL_GPIO_IN:
104*4882a593Smuzhiyun if (reg_en != NO_REG)
105*4882a593Smuzhiyun wmt_setbits(data, reg_en, BIT(bit));
106*4882a593Smuzhiyun wmt_clearbits(data, reg_dir, BIT(bit));
107*4882a593Smuzhiyun break;
108*4882a593Smuzhiyun case WMT_FSEL_GPIO_OUT:
109*4882a593Smuzhiyun if (reg_en != NO_REG)
110*4882a593Smuzhiyun wmt_setbits(data, reg_en, BIT(bit));
111*4882a593Smuzhiyun wmt_setbits(data, reg_dir, BIT(bit));
112*4882a593Smuzhiyun break;
113*4882a593Smuzhiyun case WMT_FSEL_ALT:
114*4882a593Smuzhiyun if (reg_en == NO_REG) {
115*4882a593Smuzhiyun dev_err(data->dev, "pin:%d no alt function available\n",
116*4882a593Smuzhiyun pin);
117*4882a593Smuzhiyun return -EINVAL;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun wmt_clearbits(data, reg_en, BIT(bit));
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
wmt_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned func_selector,unsigned group_selector)125*4882a593Smuzhiyun static int wmt_pmx_set_mux(struct pinctrl_dev *pctldev,
126*4882a593Smuzhiyun unsigned func_selector,
127*4882a593Smuzhiyun unsigned group_selector)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
130*4882a593Smuzhiyun u32 pinnum = data->pins[group_selector].number;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun return wmt_set_pinmux(data, func_selector, pinnum);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
wmt_pmx_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)135*4882a593Smuzhiyun static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
136*4882a593Smuzhiyun struct pinctrl_gpio_range *range,
137*4882a593Smuzhiyun unsigned offset)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* disable by setting GPIO_IN */
142*4882a593Smuzhiyun wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, offset);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
wmt_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset,bool input)145*4882a593Smuzhiyun static int wmt_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
146*4882a593Smuzhiyun struct pinctrl_gpio_range *range,
147*4882a593Smuzhiyun unsigned offset,
148*4882a593Smuzhiyun bool input)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun wmt_set_pinmux(data, (input ? WMT_FSEL_GPIO_IN : WMT_FSEL_GPIO_OUT),
153*4882a593Smuzhiyun offset);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun static const struct pinmux_ops wmt_pinmux_ops = {
159*4882a593Smuzhiyun .get_functions_count = wmt_pmx_get_functions_count,
160*4882a593Smuzhiyun .get_function_name = wmt_pmx_get_function_name,
161*4882a593Smuzhiyun .get_function_groups = wmt_pmx_get_function_groups,
162*4882a593Smuzhiyun .set_mux = wmt_pmx_set_mux,
163*4882a593Smuzhiyun .gpio_disable_free = wmt_pmx_gpio_disable_free,
164*4882a593Smuzhiyun .gpio_set_direction = wmt_pmx_gpio_set_direction,
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
wmt_get_groups_count(struct pinctrl_dev * pctldev)167*4882a593Smuzhiyun static int wmt_get_groups_count(struct pinctrl_dev *pctldev)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return data->ngroups;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
wmt_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)174*4882a593Smuzhiyun static const char *wmt_get_group_name(struct pinctrl_dev *pctldev,
175*4882a593Smuzhiyun unsigned selector)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun return data->groups[selector];
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
wmt_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * num_pins)182*4882a593Smuzhiyun static int wmt_get_group_pins(struct pinctrl_dev *pctldev,
183*4882a593Smuzhiyun unsigned selector,
184*4882a593Smuzhiyun const unsigned **pins,
185*4882a593Smuzhiyun unsigned *num_pins)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun *pins = &data->pins[selector].number;
190*4882a593Smuzhiyun *num_pins = 1;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun return 0;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
wmt_pctl_find_group_by_pin(struct wmt_pinctrl_data * data,u32 pin)195*4882a593Smuzhiyun static int wmt_pctl_find_group_by_pin(struct wmt_pinctrl_data *data, u32 pin)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun int i;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun for (i = 0; i < data->npins; i++) {
200*4882a593Smuzhiyun if (data->pins[i].number == pin)
201*4882a593Smuzhiyun return i;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun return -EINVAL;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
wmt_pctl_dt_node_to_map_func(struct wmt_pinctrl_data * data,struct device_node * np,u32 pin,u32 fnum,struct pinctrl_map ** maps)207*4882a593Smuzhiyun static int wmt_pctl_dt_node_to_map_func(struct wmt_pinctrl_data *data,
208*4882a593Smuzhiyun struct device_node *np,
209*4882a593Smuzhiyun u32 pin, u32 fnum,
210*4882a593Smuzhiyun struct pinctrl_map **maps)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun int group;
213*4882a593Smuzhiyun struct pinctrl_map *map = *maps;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (fnum >= ARRAY_SIZE(wmt_functions)) {
216*4882a593Smuzhiyun dev_err(data->dev, "invalid wm,function %d\n", fnum);
217*4882a593Smuzhiyun return -EINVAL;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun group = wmt_pctl_find_group_by_pin(data, pin);
221*4882a593Smuzhiyun if (group < 0) {
222*4882a593Smuzhiyun dev_err(data->dev, "unable to match pin %d to group\n", pin);
223*4882a593Smuzhiyun return group;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun map->type = PIN_MAP_TYPE_MUX_GROUP;
227*4882a593Smuzhiyun map->data.mux.group = data->groups[group];
228*4882a593Smuzhiyun map->data.mux.function = wmt_functions[fnum];
229*4882a593Smuzhiyun (*maps)++;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun return 0;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data * data,struct device_node * np,u32 pin,u32 pull,struct pinctrl_map ** maps)234*4882a593Smuzhiyun static int wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data *data,
235*4882a593Smuzhiyun struct device_node *np,
236*4882a593Smuzhiyun u32 pin, u32 pull,
237*4882a593Smuzhiyun struct pinctrl_map **maps)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun int group;
240*4882a593Smuzhiyun unsigned long *configs;
241*4882a593Smuzhiyun struct pinctrl_map *map = *maps;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun if (pull > 2) {
244*4882a593Smuzhiyun dev_err(data->dev, "invalid wm,pull %d\n", pull);
245*4882a593Smuzhiyun return -EINVAL;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun group = wmt_pctl_find_group_by_pin(data, pin);
249*4882a593Smuzhiyun if (group < 0) {
250*4882a593Smuzhiyun dev_err(data->dev, "unable to match pin %d to group\n", pin);
251*4882a593Smuzhiyun return group;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun configs = kzalloc(sizeof(*configs), GFP_KERNEL);
255*4882a593Smuzhiyun if (!configs)
256*4882a593Smuzhiyun return -ENOMEM;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun switch (pull) {
259*4882a593Smuzhiyun case 0:
260*4882a593Smuzhiyun configs[0] = PIN_CONFIG_BIAS_DISABLE;
261*4882a593Smuzhiyun break;
262*4882a593Smuzhiyun case 1:
263*4882a593Smuzhiyun configs[0] = PIN_CONFIG_BIAS_PULL_DOWN;
264*4882a593Smuzhiyun break;
265*4882a593Smuzhiyun case 2:
266*4882a593Smuzhiyun configs[0] = PIN_CONFIG_BIAS_PULL_UP;
267*4882a593Smuzhiyun break;
268*4882a593Smuzhiyun default:
269*4882a593Smuzhiyun configs[0] = PIN_CONFIG_BIAS_DISABLE;
270*4882a593Smuzhiyun dev_err(data->dev, "invalid pull state %d - disabling\n", pull);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun map->type = PIN_MAP_TYPE_CONFIGS_PIN;
274*4882a593Smuzhiyun map->data.configs.group_or_pin = data->groups[group];
275*4882a593Smuzhiyun map->data.configs.configs = configs;
276*4882a593Smuzhiyun map->data.configs.num_configs = 1;
277*4882a593Smuzhiyun (*maps)++;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return 0;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
wmt_pctl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * maps,unsigned num_maps)282*4882a593Smuzhiyun static void wmt_pctl_dt_free_map(struct pinctrl_dev *pctldev,
283*4882a593Smuzhiyun struct pinctrl_map *maps,
284*4882a593Smuzhiyun unsigned num_maps)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun int i;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun for (i = 0; i < num_maps; i++)
289*4882a593Smuzhiyun if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
290*4882a593Smuzhiyun kfree(maps[i].data.configs.configs);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun kfree(maps);
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
wmt_pctl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)295*4882a593Smuzhiyun static int wmt_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
296*4882a593Smuzhiyun struct device_node *np,
297*4882a593Smuzhiyun struct pinctrl_map **map,
298*4882a593Smuzhiyun unsigned *num_maps)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun struct pinctrl_map *maps, *cur_map;
301*4882a593Smuzhiyun struct property *pins, *funcs, *pulls;
302*4882a593Smuzhiyun u32 pin, func, pull;
303*4882a593Smuzhiyun int num_pins, num_funcs, num_pulls, maps_per_pin;
304*4882a593Smuzhiyun int i, err;
305*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun pins = of_find_property(np, "wm,pins", NULL);
308*4882a593Smuzhiyun if (!pins) {
309*4882a593Smuzhiyun dev_err(data->dev, "missing wmt,pins property\n");
310*4882a593Smuzhiyun return -EINVAL;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun funcs = of_find_property(np, "wm,function", NULL);
314*4882a593Smuzhiyun pulls = of_find_property(np, "wm,pull", NULL);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun if (!funcs && !pulls) {
317*4882a593Smuzhiyun dev_err(data->dev, "neither wm,function nor wm,pull specified\n");
318*4882a593Smuzhiyun return -EINVAL;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /*
322*4882a593Smuzhiyun * The following lines calculate how many values are defined for each
323*4882a593Smuzhiyun * of the properties.
324*4882a593Smuzhiyun */
325*4882a593Smuzhiyun num_pins = pins->length / sizeof(u32);
326*4882a593Smuzhiyun num_funcs = funcs ? (funcs->length / sizeof(u32)) : 0;
327*4882a593Smuzhiyun num_pulls = pulls ? (pulls->length / sizeof(u32)) : 0;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if (num_funcs > 1 && num_funcs != num_pins) {
330*4882a593Smuzhiyun dev_err(data->dev, "wm,function must have 1 or %d entries\n",
331*4882a593Smuzhiyun num_pins);
332*4882a593Smuzhiyun return -EINVAL;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (num_pulls > 1 && num_pulls != num_pins) {
336*4882a593Smuzhiyun dev_err(data->dev, "wm,pull must have 1 or %d entries\n",
337*4882a593Smuzhiyun num_pins);
338*4882a593Smuzhiyun return -EINVAL;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun maps_per_pin = 0;
342*4882a593Smuzhiyun if (num_funcs)
343*4882a593Smuzhiyun maps_per_pin++;
344*4882a593Smuzhiyun if (num_pulls)
345*4882a593Smuzhiyun maps_per_pin++;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
348*4882a593Smuzhiyun GFP_KERNEL);
349*4882a593Smuzhiyun if (!maps)
350*4882a593Smuzhiyun return -ENOMEM;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun for (i = 0; i < num_pins; i++) {
353*4882a593Smuzhiyun err = of_property_read_u32_index(np, "wm,pins", i, &pin);
354*4882a593Smuzhiyun if (err)
355*4882a593Smuzhiyun goto fail;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun if (pin >= (data->nbanks * 32)) {
358*4882a593Smuzhiyun dev_err(data->dev, "invalid wm,pins value\n");
359*4882a593Smuzhiyun err = -EINVAL;
360*4882a593Smuzhiyun goto fail;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun if (num_funcs) {
364*4882a593Smuzhiyun err = of_property_read_u32_index(np, "wm,function",
365*4882a593Smuzhiyun (num_funcs > 1 ? i : 0), &func);
366*4882a593Smuzhiyun if (err)
367*4882a593Smuzhiyun goto fail;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun err = wmt_pctl_dt_node_to_map_func(data, np, pin, func,
370*4882a593Smuzhiyun &cur_map);
371*4882a593Smuzhiyun if (err)
372*4882a593Smuzhiyun goto fail;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun if (num_pulls) {
376*4882a593Smuzhiyun err = of_property_read_u32_index(np, "wm,pull",
377*4882a593Smuzhiyun (num_pulls > 1 ? i : 0), &pull);
378*4882a593Smuzhiyun if (err)
379*4882a593Smuzhiyun goto fail;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun err = wmt_pctl_dt_node_to_map_pull(data, np, pin, pull,
382*4882a593Smuzhiyun &cur_map);
383*4882a593Smuzhiyun if (err)
384*4882a593Smuzhiyun goto fail;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun *map = maps;
388*4882a593Smuzhiyun *num_maps = num_pins * maps_per_pin;
389*4882a593Smuzhiyun return 0;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun /*
392*4882a593Smuzhiyun * The fail path removes any maps that have been allocated. The fail path is
393*4882a593Smuzhiyun * only called from code after maps has been kzalloc'd. It is also safe to
394*4882a593Smuzhiyun * pass 'num_pins * maps_per_pin' as the map count even though we probably
395*4882a593Smuzhiyun * failed before all the mappings were read as all maps are allocated at once,
396*4882a593Smuzhiyun * and configs are only allocated for .type = PIN_MAP_TYPE_CONFIGS_PIN - there
397*4882a593Smuzhiyun * is no failpath where a config can be allocated without .type being set.
398*4882a593Smuzhiyun */
399*4882a593Smuzhiyun fail:
400*4882a593Smuzhiyun wmt_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
401*4882a593Smuzhiyun return err;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun static const struct pinctrl_ops wmt_pctl_ops = {
405*4882a593Smuzhiyun .get_groups_count = wmt_get_groups_count,
406*4882a593Smuzhiyun .get_group_name = wmt_get_group_name,
407*4882a593Smuzhiyun .get_group_pins = wmt_get_group_pins,
408*4882a593Smuzhiyun .dt_node_to_map = wmt_pctl_dt_node_to_map,
409*4882a593Smuzhiyun .dt_free_map = wmt_pctl_dt_free_map,
410*4882a593Smuzhiyun };
411*4882a593Smuzhiyun
wmt_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)412*4882a593Smuzhiyun static int wmt_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
413*4882a593Smuzhiyun unsigned long *config)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun return -ENOTSUPP;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
wmt_pinconf_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * configs,unsigned num_configs)418*4882a593Smuzhiyun static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
419*4882a593Smuzhiyun unsigned long *configs, unsigned num_configs)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
422*4882a593Smuzhiyun enum pin_config_param param;
423*4882a593Smuzhiyun u32 arg;
424*4882a593Smuzhiyun u32 bank = WMT_BANK_FROM_PIN(pin);
425*4882a593Smuzhiyun u32 bit = WMT_BIT_FROM_PIN(pin);
426*4882a593Smuzhiyun u32 reg_pull_en = data->banks[bank].reg_pull_en;
427*4882a593Smuzhiyun u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg;
428*4882a593Smuzhiyun int i;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun if ((reg_pull_en == NO_REG) || (reg_pull_cfg == NO_REG)) {
431*4882a593Smuzhiyun dev_err(data->dev, "bias functions not supported on pin %d\n",
432*4882a593Smuzhiyun pin);
433*4882a593Smuzhiyun return -EINVAL;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun for (i = 0; i < num_configs; i++) {
437*4882a593Smuzhiyun param = pinconf_to_config_param(configs[i]);
438*4882a593Smuzhiyun arg = pinconf_to_config_argument(configs[i]);
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun if ((param == PIN_CONFIG_BIAS_PULL_DOWN) ||
441*4882a593Smuzhiyun (param == PIN_CONFIG_BIAS_PULL_UP)) {
442*4882a593Smuzhiyun if (arg == 0)
443*4882a593Smuzhiyun param = PIN_CONFIG_BIAS_DISABLE;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun switch (param) {
447*4882a593Smuzhiyun case PIN_CONFIG_BIAS_DISABLE:
448*4882a593Smuzhiyun wmt_clearbits(data, reg_pull_en, BIT(bit));
449*4882a593Smuzhiyun break;
450*4882a593Smuzhiyun case PIN_CONFIG_BIAS_PULL_DOWN:
451*4882a593Smuzhiyun wmt_clearbits(data, reg_pull_cfg, BIT(bit));
452*4882a593Smuzhiyun wmt_setbits(data, reg_pull_en, BIT(bit));
453*4882a593Smuzhiyun break;
454*4882a593Smuzhiyun case PIN_CONFIG_BIAS_PULL_UP:
455*4882a593Smuzhiyun wmt_setbits(data, reg_pull_cfg, BIT(bit));
456*4882a593Smuzhiyun wmt_setbits(data, reg_pull_en, BIT(bit));
457*4882a593Smuzhiyun break;
458*4882a593Smuzhiyun default:
459*4882a593Smuzhiyun dev_err(data->dev, "unknown pinconf param\n");
460*4882a593Smuzhiyun return -EINVAL;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun } /* for each config */
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun return 0;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun static const struct pinconf_ops wmt_pinconf_ops = {
468*4882a593Smuzhiyun .pin_config_get = wmt_pinconf_get,
469*4882a593Smuzhiyun .pin_config_set = wmt_pinconf_set,
470*4882a593Smuzhiyun };
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun static struct pinctrl_desc wmt_desc = {
473*4882a593Smuzhiyun .owner = THIS_MODULE,
474*4882a593Smuzhiyun .name = "pinctrl-wmt",
475*4882a593Smuzhiyun .pctlops = &wmt_pctl_ops,
476*4882a593Smuzhiyun .pmxops = &wmt_pinmux_ops,
477*4882a593Smuzhiyun .confops = &wmt_pinconf_ops,
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun
wmt_gpio_get_direction(struct gpio_chip * chip,unsigned offset)480*4882a593Smuzhiyun static int wmt_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun struct wmt_pinctrl_data *data = gpiochip_get_data(chip);
483*4882a593Smuzhiyun u32 bank = WMT_BANK_FROM_PIN(offset);
484*4882a593Smuzhiyun u32 bit = WMT_BIT_FROM_PIN(offset);
485*4882a593Smuzhiyun u32 reg_dir = data->banks[bank].reg_dir;
486*4882a593Smuzhiyun u32 val;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun val = readl_relaxed(data->base + reg_dir);
489*4882a593Smuzhiyun if (val & BIT(bit))
490*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_OUT;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_IN;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
wmt_gpio_get_value(struct gpio_chip * chip,unsigned offset)495*4882a593Smuzhiyun static int wmt_gpio_get_value(struct gpio_chip *chip, unsigned offset)
496*4882a593Smuzhiyun {
497*4882a593Smuzhiyun struct wmt_pinctrl_data *data = gpiochip_get_data(chip);
498*4882a593Smuzhiyun u32 bank = WMT_BANK_FROM_PIN(offset);
499*4882a593Smuzhiyun u32 bit = WMT_BIT_FROM_PIN(offset);
500*4882a593Smuzhiyun u32 reg_data_in = data->banks[bank].reg_data_in;
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun if (reg_data_in == NO_REG) {
503*4882a593Smuzhiyun dev_err(data->dev, "no data in register defined\n");
504*4882a593Smuzhiyun return -EINVAL;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit));
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun
wmt_gpio_set_value(struct gpio_chip * chip,unsigned offset,int val)510*4882a593Smuzhiyun static void wmt_gpio_set_value(struct gpio_chip *chip, unsigned offset,
511*4882a593Smuzhiyun int val)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun struct wmt_pinctrl_data *data = gpiochip_get_data(chip);
514*4882a593Smuzhiyun u32 bank = WMT_BANK_FROM_PIN(offset);
515*4882a593Smuzhiyun u32 bit = WMT_BIT_FROM_PIN(offset);
516*4882a593Smuzhiyun u32 reg_data_out = data->banks[bank].reg_data_out;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun if (reg_data_out == NO_REG) {
519*4882a593Smuzhiyun dev_err(data->dev, "no data out register defined\n");
520*4882a593Smuzhiyun return;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun if (val)
524*4882a593Smuzhiyun wmt_setbits(data, reg_data_out, BIT(bit));
525*4882a593Smuzhiyun else
526*4882a593Smuzhiyun wmt_clearbits(data, reg_data_out, BIT(bit));
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
wmt_gpio_direction_input(struct gpio_chip * chip,unsigned offset)529*4882a593Smuzhiyun static int wmt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun return pinctrl_gpio_direction_input(chip->base + offset);
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
wmt_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)534*4882a593Smuzhiyun static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
535*4882a593Smuzhiyun int value)
536*4882a593Smuzhiyun {
537*4882a593Smuzhiyun wmt_gpio_set_value(chip, offset, value);
538*4882a593Smuzhiyun return pinctrl_gpio_direction_output(chip->base + offset);
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun static const struct gpio_chip wmt_gpio_chip = {
542*4882a593Smuzhiyun .label = "gpio-wmt",
543*4882a593Smuzhiyun .owner = THIS_MODULE,
544*4882a593Smuzhiyun .request = gpiochip_generic_request,
545*4882a593Smuzhiyun .free = gpiochip_generic_free,
546*4882a593Smuzhiyun .get_direction = wmt_gpio_get_direction,
547*4882a593Smuzhiyun .direction_input = wmt_gpio_direction_input,
548*4882a593Smuzhiyun .direction_output = wmt_gpio_direction_output,
549*4882a593Smuzhiyun .get = wmt_gpio_get_value,
550*4882a593Smuzhiyun .set = wmt_gpio_set_value,
551*4882a593Smuzhiyun .can_sleep = false,
552*4882a593Smuzhiyun };
553*4882a593Smuzhiyun
wmt_pinctrl_probe(struct platform_device * pdev,struct wmt_pinctrl_data * data)554*4882a593Smuzhiyun int wmt_pinctrl_probe(struct platform_device *pdev,
555*4882a593Smuzhiyun struct wmt_pinctrl_data *data)
556*4882a593Smuzhiyun {
557*4882a593Smuzhiyun int err;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun data->base = devm_platform_ioremap_resource(pdev, 0);
560*4882a593Smuzhiyun if (IS_ERR(data->base))
561*4882a593Smuzhiyun return PTR_ERR(data->base);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun wmt_desc.pins = data->pins;
564*4882a593Smuzhiyun wmt_desc.npins = data->npins;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun data->gpio_chip = wmt_gpio_chip;
567*4882a593Smuzhiyun data->gpio_chip.parent = &pdev->dev;
568*4882a593Smuzhiyun data->gpio_chip.of_node = pdev->dev.of_node;
569*4882a593Smuzhiyun data->gpio_chip.ngpio = data->nbanks * 32;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun platform_set_drvdata(pdev, data);
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun data->dev = &pdev->dev;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun data->pctl_dev = devm_pinctrl_register(&pdev->dev, &wmt_desc, data);
576*4882a593Smuzhiyun if (IS_ERR(data->pctl_dev)) {
577*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register pinctrl\n");
578*4882a593Smuzhiyun return PTR_ERR(data->pctl_dev);
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun err = gpiochip_add_data(&data->gpio_chip, data);
582*4882a593Smuzhiyun if (err) {
583*4882a593Smuzhiyun dev_err(&pdev->dev, "could not add GPIO chip\n");
584*4882a593Smuzhiyun return err;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun err = gpiochip_add_pin_range(&data->gpio_chip, dev_name(data->dev),
588*4882a593Smuzhiyun 0, 0, data->nbanks * 32);
589*4882a593Smuzhiyun if (err)
590*4882a593Smuzhiyun goto fail_range;
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun dev_info(&pdev->dev, "Pin controller initialized\n");
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun return 0;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun fail_range:
597*4882a593Smuzhiyun gpiochip_remove(&data->gpio_chip);
598*4882a593Smuzhiyun return err;
599*4882a593Smuzhiyun }
600