1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2015-2017 Socionext Inc.
4*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __PINCTRL_UNIPHIER_H__
8*4882a593Smuzhiyun #define __PINCTRL_UNIPHIER_H__
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/bits.h>
11*4882a593Smuzhiyun #include <linux/build_bug.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/types.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct platform_device;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* input enable control register bit */
18*4882a593Smuzhiyun #define UNIPHIER_PIN_IECTRL_SHIFT 0
19*4882a593Smuzhiyun #define UNIPHIER_PIN_IECTRL_BITS 3
20*4882a593Smuzhiyun #define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
21*4882a593Smuzhiyun - 1)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* drive strength control register number */
24*4882a593Smuzhiyun #define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \
25*4882a593Smuzhiyun (UNIPHIER_PIN_IECTRL_BITS))
26*4882a593Smuzhiyun #define UNIPHIER_PIN_DRVCTRL_BITS 9
27*4882a593Smuzhiyun #define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
28*4882a593Smuzhiyun - 1)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* drive control type */
31*4882a593Smuzhiyun #define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
32*4882a593Smuzhiyun (UNIPHIER_PIN_DRVCTRL_BITS))
33*4882a593Smuzhiyun #define UNIPHIER_PIN_DRV_TYPE_BITS 3
34*4882a593Smuzhiyun #define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
35*4882a593Smuzhiyun - 1)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* pull-up / pull-down register number */
38*4882a593Smuzhiyun #define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
39*4882a593Smuzhiyun (UNIPHIER_PIN_DRV_TYPE_BITS))
40*4882a593Smuzhiyun #define UNIPHIER_PIN_PUPDCTRL_BITS 9
41*4882a593Smuzhiyun #define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
42*4882a593Smuzhiyun - 1)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* direction of pull register */
45*4882a593Smuzhiyun #define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
46*4882a593Smuzhiyun (UNIPHIER_PIN_PUPDCTRL_BITS))
47*4882a593Smuzhiyun #define UNIPHIER_PIN_PULL_DIR_BITS 3
48*4882a593Smuzhiyun #define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
49*4882a593Smuzhiyun - 1)
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
52*4882a593Smuzhiyun #error "unable to pack pin attributes."
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
56*4882a593Smuzhiyun #define UNIPHIER_PIN_IECTRL_EXIST 0
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* drive control type */
59*4882a593Smuzhiyun enum uniphier_pin_drv_type {
60*4882a593Smuzhiyun UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
61*4882a593Smuzhiyun UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
62*4882a593Smuzhiyun UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
63*4882a593Smuzhiyun UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */
64*4882a593Smuzhiyun UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */
65*4882a593Smuzhiyun UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */
66*4882a593Smuzhiyun UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* direction of pull register (no pin supports bi-directional pull biasing) */
70*4882a593Smuzhiyun enum uniphier_pin_pull_dir {
71*4882a593Smuzhiyun UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */
72*4882a593Smuzhiyun UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */
73*4882a593Smuzhiyun UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */
74*4882a593Smuzhiyun UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */
75*4882a593Smuzhiyun UNIPHIER_PIN_PULL_NONE, /* no pull register */
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define UNIPHIER_PIN_IECTRL(x) \
79*4882a593Smuzhiyun (((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
80*4882a593Smuzhiyun #define UNIPHIER_PIN_DRVCTRL(x) \
81*4882a593Smuzhiyun (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
82*4882a593Smuzhiyun #define UNIPHIER_PIN_DRV_TYPE(x) \
83*4882a593Smuzhiyun (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
84*4882a593Smuzhiyun #define UNIPHIER_PIN_PUPDCTRL(x) \
85*4882a593Smuzhiyun (((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
86*4882a593Smuzhiyun #define UNIPHIER_PIN_PULL_DIR(x) \
87*4882a593Smuzhiyun (((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
90*4882a593Smuzhiyun (UNIPHIER_PIN_IECTRL(iectrl) | \
91*4882a593Smuzhiyun UNIPHIER_PIN_DRVCTRL(drvctrl) | \
92*4882a593Smuzhiyun UNIPHIER_PIN_DRV_TYPE(drv_type) | \
93*4882a593Smuzhiyun UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \
94*4882a593Smuzhiyun UNIPHIER_PIN_PULL_DIR(pull_dir))
95*4882a593Smuzhiyun
uniphier_pin_get_iectrl(void * drv_data)96*4882a593Smuzhiyun static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
99*4882a593Smuzhiyun UNIPHIER_PIN_IECTRL_MASK;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
uniphier_pin_get_drvctrl(void * drv_data)102*4882a593Smuzhiyun static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
105*4882a593Smuzhiyun UNIPHIER_PIN_DRVCTRL_MASK;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
uniphier_pin_get_drv_type(void * drv_data)108*4882a593Smuzhiyun static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
111*4882a593Smuzhiyun UNIPHIER_PIN_DRV_TYPE_MASK;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
uniphier_pin_get_pupdctrl(void * drv_data)114*4882a593Smuzhiyun static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
117*4882a593Smuzhiyun UNIPHIER_PIN_PUPDCTRL_MASK;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
uniphier_pin_get_pull_dir(void * drv_data)120*4882a593Smuzhiyun static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
123*4882a593Smuzhiyun UNIPHIER_PIN_PULL_DIR_MASK;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun struct uniphier_pinctrl_group {
127*4882a593Smuzhiyun const char *name;
128*4882a593Smuzhiyun const unsigned *pins;
129*4882a593Smuzhiyun unsigned num_pins;
130*4882a593Smuzhiyun const int *muxvals;
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun struct uniphier_pinmux_function {
134*4882a593Smuzhiyun const char *name;
135*4882a593Smuzhiyun const char * const *groups;
136*4882a593Smuzhiyun unsigned num_groups;
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun struct uniphier_pinctrl_socdata {
140*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins;
141*4882a593Smuzhiyun unsigned int npins;
142*4882a593Smuzhiyun const struct uniphier_pinctrl_group *groups;
143*4882a593Smuzhiyun int groups_count;
144*4882a593Smuzhiyun const struct uniphier_pinmux_function *functions;
145*4882a593Smuzhiyun int functions_count;
146*4882a593Smuzhiyun int (*get_gpio_muxval)(unsigned int pin, unsigned int gpio_offset);
147*4882a593Smuzhiyun unsigned int caps;
148*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
149*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
153*4882a593Smuzhiyun { \
154*4882a593Smuzhiyun .number = a, \
155*4882a593Smuzhiyun .name = b, \
156*4882a593Smuzhiyun .drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun #define __UNIPHIER_PINCTRL_GROUP(grp, mux) \
160*4882a593Smuzhiyun { \
161*4882a593Smuzhiyun .name = #grp, \
162*4882a593Smuzhiyun .pins = grp##_pins, \
163*4882a593Smuzhiyun .num_pins = ARRAY_SIZE(grp##_pins), \
164*4882a593Smuzhiyun .muxvals = mux, \
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_GROUP(grp) \
168*4882a593Smuzhiyun __UNIPHIER_PINCTRL_GROUP(grp, \
169*4882a593Smuzhiyun grp##_muxvals + \
170*4882a593Smuzhiyun BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
171*4882a593Smuzhiyun ARRAY_SIZE(grp##_muxvals)))
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun #define UNIPHIER_PINCTRL_GROUP_GPIO(grp) \
174*4882a593Smuzhiyun __UNIPHIER_PINCTRL_GROUP(grp, NULL)
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #define UNIPHIER_PINMUX_FUNCTION(func) \
177*4882a593Smuzhiyun { \
178*4882a593Smuzhiyun .name = #func, \
179*4882a593Smuzhiyun .groups = func##_groups, \
180*4882a593Smuzhiyun .num_groups = ARRAY_SIZE(func##_groups), \
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun int uniphier_pinctrl_probe(struct platform_device *pdev,
184*4882a593Smuzhiyun const struct uniphier_pinctrl_socdata *socdata);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun extern const struct dev_pm_ops uniphier_pinctrl_pm_ops;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun #endif /* __PINCTRL_UNIPHIER_H__ */
189