1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Allwinner A80 SoCs special pins pinctrl driver.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2014 Maxime Ripard
5*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
8*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
9*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
17*4882a593Smuzhiyun #include <linux/reset.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "pinctrl-sunxi.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
22*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
23*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
24*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
25*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_uart"), /* TX */
26*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
27*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
28*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
29*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
30*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_uart"), /* RX */
31*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
32*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
33*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
34*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
35*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_jtag"), /* TMS */
36*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
37*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
38*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
39*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
40*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_jtag"), /* TCK */
41*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
42*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
43*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
44*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
45*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_jtag"), /* TDO */
46*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
47*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
48*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
49*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
50*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_jtag"), /* TDI */
51*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
52*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
53*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
54*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
55*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_cir_rx"),
56*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
57*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
58*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
59*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
60*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "1wire"),
61*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
62*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
63*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
64*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
65*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_ps2"), /* SCK1 */
66*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
67*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
68*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
69*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
70*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_ps2"), /* SDA1 */
71*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Hole */
74*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
75*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
76*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
77*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
78*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
79*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
80*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
81*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
82*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
83*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
84*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
85*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PM_EINT2 */
86*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
87*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
88*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
89*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
90*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
91*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
92*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
93*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_i2s1"), /* LRCKR */
94*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* Hole */
97*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
98*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
99*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
100*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_i2c1"), /* SCK */
101*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PM_EINT8 */
102*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
103*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
104*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
105*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_i2c1"), /* SDA */
106*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PM_EINT9 */
107*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
108*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
109*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
110*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2s0"), /* MCLK */
111*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_i2s1")), /* MCLK */
112*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
113*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
114*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
115*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2s0"), /* BCLK */
116*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_i2s1")), /* BCLK */
117*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
118*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
119*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
120*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2s0"), /* LRCK */
121*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_i2s1")), /* LRCK */
122*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
123*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
124*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
125*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2s0"), /* DIN */
126*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_i2s1")), /* DIN */
127*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
128*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
129*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
130*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2s0"), /* DOUT */
131*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_i2s1")), /* DOUT */
132*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
133*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
134*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
135*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PM_EINT15 */
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* Hole */
138*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
139*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
140*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
141*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
142*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_rsb")), /* SCK */
143*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
144*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
145*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
146*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
147*4882a593Smuzhiyun SUNXI_FUNCTION(0x3, "s_rsb")), /* SDA */
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
151*4882a593Smuzhiyun .pins = sun9i_a80_r_pins,
152*4882a593Smuzhiyun .npins = ARRAY_SIZE(sun9i_a80_r_pins),
153*4882a593Smuzhiyun .pin_base = PL_BASE,
154*4882a593Smuzhiyun .irq_banks = 2,
155*4882a593Smuzhiyun .disable_strict_mode = true,
156*4882a593Smuzhiyun .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
sun9i_a80_r_pinctrl_probe(struct platform_device * pdev)159*4882a593Smuzhiyun static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun return sunxi_pinctrl_init(pdev,
162*4882a593Smuzhiyun &sun9i_a80_r_pinctrl_data);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
166*4882a593Smuzhiyun { .compatible = "allwinner,sun9i-a80-r-pinctrl", },
167*4882a593Smuzhiyun {}
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static struct platform_driver sun9i_a80_r_pinctrl_driver = {
171*4882a593Smuzhiyun .probe = sun9i_a80_r_pinctrl_probe,
172*4882a593Smuzhiyun .driver = {
173*4882a593Smuzhiyun .name = "sun9i-a80-r-pinctrl",
174*4882a593Smuzhiyun .owner = THIS_MODULE,
175*4882a593Smuzhiyun .of_match_table = sun9i_a80_r_pinctrl_match,
176*4882a593Smuzhiyun },
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun builtin_platform_driver(sun9i_a80_r_pinctrl_driver);
179