1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Allwinner H3 SoCs pinctrl driver.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "pinctrl-sunxi.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static const struct sunxi_desc_pin sun8i_h3_r_pins[] = {
20*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
21*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
22*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
23*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
24*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
25*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
26*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
27*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
28*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
29*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
30*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
31*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
32*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
33*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
34*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
35*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
36*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
37*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
38*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
39*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
40*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
41*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
42*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
43*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
44*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
45*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
46*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
47*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
48*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
49*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
50*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
51*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
52*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
53*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
54*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
55*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
56*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
57*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
58*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
59*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
60*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
61*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
62*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
63*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
64*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
65*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
66*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
67*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
68*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
69*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
70*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
71*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_pwm"),
72*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
73*4882a593Smuzhiyun SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
74*4882a593Smuzhiyun SUNXI_FUNCTION(0x0, "gpio_in"),
75*4882a593Smuzhiyun SUNXI_FUNCTION(0x1, "gpio_out"),
76*4882a593Smuzhiyun SUNXI_FUNCTION(0x2, "s_cir_rx"),
77*4882a593Smuzhiyun SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
81*4882a593Smuzhiyun .pins = sun8i_h3_r_pins,
82*4882a593Smuzhiyun .npins = ARRAY_SIZE(sun8i_h3_r_pins),
83*4882a593Smuzhiyun .irq_banks = 1,
84*4882a593Smuzhiyun .pin_base = PL_BASE,
85*4882a593Smuzhiyun .irq_read_needs_mux = true,
86*4882a593Smuzhiyun .disable_strict_mode = true,
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
sun8i_h3_r_pinctrl_probe(struct platform_device * pdev)89*4882a593Smuzhiyun static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun return sunxi_pinctrl_init(pdev,
92*4882a593Smuzhiyun &sun8i_h3_r_pinctrl_data);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static const struct of_device_id sun8i_h3_r_pinctrl_match[] = {
96*4882a593Smuzhiyun { .compatible = "allwinner,sun8i-h3-r-pinctrl", },
97*4882a593Smuzhiyun {}
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static struct platform_driver sun8i_h3_r_pinctrl_driver = {
101*4882a593Smuzhiyun .probe = sun8i_h3_r_pinctrl_probe,
102*4882a593Smuzhiyun .driver = {
103*4882a593Smuzhiyun .name = "sun8i-h3-r-pinctrl",
104*4882a593Smuzhiyun .of_match_table = sun8i_h3_r_pinctrl_match,
105*4882a593Smuzhiyun },
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun builtin_platform_driver(sun8i_h3_r_pinctrl_driver);
108