1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyunif ARCH_SUNXI 3*4882a593Smuzhiyun 4*4882a593Smuzhiyunconfig PINCTRL_SUNXI 5*4882a593Smuzhiyun bool 6*4882a593Smuzhiyun select PINMUX 7*4882a593Smuzhiyun select GENERIC_PINCONF 8*4882a593Smuzhiyun select GPIOLIB 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunconfig PINCTRL_SUNIV_F1C100S 11*4882a593Smuzhiyun def_bool MACH_SUNIV 12*4882a593Smuzhiyun select PINCTRL_SUNXI 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunconfig PINCTRL_SUN4I_A10 15*4882a593Smuzhiyun bool "Support for the Allwinner A10, A20 and R40 PIO" 16*4882a593Smuzhiyun default MACH_SUN4I || MACH_SUN7I || MACH_SUN8I 17*4882a593Smuzhiyun select PINCTRL_SUNXI 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunconfig PINCTRL_SUN5I 20*4882a593Smuzhiyun bool "Support for the Allwinner A10s, A13, R8 and NextThing GR8 PIO" 21*4882a593Smuzhiyun default MACH_SUN5I 22*4882a593Smuzhiyun select PINCTRL_SUNXI 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunconfig PINCTRL_SUN6I_A31 25*4882a593Smuzhiyun bool "Support for the Allwinner A31 PIO" 26*4882a593Smuzhiyun default MACH_SUN6I 27*4882a593Smuzhiyun select PINCTRL_SUNXI 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunconfig PINCTRL_SUN6I_A31_R 30*4882a593Smuzhiyun bool "Support for the Allwinner A31 R-PIO" 31*4882a593Smuzhiyun default MACH_SUN6I 32*4882a593Smuzhiyun depends on RESET_CONTROLLER 33*4882a593Smuzhiyun select PINCTRL_SUNXI 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig PINCTRL_SUN8I_A23 36*4882a593Smuzhiyun bool "Support for the Allwinner A23 PIO" 37*4882a593Smuzhiyun default MACH_SUN8I 38*4882a593Smuzhiyun select PINCTRL_SUNXI 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunconfig PINCTRL_SUN8I_A33 41*4882a593Smuzhiyun bool "Support for the Allwinner A33 PIO" 42*4882a593Smuzhiyun default MACH_SUN8I 43*4882a593Smuzhiyun select PINCTRL_SUNXI 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunconfig PINCTRL_SUN8I_A83T 46*4882a593Smuzhiyun bool "Support for the Allwinner A83T PIO" 47*4882a593Smuzhiyun default MACH_SUN8I 48*4882a593Smuzhiyun select PINCTRL_SUNXI 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunconfig PINCTRL_SUN8I_A83T_R 51*4882a593Smuzhiyun bool "Support for the Allwinner A83T R-PIO" 52*4882a593Smuzhiyun default MACH_SUN8I 53*4882a593Smuzhiyun select PINCTRL_SUNXI 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunconfig PINCTRL_SUN8I_A23_R 56*4882a593Smuzhiyun bool "Support for the Allwinner A23 and A33 R-PIO" 57*4882a593Smuzhiyun default MACH_SUN8I 58*4882a593Smuzhiyun depends on RESET_CONTROLLER 59*4882a593Smuzhiyun select PINCTRL_SUNXI 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunconfig PINCTRL_SUN8I_H3 62*4882a593Smuzhiyun bool "Support for the Allwinner H3 PIO" 63*4882a593Smuzhiyun default MACH_SUN8I 64*4882a593Smuzhiyun select PINCTRL_SUNXI 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunconfig PINCTRL_SUN8I_H3_R 67*4882a593Smuzhiyun bool "Support for the Allwinner H3 and H5 R-PIO" 68*4882a593Smuzhiyun default MACH_SUN8I || (ARM64 && ARCH_SUNXI) 69*4882a593Smuzhiyun select PINCTRL_SUNXI 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunconfig PINCTRL_SUN8I_V3S 72*4882a593Smuzhiyun bool "Support for the Allwinner V3s PIO" 73*4882a593Smuzhiyun default MACH_SUN8I 74*4882a593Smuzhiyun select PINCTRL_SUNXI 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunconfig PINCTRL_SUN9I_A80 77*4882a593Smuzhiyun bool "Support for the Allwinner A80 PIO" 78*4882a593Smuzhiyun default MACH_SUN9I 79*4882a593Smuzhiyun select PINCTRL_SUNXI 80*4882a593Smuzhiyun 81*4882a593Smuzhiyunconfig PINCTRL_SUN9I_A80_R 82*4882a593Smuzhiyun bool "Support for the Allwinner A80 R-PIO" 83*4882a593Smuzhiyun default MACH_SUN9I 84*4882a593Smuzhiyun depends on RESET_CONTROLLER 85*4882a593Smuzhiyun select PINCTRL_SUNXI 86*4882a593Smuzhiyun 87*4882a593Smuzhiyunconfig PINCTRL_SUN50I_A64 88*4882a593Smuzhiyun bool "Support for the Allwinner A64 PIO" 89*4882a593Smuzhiyun default ARM64 && ARCH_SUNXI 90*4882a593Smuzhiyun select PINCTRL_SUNXI 91*4882a593Smuzhiyun 92*4882a593Smuzhiyunconfig PINCTRL_SUN50I_A64_R 93*4882a593Smuzhiyun bool "Support for the Allwinner A64 R-PIO" 94*4882a593Smuzhiyun default ARM64 && ARCH_SUNXI 95*4882a593Smuzhiyun select PINCTRL_SUNXI 96*4882a593Smuzhiyun 97*4882a593Smuzhiyunconfig PINCTRL_SUN50I_A100 98*4882a593Smuzhiyun bool "Support for the Allwinner A100 PIO" 99*4882a593Smuzhiyun default ARM64 && ARCH_SUNXI 100*4882a593Smuzhiyun select PINCTRL_SUNXI 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunconfig PINCTRL_SUN50I_A100_R 103*4882a593Smuzhiyun bool "Support for the Allwinner A100 R-PIO" 104*4882a593Smuzhiyun default ARM64 && ARCH_SUNXI 105*4882a593Smuzhiyun select PINCTRL_SUNXI 106*4882a593Smuzhiyun 107*4882a593Smuzhiyunconfig PINCTRL_SUN50I_H5 108*4882a593Smuzhiyun bool "Support for the Allwinner H5 PIO" 109*4882a593Smuzhiyun default ARM64 && ARCH_SUNXI 110*4882a593Smuzhiyun select PINCTRL_SUNXI 111*4882a593Smuzhiyun 112*4882a593Smuzhiyunconfig PINCTRL_SUN50I_H6 113*4882a593Smuzhiyun bool "Support for the Allwinner H6 PIO" 114*4882a593Smuzhiyun default ARM64 && ARCH_SUNXI 115*4882a593Smuzhiyun select PINCTRL_SUNXI 116*4882a593Smuzhiyun 117*4882a593Smuzhiyunconfig PINCTRL_SUN50I_H6_R 118*4882a593Smuzhiyun bool "Support for the Allwinner H6 R-PIO" 119*4882a593Smuzhiyun default ARM64 && ARCH_SUNXI 120*4882a593Smuzhiyun select PINCTRL_SUNXI 121*4882a593Smuzhiyun 122*4882a593Smuzhiyunendif 123