xref: /OK3568_Linux_fs/kernel/drivers/pinctrl/sprd/pinctrl-sprd.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Spreadtrum pin controller driver
4*4882a593Smuzhiyun  * Copyright (C) 2017 Spreadtrum  - http://www.spreadtrum.com
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/debugfs.h>
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/pinctrl/machine.h>
17*4882a593Smuzhiyun #include <linux/pinctrl/pinconf.h>
18*4882a593Smuzhiyun #include <linux/pinctrl/pinconf-generic.h>
19*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
20*4882a593Smuzhiyun #include <linux/pinctrl/pinmux.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "../core.h"
24*4882a593Smuzhiyun #include "../pinmux.h"
25*4882a593Smuzhiyun #include "../pinconf.h"
26*4882a593Smuzhiyun #include "../pinctrl-utils.h"
27*4882a593Smuzhiyun #include "pinctrl-sprd.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define PINCTRL_BIT_MASK(width)		(~(~0UL << (width)))
30*4882a593Smuzhiyun #define PINCTRL_REG_OFFSET		0x20
31*4882a593Smuzhiyun #define PINCTRL_REG_MISC_OFFSET		0x4020
32*4882a593Smuzhiyun #define PINCTRL_REG_LEN			0x4
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define PIN_FUNC_MASK			(BIT(4) | BIT(5))
35*4882a593Smuzhiyun #define PIN_FUNC_SEL_1			~PIN_FUNC_MASK
36*4882a593Smuzhiyun #define PIN_FUNC_SEL_2			BIT(4)
37*4882a593Smuzhiyun #define PIN_FUNC_SEL_3			BIT(5)
38*4882a593Smuzhiyun #define PIN_FUNC_SEL_4			PIN_FUNC_MASK
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define AP_SLEEP_MODE			BIT(13)
41*4882a593Smuzhiyun #define PUBCP_SLEEP_MODE		BIT(14)
42*4882a593Smuzhiyun #define TGLDSP_SLEEP_MODE		BIT(15)
43*4882a593Smuzhiyun #define AGDSP_SLEEP_MODE		BIT(16)
44*4882a593Smuzhiyun #define CM4_SLEEP_MODE			BIT(17)
45*4882a593Smuzhiyun #define SLEEP_MODE_MASK			GENMASK(5, 0)
46*4882a593Smuzhiyun #define SLEEP_MODE_SHIFT		13
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define SLEEP_INPUT			BIT(1)
49*4882a593Smuzhiyun #define SLEEP_INPUT_MASK		0x1
50*4882a593Smuzhiyun #define SLEEP_INPUT_SHIFT		1
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define SLEEP_OUTPUT			BIT(0)
53*4882a593Smuzhiyun #define SLEEP_OUTPUT_MASK		0x1
54*4882a593Smuzhiyun #define SLEEP_OUTPUT_SHIFT		0
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define DRIVE_STRENGTH_MASK		GENMASK(3, 0)
57*4882a593Smuzhiyun #define DRIVE_STRENGTH_SHIFT		19
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define SLEEP_PULL_DOWN			BIT(2)
60*4882a593Smuzhiyun #define SLEEP_PULL_DOWN_MASK		0x1
61*4882a593Smuzhiyun #define SLEEP_PULL_DOWN_SHIFT		2
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define PULL_DOWN			BIT(6)
64*4882a593Smuzhiyun #define PULL_DOWN_MASK			0x1
65*4882a593Smuzhiyun #define PULL_DOWN_SHIFT			6
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define SLEEP_PULL_UP			BIT(3)
68*4882a593Smuzhiyun #define SLEEP_PULL_UP_MASK		0x1
69*4882a593Smuzhiyun #define SLEEP_PULL_UP_SHIFT		3
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define PULL_UP_4_7K			(BIT(12) | BIT(7))
72*4882a593Smuzhiyun #define PULL_UP_20K			BIT(7)
73*4882a593Smuzhiyun #define PULL_UP_MASK			0x21
74*4882a593Smuzhiyun #define PULL_UP_SHIFT			7
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define INPUT_SCHMITT			BIT(11)
77*4882a593Smuzhiyun #define INPUT_SCHMITT_MASK		0x1
78*4882a593Smuzhiyun #define INPUT_SCHMITT_SHIFT		11
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun enum pin_sleep_mode {
81*4882a593Smuzhiyun 	AP_SLEEP = BIT(0),
82*4882a593Smuzhiyun 	PUBCP_SLEEP = BIT(1),
83*4882a593Smuzhiyun 	TGLDSP_SLEEP = BIT(2),
84*4882a593Smuzhiyun 	AGDSP_SLEEP = BIT(3),
85*4882a593Smuzhiyun 	CM4_SLEEP = BIT(4),
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun enum pin_func_sel {
89*4882a593Smuzhiyun 	PIN_FUNC_1,
90*4882a593Smuzhiyun 	PIN_FUNC_2,
91*4882a593Smuzhiyun 	PIN_FUNC_3,
92*4882a593Smuzhiyun 	PIN_FUNC_4,
93*4882a593Smuzhiyun 	PIN_FUNC_MAX,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /**
97*4882a593Smuzhiyun  * struct sprd_pin: represent one pin's description
98*4882a593Smuzhiyun  * @name: pin name
99*4882a593Smuzhiyun  * @number: pin number
100*4882a593Smuzhiyun  * @type: pin type, can be GLOBAL_CTRL_PIN/COMMON_PIN/MISC_PIN
101*4882a593Smuzhiyun  * @reg: pin register address
102*4882a593Smuzhiyun  * @bit_offset: bit offset in pin register
103*4882a593Smuzhiyun  * @bit_width: bit width in pin register
104*4882a593Smuzhiyun  */
105*4882a593Smuzhiyun struct sprd_pin {
106*4882a593Smuzhiyun 	const char *name;
107*4882a593Smuzhiyun 	unsigned int number;
108*4882a593Smuzhiyun 	enum pin_type type;
109*4882a593Smuzhiyun 	unsigned long reg;
110*4882a593Smuzhiyun 	unsigned long bit_offset;
111*4882a593Smuzhiyun 	unsigned long bit_width;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /**
115*4882a593Smuzhiyun  * struct sprd_pin_group: represent one group's description
116*4882a593Smuzhiyun  * @name: group name
117*4882a593Smuzhiyun  * @npins: pin numbers of this group
118*4882a593Smuzhiyun  * @pins: pointer to pins array
119*4882a593Smuzhiyun  */
120*4882a593Smuzhiyun struct sprd_pin_group {
121*4882a593Smuzhiyun 	const char *name;
122*4882a593Smuzhiyun 	unsigned int npins;
123*4882a593Smuzhiyun 	unsigned int *pins;
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /**
127*4882a593Smuzhiyun  * struct sprd_pinctrl_soc_info: represent the SoC's pins description
128*4882a593Smuzhiyun  * @groups: pointer to groups of pins
129*4882a593Smuzhiyun  * @ngroups: group numbers of the whole SoC
130*4882a593Smuzhiyun  * @pins: pointer to pins description
131*4882a593Smuzhiyun  * @npins: pin numbers of the whole SoC
132*4882a593Smuzhiyun  * @grp_names: pointer to group names array
133*4882a593Smuzhiyun  */
134*4882a593Smuzhiyun struct sprd_pinctrl_soc_info {
135*4882a593Smuzhiyun 	struct sprd_pin_group *groups;
136*4882a593Smuzhiyun 	unsigned int ngroups;
137*4882a593Smuzhiyun 	struct sprd_pin *pins;
138*4882a593Smuzhiyun 	unsigned int npins;
139*4882a593Smuzhiyun 	const char **grp_names;
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /**
143*4882a593Smuzhiyun  * struct sprd_pinctrl: represent the pin controller device
144*4882a593Smuzhiyun  * @dev: pointer to the device structure
145*4882a593Smuzhiyun  * @pctl: pointer to the pinctrl handle
146*4882a593Smuzhiyun  * @base: base address of the controller
147*4882a593Smuzhiyun  * @info: pointer to SoC's pins description information
148*4882a593Smuzhiyun  */
149*4882a593Smuzhiyun struct sprd_pinctrl {
150*4882a593Smuzhiyun 	struct device *dev;
151*4882a593Smuzhiyun 	struct pinctrl_dev *pctl;
152*4882a593Smuzhiyun 	void __iomem *base;
153*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info;
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun #define SPRD_PIN_CONFIG_CONTROL		(PIN_CONFIG_END + 1)
157*4882a593Smuzhiyun #define SPRD_PIN_CONFIG_SLEEP_MODE	(PIN_CONFIG_END + 2)
158*4882a593Smuzhiyun 
sprd_pinctrl_get_id_by_name(struct sprd_pinctrl * sprd_pctl,const char * name)159*4882a593Smuzhiyun static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl,
160*4882a593Smuzhiyun 				       const char *name)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
163*4882a593Smuzhiyun 	int i;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	for (i = 0; i < info->npins; i++) {
166*4882a593Smuzhiyun 		if (!strcmp(info->pins[i].name, name))
167*4882a593Smuzhiyun 			return info->pins[i].number;
168*4882a593Smuzhiyun 	}
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	return -ENODEV;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static struct sprd_pin *
sprd_pinctrl_get_pin_by_id(struct sprd_pinctrl * sprd_pctl,unsigned int id)174*4882a593Smuzhiyun sprd_pinctrl_get_pin_by_id(struct sprd_pinctrl *sprd_pctl, unsigned int id)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
177*4882a593Smuzhiyun 	struct sprd_pin *pin = NULL;
178*4882a593Smuzhiyun 	int i;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	for (i = 0; i < info->npins; i++) {
181*4882a593Smuzhiyun 		if (info->pins[i].number == id) {
182*4882a593Smuzhiyun 			pin = &info->pins[i];
183*4882a593Smuzhiyun 			break;
184*4882a593Smuzhiyun 		}
185*4882a593Smuzhiyun 	}
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	return pin;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static const struct sprd_pin_group *
sprd_pinctrl_find_group_by_name(struct sprd_pinctrl * sprd_pctl,const char * name)191*4882a593Smuzhiyun sprd_pinctrl_find_group_by_name(struct sprd_pinctrl *sprd_pctl,
192*4882a593Smuzhiyun 				const char *name)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
195*4882a593Smuzhiyun 	const struct sprd_pin_group *grp = NULL;
196*4882a593Smuzhiyun 	int i;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	for (i = 0; i < info->ngroups; i++) {
199*4882a593Smuzhiyun 		if (!strcmp(info->groups[i].name, name)) {
200*4882a593Smuzhiyun 			grp = &info->groups[i];
201*4882a593Smuzhiyun 			break;
202*4882a593Smuzhiyun 		}
203*4882a593Smuzhiyun 	}
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	return grp;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
sprd_pctrl_group_count(struct pinctrl_dev * pctldev)208*4882a593Smuzhiyun static int sprd_pctrl_group_count(struct pinctrl_dev *pctldev)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
211*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = pctl->info;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	return info->ngroups;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
sprd_pctrl_group_name(struct pinctrl_dev * pctldev,unsigned int selector)216*4882a593Smuzhiyun static const char *sprd_pctrl_group_name(struct pinctrl_dev *pctldev,
217*4882a593Smuzhiyun 					 unsigned int selector)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
220*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = pctl->info;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	return info->groups[selector].name;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
sprd_pctrl_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * npins)225*4882a593Smuzhiyun static int sprd_pctrl_group_pins(struct pinctrl_dev *pctldev,
226*4882a593Smuzhiyun 				 unsigned int selector,
227*4882a593Smuzhiyun 				 const unsigned int **pins,
228*4882a593Smuzhiyun 				 unsigned int *npins)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
231*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = pctl->info;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	if (selector >= info->ngroups)
234*4882a593Smuzhiyun 		return -EINVAL;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	*pins = info->groups[selector].pins;
237*4882a593Smuzhiyun 	*npins = info->groups[selector].npins;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	return 0;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun 
sprd_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)242*4882a593Smuzhiyun static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev,
243*4882a593Smuzhiyun 			       struct device_node *np,
244*4882a593Smuzhiyun 			       struct pinctrl_map **map,
245*4882a593Smuzhiyun 			       unsigned int *num_maps)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
248*4882a593Smuzhiyun 	const struct sprd_pin_group *grp;
249*4882a593Smuzhiyun 	unsigned long *configs = NULL;
250*4882a593Smuzhiyun 	unsigned int num_configs = 0;
251*4882a593Smuzhiyun 	unsigned int reserved_maps = 0;
252*4882a593Smuzhiyun 	unsigned int reserve = 0;
253*4882a593Smuzhiyun 	const char *function;
254*4882a593Smuzhiyun 	enum pinctrl_map_type type;
255*4882a593Smuzhiyun 	int ret;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	grp = sprd_pinctrl_find_group_by_name(pctl, np->name);
258*4882a593Smuzhiyun 	if (!grp) {
259*4882a593Smuzhiyun 		dev_err(pctl->dev, "unable to find group for node %s\n",
260*4882a593Smuzhiyun 			of_node_full_name(np));
261*4882a593Smuzhiyun 		return -EINVAL;
262*4882a593Smuzhiyun 	}
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	ret = of_property_count_strings(np, "pins");
265*4882a593Smuzhiyun 	if (ret < 0)
266*4882a593Smuzhiyun 		return ret;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	if (ret == 1)
269*4882a593Smuzhiyun 		type = PIN_MAP_TYPE_CONFIGS_PIN;
270*4882a593Smuzhiyun 	else
271*4882a593Smuzhiyun 		type = PIN_MAP_TYPE_CONFIGS_GROUP;
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	ret = of_property_read_string(np, "function", &function);
274*4882a593Smuzhiyun 	if (ret < 0) {
275*4882a593Smuzhiyun 		if (ret != -EINVAL)
276*4882a593Smuzhiyun 			dev_err(pctl->dev,
277*4882a593Smuzhiyun 				"%s: could not parse property function\n",
278*4882a593Smuzhiyun 				of_node_full_name(np));
279*4882a593Smuzhiyun 		function = NULL;
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
283*4882a593Smuzhiyun 					      &num_configs);
284*4882a593Smuzhiyun 	if (ret < 0) {
285*4882a593Smuzhiyun 		dev_err(pctl->dev, "%s: could not parse node property\n",
286*4882a593Smuzhiyun 			of_node_full_name(np));
287*4882a593Smuzhiyun 		return ret;
288*4882a593Smuzhiyun 	}
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	*map = NULL;
291*4882a593Smuzhiyun 	*num_maps = 0;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	if (function != NULL)
294*4882a593Smuzhiyun 		reserve++;
295*4882a593Smuzhiyun 	if (num_configs)
296*4882a593Smuzhiyun 		reserve++;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
299*4882a593Smuzhiyun 					num_maps, reserve);
300*4882a593Smuzhiyun 	if (ret < 0)
301*4882a593Smuzhiyun 		goto out;
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	if (function) {
304*4882a593Smuzhiyun 		ret = pinctrl_utils_add_map_mux(pctldev, map,
305*4882a593Smuzhiyun 						&reserved_maps, num_maps,
306*4882a593Smuzhiyun 						grp->name, function);
307*4882a593Smuzhiyun 		if (ret < 0)
308*4882a593Smuzhiyun 			goto out;
309*4882a593Smuzhiyun 	}
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	if (num_configs) {
312*4882a593Smuzhiyun 		const char *group_or_pin;
313*4882a593Smuzhiyun 		unsigned int pin_id;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 		if (type == PIN_MAP_TYPE_CONFIGS_PIN) {
316*4882a593Smuzhiyun 			pin_id = grp->pins[0];
317*4882a593Smuzhiyun 			group_or_pin = pin_get_name(pctldev, pin_id);
318*4882a593Smuzhiyun 		} else {
319*4882a593Smuzhiyun 			group_or_pin = grp->name;
320*4882a593Smuzhiyun 		}
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 		ret = pinctrl_utils_add_map_configs(pctldev, map,
323*4882a593Smuzhiyun 						    &reserved_maps, num_maps,
324*4882a593Smuzhiyun 						    group_or_pin, configs,
325*4882a593Smuzhiyun 						    num_configs, type);
326*4882a593Smuzhiyun 	}
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun out:
329*4882a593Smuzhiyun 	kfree(configs);
330*4882a593Smuzhiyun 	return ret;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun 
sprd_pctrl_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int offset)333*4882a593Smuzhiyun static void sprd_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
334*4882a593Smuzhiyun 				unsigned int offset)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun 	seq_printf(s, "%s", dev_name(pctldev->dev));
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun static const struct pinctrl_ops sprd_pctrl_ops = {
340*4882a593Smuzhiyun 	.get_groups_count = sprd_pctrl_group_count,
341*4882a593Smuzhiyun 	.get_group_name = sprd_pctrl_group_name,
342*4882a593Smuzhiyun 	.get_group_pins = sprd_pctrl_group_pins,
343*4882a593Smuzhiyun 	.pin_dbg_show = sprd_pctrl_dbg_show,
344*4882a593Smuzhiyun 	.dt_node_to_map = sprd_dt_node_to_map,
345*4882a593Smuzhiyun 	.dt_free_map = pinctrl_utils_free_map,
346*4882a593Smuzhiyun };
347*4882a593Smuzhiyun 
sprd_pmx_get_function_count(struct pinctrl_dev * pctldev)348*4882a593Smuzhiyun static int sprd_pmx_get_function_count(struct pinctrl_dev *pctldev)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun 	return PIN_FUNC_MAX;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun 
sprd_pmx_get_function_name(struct pinctrl_dev * pctldev,unsigned int selector)353*4882a593Smuzhiyun static const char *sprd_pmx_get_function_name(struct pinctrl_dev *pctldev,
354*4882a593Smuzhiyun 					      unsigned int selector)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun 	switch (selector) {
357*4882a593Smuzhiyun 	case PIN_FUNC_1:
358*4882a593Smuzhiyun 		return "func1";
359*4882a593Smuzhiyun 	case PIN_FUNC_2:
360*4882a593Smuzhiyun 		return "func2";
361*4882a593Smuzhiyun 	case PIN_FUNC_3:
362*4882a593Smuzhiyun 		return "func3";
363*4882a593Smuzhiyun 	case PIN_FUNC_4:
364*4882a593Smuzhiyun 		return "func4";
365*4882a593Smuzhiyun 	default:
366*4882a593Smuzhiyun 		return "null";
367*4882a593Smuzhiyun 	}
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
sprd_pmx_get_function_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)370*4882a593Smuzhiyun static int sprd_pmx_get_function_groups(struct pinctrl_dev *pctldev,
371*4882a593Smuzhiyun 					unsigned int selector,
372*4882a593Smuzhiyun 					const char * const **groups,
373*4882a593Smuzhiyun 					unsigned int * const num_groups)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
376*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = pctl->info;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	*groups = info->grp_names;
379*4882a593Smuzhiyun 	*num_groups = info->ngroups;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	return 0;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
sprd_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)384*4882a593Smuzhiyun static int sprd_pmx_set_mux(struct pinctrl_dev *pctldev,
385*4882a593Smuzhiyun 			    unsigned int func_selector,
386*4882a593Smuzhiyun 			    unsigned int group_selector)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
389*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = pctl->info;
390*4882a593Smuzhiyun 	struct sprd_pin_group *grp = &info->groups[group_selector];
391*4882a593Smuzhiyun 	unsigned int i, grp_pins = grp->npins;
392*4882a593Smuzhiyun 	unsigned long reg;
393*4882a593Smuzhiyun 	unsigned int val = 0;
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	if (group_selector >= info->ngroups)
396*4882a593Smuzhiyun 		return -EINVAL;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	switch (func_selector) {
399*4882a593Smuzhiyun 	case PIN_FUNC_1:
400*4882a593Smuzhiyun 		val &= PIN_FUNC_SEL_1;
401*4882a593Smuzhiyun 		break;
402*4882a593Smuzhiyun 	case PIN_FUNC_2:
403*4882a593Smuzhiyun 		val |= PIN_FUNC_SEL_2;
404*4882a593Smuzhiyun 		break;
405*4882a593Smuzhiyun 	case PIN_FUNC_3:
406*4882a593Smuzhiyun 		val |= PIN_FUNC_SEL_3;
407*4882a593Smuzhiyun 		break;
408*4882a593Smuzhiyun 	case PIN_FUNC_4:
409*4882a593Smuzhiyun 		val |= PIN_FUNC_SEL_4;
410*4882a593Smuzhiyun 		break;
411*4882a593Smuzhiyun 	default:
412*4882a593Smuzhiyun 		break;
413*4882a593Smuzhiyun 	}
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	for (i = 0; i < grp_pins; i++) {
416*4882a593Smuzhiyun 		unsigned int pin_id = grp->pins[i];
417*4882a593Smuzhiyun 		struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 		if (!pin || pin->type != COMMON_PIN)
420*4882a593Smuzhiyun 			continue;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 		reg = readl((void __iomem *)pin->reg);
423*4882a593Smuzhiyun 		reg &= ~PIN_FUNC_MASK;
424*4882a593Smuzhiyun 		reg |= val;
425*4882a593Smuzhiyun 		writel(reg, (void __iomem *)pin->reg);
426*4882a593Smuzhiyun 	}
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	return 0;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun static const struct pinmux_ops sprd_pmx_ops = {
432*4882a593Smuzhiyun 	.get_functions_count = sprd_pmx_get_function_count,
433*4882a593Smuzhiyun 	.get_function_name = sprd_pmx_get_function_name,
434*4882a593Smuzhiyun 	.get_function_groups = sprd_pmx_get_function_groups,
435*4882a593Smuzhiyun 	.set_mux = sprd_pmx_set_mux,
436*4882a593Smuzhiyun };
437*4882a593Smuzhiyun 
sprd_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin_id,unsigned long * config)438*4882a593Smuzhiyun static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
439*4882a593Smuzhiyun 			    unsigned long *config)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
442*4882a593Smuzhiyun 	struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
443*4882a593Smuzhiyun 	unsigned int param = pinconf_to_config_param(*config);
444*4882a593Smuzhiyun 	unsigned int reg, arg;
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	if (!pin)
447*4882a593Smuzhiyun 		return -EINVAL;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	if (pin->type == GLOBAL_CTRL_PIN) {
450*4882a593Smuzhiyun 		reg = (readl((void __iomem *)pin->reg) >>
451*4882a593Smuzhiyun 			   pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
452*4882a593Smuzhiyun 	} else {
453*4882a593Smuzhiyun 		reg = readl((void __iomem *)pin->reg);
454*4882a593Smuzhiyun 	}
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	if (pin->type == GLOBAL_CTRL_PIN &&
457*4882a593Smuzhiyun 	    param == SPRD_PIN_CONFIG_CONTROL) {
458*4882a593Smuzhiyun 		arg = reg;
459*4882a593Smuzhiyun 	} else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
460*4882a593Smuzhiyun 		switch (param) {
461*4882a593Smuzhiyun 		case SPRD_PIN_CONFIG_SLEEP_MODE:
462*4882a593Smuzhiyun 			arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK;
463*4882a593Smuzhiyun 			break;
464*4882a593Smuzhiyun 		case PIN_CONFIG_INPUT_ENABLE:
465*4882a593Smuzhiyun 			arg = (reg >> SLEEP_INPUT_SHIFT) & SLEEP_INPUT_MASK;
466*4882a593Smuzhiyun 			break;
467*4882a593Smuzhiyun 		case PIN_CONFIG_OUTPUT_ENABLE:
468*4882a593Smuzhiyun 			arg = reg & SLEEP_OUTPUT_MASK;
469*4882a593Smuzhiyun 			break;
470*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
471*4882a593Smuzhiyun 			if ((reg & SLEEP_OUTPUT) || (reg & SLEEP_INPUT))
472*4882a593Smuzhiyun 				return -EINVAL;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 			arg = 1;
475*4882a593Smuzhiyun 			break;
476*4882a593Smuzhiyun 		case PIN_CONFIG_DRIVE_STRENGTH:
477*4882a593Smuzhiyun 			arg = (reg >> DRIVE_STRENGTH_SHIFT) &
478*4882a593Smuzhiyun 				DRIVE_STRENGTH_MASK;
479*4882a593Smuzhiyun 			break;
480*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_PULL_DOWN:
481*4882a593Smuzhiyun 			/* combine sleep pull down and pull down config */
482*4882a593Smuzhiyun 			arg = ((reg >> SLEEP_PULL_DOWN_SHIFT) &
483*4882a593Smuzhiyun 			       SLEEP_PULL_DOWN_MASK) << 16;
484*4882a593Smuzhiyun 			arg |= (reg >> PULL_DOWN_SHIFT) & PULL_DOWN_MASK;
485*4882a593Smuzhiyun 			break;
486*4882a593Smuzhiyun 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
487*4882a593Smuzhiyun 			arg = (reg >> INPUT_SCHMITT_SHIFT) & INPUT_SCHMITT_MASK;
488*4882a593Smuzhiyun 			break;
489*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_PULL_UP:
490*4882a593Smuzhiyun 			/* combine sleep pull up and pull up config */
491*4882a593Smuzhiyun 			arg = ((reg >> SLEEP_PULL_UP_SHIFT) &
492*4882a593Smuzhiyun 			       SLEEP_PULL_UP_MASK) << 16;
493*4882a593Smuzhiyun 			arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK;
494*4882a593Smuzhiyun 			break;
495*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_DISABLE:
496*4882a593Smuzhiyun 			if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
497*4882a593Smuzhiyun 			    (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
498*4882a593Smuzhiyun 				return -EINVAL;
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 			arg = 1;
501*4882a593Smuzhiyun 			break;
502*4882a593Smuzhiyun 		case PIN_CONFIG_SLEEP_HARDWARE_STATE:
503*4882a593Smuzhiyun 			arg = 0;
504*4882a593Smuzhiyun 			break;
505*4882a593Smuzhiyun 		default:
506*4882a593Smuzhiyun 			return -ENOTSUPP;
507*4882a593Smuzhiyun 		}
508*4882a593Smuzhiyun 	} else {
509*4882a593Smuzhiyun 		return -ENOTSUPP;
510*4882a593Smuzhiyun 	}
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	*config = pinconf_to_config_packed(param, arg);
513*4882a593Smuzhiyun 	return 0;
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun 
sprd_pinconf_drive(unsigned int mA)516*4882a593Smuzhiyun static unsigned int sprd_pinconf_drive(unsigned int mA)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun 	unsigned int val = 0;
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	switch (mA) {
521*4882a593Smuzhiyun 	case 2:
522*4882a593Smuzhiyun 		break;
523*4882a593Smuzhiyun 	case 4:
524*4882a593Smuzhiyun 		val |= BIT(19);
525*4882a593Smuzhiyun 		break;
526*4882a593Smuzhiyun 	case 6:
527*4882a593Smuzhiyun 		val |= BIT(20);
528*4882a593Smuzhiyun 		break;
529*4882a593Smuzhiyun 	case 8:
530*4882a593Smuzhiyun 		val |= BIT(19) | BIT(20);
531*4882a593Smuzhiyun 		break;
532*4882a593Smuzhiyun 	case 10:
533*4882a593Smuzhiyun 		val |= BIT(21);
534*4882a593Smuzhiyun 		break;
535*4882a593Smuzhiyun 	case 12:
536*4882a593Smuzhiyun 		val |= BIT(21) | BIT(19);
537*4882a593Smuzhiyun 		break;
538*4882a593Smuzhiyun 	case 14:
539*4882a593Smuzhiyun 		val |= BIT(21) | BIT(20);
540*4882a593Smuzhiyun 		break;
541*4882a593Smuzhiyun 	case 16:
542*4882a593Smuzhiyun 		val |= BIT(19) | BIT(20) | BIT(21);
543*4882a593Smuzhiyun 		break;
544*4882a593Smuzhiyun 	case 20:
545*4882a593Smuzhiyun 		val |= BIT(22);
546*4882a593Smuzhiyun 		break;
547*4882a593Smuzhiyun 	case 21:
548*4882a593Smuzhiyun 		val |= BIT(22) | BIT(19);
549*4882a593Smuzhiyun 		break;
550*4882a593Smuzhiyun 	case 24:
551*4882a593Smuzhiyun 		val |= BIT(22) | BIT(20);
552*4882a593Smuzhiyun 		break;
553*4882a593Smuzhiyun 	case 25:
554*4882a593Smuzhiyun 		val |= BIT(22) | BIT(20) | BIT(19);
555*4882a593Smuzhiyun 		break;
556*4882a593Smuzhiyun 	case 27:
557*4882a593Smuzhiyun 		val |= BIT(22) | BIT(21);
558*4882a593Smuzhiyun 		break;
559*4882a593Smuzhiyun 	case 29:
560*4882a593Smuzhiyun 		val |= BIT(22) | BIT(21) | BIT(19);
561*4882a593Smuzhiyun 		break;
562*4882a593Smuzhiyun 	case 31:
563*4882a593Smuzhiyun 		val |= BIT(22) | BIT(21) | BIT(20);
564*4882a593Smuzhiyun 		break;
565*4882a593Smuzhiyun 	case 33:
566*4882a593Smuzhiyun 		val |= BIT(22) | BIT(21) | BIT(20) | BIT(19);
567*4882a593Smuzhiyun 		break;
568*4882a593Smuzhiyun 	default:
569*4882a593Smuzhiyun 		break;
570*4882a593Smuzhiyun 	}
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	return val;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun 
sprd_pinctrl_check_sleep_config(unsigned long * configs,unsigned int num_configs)575*4882a593Smuzhiyun static bool sprd_pinctrl_check_sleep_config(unsigned long *configs,
576*4882a593Smuzhiyun 					    unsigned int num_configs)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun 	unsigned int param;
579*4882a593Smuzhiyun 	int i;
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	for (i = 0; i < num_configs; i++) {
582*4882a593Smuzhiyun 		param = pinconf_to_config_param(configs[i]);
583*4882a593Smuzhiyun 		if (param == PIN_CONFIG_SLEEP_HARDWARE_STATE)
584*4882a593Smuzhiyun 			return true;
585*4882a593Smuzhiyun 	}
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	return false;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun 
sprd_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin_id,unsigned long * configs,unsigned int num_configs)590*4882a593Smuzhiyun static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
591*4882a593Smuzhiyun 			    unsigned long *configs, unsigned int num_configs)
592*4882a593Smuzhiyun {
593*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
594*4882a593Smuzhiyun 	struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
595*4882a593Smuzhiyun 	bool is_sleep_config;
596*4882a593Smuzhiyun 	unsigned long reg;
597*4882a593Smuzhiyun 	int i;
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	if (!pin)
600*4882a593Smuzhiyun 		return -EINVAL;
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	is_sleep_config = sprd_pinctrl_check_sleep_config(configs, num_configs);
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	for (i = 0; i < num_configs; i++) {
605*4882a593Smuzhiyun 		unsigned int param, arg, shift, mask, val;
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 		param = pinconf_to_config_param(configs[i]);
608*4882a593Smuzhiyun 		arg = pinconf_to_config_argument(configs[i]);
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 		val = 0;
611*4882a593Smuzhiyun 		shift = 0;
612*4882a593Smuzhiyun 		mask = 0;
613*4882a593Smuzhiyun 		if (pin->type == GLOBAL_CTRL_PIN &&
614*4882a593Smuzhiyun 		    param == SPRD_PIN_CONFIG_CONTROL) {
615*4882a593Smuzhiyun 			val = arg;
616*4882a593Smuzhiyun 		} else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
617*4882a593Smuzhiyun 			switch (param) {
618*4882a593Smuzhiyun 			case SPRD_PIN_CONFIG_SLEEP_MODE:
619*4882a593Smuzhiyun 				if (arg & AP_SLEEP)
620*4882a593Smuzhiyun 					val |= AP_SLEEP_MODE;
621*4882a593Smuzhiyun 				if (arg & PUBCP_SLEEP)
622*4882a593Smuzhiyun 					val |= PUBCP_SLEEP_MODE;
623*4882a593Smuzhiyun 				if (arg & TGLDSP_SLEEP)
624*4882a593Smuzhiyun 					val |= TGLDSP_SLEEP_MODE;
625*4882a593Smuzhiyun 				if (arg & AGDSP_SLEEP)
626*4882a593Smuzhiyun 					val |= AGDSP_SLEEP_MODE;
627*4882a593Smuzhiyun 				if (arg & CM4_SLEEP)
628*4882a593Smuzhiyun 					val |= CM4_SLEEP_MODE;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 				mask = SLEEP_MODE_MASK;
631*4882a593Smuzhiyun 				shift = SLEEP_MODE_SHIFT;
632*4882a593Smuzhiyun 				break;
633*4882a593Smuzhiyun 			case PIN_CONFIG_INPUT_ENABLE:
634*4882a593Smuzhiyun 				if (is_sleep_config == true) {
635*4882a593Smuzhiyun 					if (arg > 0)
636*4882a593Smuzhiyun 						val |= SLEEP_INPUT;
637*4882a593Smuzhiyun 					else
638*4882a593Smuzhiyun 						val &= ~SLEEP_INPUT;
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 					mask = SLEEP_INPUT_MASK;
641*4882a593Smuzhiyun 					shift = SLEEP_INPUT_SHIFT;
642*4882a593Smuzhiyun 				}
643*4882a593Smuzhiyun 				break;
644*4882a593Smuzhiyun 			case PIN_CONFIG_OUTPUT_ENABLE:
645*4882a593Smuzhiyun 				if (is_sleep_config == true) {
646*4882a593Smuzhiyun 					if (arg > 0)
647*4882a593Smuzhiyun 						val |= SLEEP_OUTPUT;
648*4882a593Smuzhiyun 					else
649*4882a593Smuzhiyun 						val &= ~SLEEP_OUTPUT;
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 					mask = SLEEP_OUTPUT_MASK;
652*4882a593Smuzhiyun 					shift = SLEEP_OUTPUT_SHIFT;
653*4882a593Smuzhiyun 				}
654*4882a593Smuzhiyun 				break;
655*4882a593Smuzhiyun 			case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
656*4882a593Smuzhiyun 				if (is_sleep_config == true) {
657*4882a593Smuzhiyun 					val = shift = 0;
658*4882a593Smuzhiyun 					mask = SLEEP_OUTPUT | SLEEP_INPUT;
659*4882a593Smuzhiyun 				}
660*4882a593Smuzhiyun 				break;
661*4882a593Smuzhiyun 			case PIN_CONFIG_DRIVE_STRENGTH:
662*4882a593Smuzhiyun 				if (arg < 2 || arg > 60)
663*4882a593Smuzhiyun 					return -EINVAL;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 				val = sprd_pinconf_drive(arg);
666*4882a593Smuzhiyun 				mask = DRIVE_STRENGTH_MASK;
667*4882a593Smuzhiyun 				shift = DRIVE_STRENGTH_SHIFT;
668*4882a593Smuzhiyun 				break;
669*4882a593Smuzhiyun 			case PIN_CONFIG_BIAS_PULL_DOWN:
670*4882a593Smuzhiyun 				if (is_sleep_config == true) {
671*4882a593Smuzhiyun 					val |= SLEEP_PULL_DOWN;
672*4882a593Smuzhiyun 					mask = SLEEP_PULL_DOWN_MASK;
673*4882a593Smuzhiyun 					shift = SLEEP_PULL_DOWN_SHIFT;
674*4882a593Smuzhiyun 				} else {
675*4882a593Smuzhiyun 					val |= PULL_DOWN;
676*4882a593Smuzhiyun 					mask = PULL_DOWN_MASK;
677*4882a593Smuzhiyun 					shift = PULL_DOWN_SHIFT;
678*4882a593Smuzhiyun 				}
679*4882a593Smuzhiyun 				break;
680*4882a593Smuzhiyun 			case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
681*4882a593Smuzhiyun 				if (arg > 0)
682*4882a593Smuzhiyun 					val |= INPUT_SCHMITT;
683*4882a593Smuzhiyun 				else
684*4882a593Smuzhiyun 					val &= ~INPUT_SCHMITT;
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 				mask = INPUT_SCHMITT_MASK;
687*4882a593Smuzhiyun 				shift = INPUT_SCHMITT_SHIFT;
688*4882a593Smuzhiyun 				break;
689*4882a593Smuzhiyun 			case PIN_CONFIG_BIAS_PULL_UP:
690*4882a593Smuzhiyun 				if (is_sleep_config == true) {
691*4882a593Smuzhiyun 					val |= SLEEP_PULL_UP;
692*4882a593Smuzhiyun 					mask = SLEEP_PULL_UP_MASK;
693*4882a593Smuzhiyun 					shift = SLEEP_PULL_UP_SHIFT;
694*4882a593Smuzhiyun 				} else {
695*4882a593Smuzhiyun 					if (arg == 20000)
696*4882a593Smuzhiyun 						val |= PULL_UP_20K;
697*4882a593Smuzhiyun 					else if (arg == 4700)
698*4882a593Smuzhiyun 						val |= PULL_UP_4_7K;
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 					mask = PULL_UP_MASK;
701*4882a593Smuzhiyun 					shift = PULL_UP_SHIFT;
702*4882a593Smuzhiyun 				}
703*4882a593Smuzhiyun 				break;
704*4882a593Smuzhiyun 			case PIN_CONFIG_BIAS_DISABLE:
705*4882a593Smuzhiyun 				if (is_sleep_config == true) {
706*4882a593Smuzhiyun 					val = shift = 0;
707*4882a593Smuzhiyun 					mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP;
708*4882a593Smuzhiyun 				} else {
709*4882a593Smuzhiyun 					val = shift = 0;
710*4882a593Smuzhiyun 					mask = PULL_DOWN | PULL_UP_20K |
711*4882a593Smuzhiyun 						PULL_UP_4_7K;
712*4882a593Smuzhiyun 				}
713*4882a593Smuzhiyun 				break;
714*4882a593Smuzhiyun 			case PIN_CONFIG_SLEEP_HARDWARE_STATE:
715*4882a593Smuzhiyun 				continue;
716*4882a593Smuzhiyun 			default:
717*4882a593Smuzhiyun 				return -ENOTSUPP;
718*4882a593Smuzhiyun 			}
719*4882a593Smuzhiyun 		} else {
720*4882a593Smuzhiyun 			return -ENOTSUPP;
721*4882a593Smuzhiyun 		}
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 		if (pin->type == GLOBAL_CTRL_PIN) {
724*4882a593Smuzhiyun 			reg = readl((void __iomem *)pin->reg);
725*4882a593Smuzhiyun 			reg &= ~(PINCTRL_BIT_MASK(pin->bit_width)
726*4882a593Smuzhiyun 				<< pin->bit_offset);
727*4882a593Smuzhiyun 			reg |= (val & PINCTRL_BIT_MASK(pin->bit_width))
728*4882a593Smuzhiyun 				<< pin->bit_offset;
729*4882a593Smuzhiyun 			writel(reg, (void __iomem *)pin->reg);
730*4882a593Smuzhiyun 		} else {
731*4882a593Smuzhiyun 			reg = readl((void __iomem *)pin->reg);
732*4882a593Smuzhiyun 			reg &= ~(mask << shift);
733*4882a593Smuzhiyun 			reg |= val;
734*4882a593Smuzhiyun 			writel(reg, (void __iomem *)pin->reg);
735*4882a593Smuzhiyun 		}
736*4882a593Smuzhiyun 	}
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun 	return 0;
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun 
sprd_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int selector,unsigned long * config)741*4882a593Smuzhiyun static int sprd_pinconf_group_get(struct pinctrl_dev *pctldev,
742*4882a593Smuzhiyun 				  unsigned int selector, unsigned long *config)
743*4882a593Smuzhiyun {
744*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
745*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = pctl->info;
746*4882a593Smuzhiyun 	struct sprd_pin_group *grp;
747*4882a593Smuzhiyun 	unsigned int pin_id;
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	if (selector >= info->ngroups)
750*4882a593Smuzhiyun 		return -EINVAL;
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun 	grp = &info->groups[selector];
753*4882a593Smuzhiyun 	pin_id = grp->pins[0];
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	return sprd_pinconf_get(pctldev, pin_id, config);
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun 
sprd_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int selector,unsigned long * configs,unsigned int num_configs)758*4882a593Smuzhiyun static int sprd_pinconf_group_set(struct pinctrl_dev *pctldev,
759*4882a593Smuzhiyun 				  unsigned int selector,
760*4882a593Smuzhiyun 				  unsigned long *configs,
761*4882a593Smuzhiyun 				  unsigned int num_configs)
762*4882a593Smuzhiyun {
763*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
764*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = pctl->info;
765*4882a593Smuzhiyun 	struct sprd_pin_group *grp;
766*4882a593Smuzhiyun 	int ret, i;
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 	if (selector >= info->ngroups)
769*4882a593Smuzhiyun 		return -EINVAL;
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun 	grp = &info->groups[selector];
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	for (i = 0; i < grp->npins; i++) {
774*4882a593Smuzhiyun 		unsigned int pin_id = grp->pins[i];
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun 		ret = sprd_pinconf_set(pctldev, pin_id, configs, num_configs);
777*4882a593Smuzhiyun 		if (ret)
778*4882a593Smuzhiyun 			return ret;
779*4882a593Smuzhiyun 	}
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun 	return 0;
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun 
sprd_pinconf_get_config(struct pinctrl_dev * pctldev,unsigned int pin_id,unsigned long * config)784*4882a593Smuzhiyun static int sprd_pinconf_get_config(struct pinctrl_dev *pctldev,
785*4882a593Smuzhiyun 				   unsigned int pin_id,
786*4882a593Smuzhiyun 				   unsigned long *config)
787*4882a593Smuzhiyun {
788*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
789*4882a593Smuzhiyun 	struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun 	if (!pin)
792*4882a593Smuzhiyun 		return -EINVAL;
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun 	if (pin->type == GLOBAL_CTRL_PIN) {
795*4882a593Smuzhiyun 		*config = (readl((void __iomem *)pin->reg) >>
796*4882a593Smuzhiyun 			   pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
797*4882a593Smuzhiyun 	} else {
798*4882a593Smuzhiyun 		*config = readl((void __iomem *)pin->reg);
799*4882a593Smuzhiyun 	}
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	return 0;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun 
sprd_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin_id)804*4882a593Smuzhiyun static void sprd_pinconf_dbg_show(struct pinctrl_dev *pctldev,
805*4882a593Smuzhiyun 				  struct seq_file *s, unsigned int pin_id)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun 	unsigned long config;
808*4882a593Smuzhiyun 	int ret;
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
811*4882a593Smuzhiyun 	if (ret)
812*4882a593Smuzhiyun 		return;
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	seq_printf(s, "0x%lx", config);
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun 
sprd_pinconf_group_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int selector)817*4882a593Smuzhiyun static void sprd_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
818*4882a593Smuzhiyun 					struct seq_file *s,
819*4882a593Smuzhiyun 					unsigned int selector)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun 	struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
822*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = pctl->info;
823*4882a593Smuzhiyun 	struct sprd_pin_group *grp;
824*4882a593Smuzhiyun 	unsigned long config;
825*4882a593Smuzhiyun 	const char *name;
826*4882a593Smuzhiyun 	int i, ret;
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 	if (selector >= info->ngroups)
829*4882a593Smuzhiyun 		return;
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun 	grp = &info->groups[selector];
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun 	seq_putc(s, '\n');
834*4882a593Smuzhiyun 	for (i = 0; i < grp->npins; i++, config++) {
835*4882a593Smuzhiyun 		unsigned int pin_id = grp->pins[i];
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 		name = pin_get_name(pctldev, pin_id);
838*4882a593Smuzhiyun 		ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
839*4882a593Smuzhiyun 		if (ret)
840*4882a593Smuzhiyun 			return;
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 		seq_printf(s, "%s: 0x%lx ", name, config);
843*4882a593Smuzhiyun 	}
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun static const struct pinconf_ops sprd_pinconf_ops = {
847*4882a593Smuzhiyun 	.is_generic = true,
848*4882a593Smuzhiyun 	.pin_config_get = sprd_pinconf_get,
849*4882a593Smuzhiyun 	.pin_config_set = sprd_pinconf_set,
850*4882a593Smuzhiyun 	.pin_config_group_get = sprd_pinconf_group_get,
851*4882a593Smuzhiyun 	.pin_config_group_set = sprd_pinconf_group_set,
852*4882a593Smuzhiyun 	.pin_config_dbg_show = sprd_pinconf_dbg_show,
853*4882a593Smuzhiyun 	.pin_config_group_dbg_show = sprd_pinconf_group_dbg_show,
854*4882a593Smuzhiyun };
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun static const struct pinconf_generic_params sprd_dt_params[] = {
857*4882a593Smuzhiyun 	{"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0},
858*4882a593Smuzhiyun 	{"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0},
859*4882a593Smuzhiyun };
860*4882a593Smuzhiyun 
861*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
862*4882a593Smuzhiyun static const struct pin_config_item sprd_conf_items[] = {
863*4882a593Smuzhiyun 	PCONFDUMP(SPRD_PIN_CONFIG_CONTROL, "global control", NULL, true),
864*4882a593Smuzhiyun 	PCONFDUMP(SPRD_PIN_CONFIG_SLEEP_MODE, "sleep mode", NULL, true),
865*4882a593Smuzhiyun };
866*4882a593Smuzhiyun #endif
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun static struct pinctrl_desc sprd_pinctrl_desc = {
869*4882a593Smuzhiyun 	.pctlops = &sprd_pctrl_ops,
870*4882a593Smuzhiyun 	.pmxops = &sprd_pmx_ops,
871*4882a593Smuzhiyun 	.confops = &sprd_pinconf_ops,
872*4882a593Smuzhiyun 	.num_custom_params = ARRAY_SIZE(sprd_dt_params),
873*4882a593Smuzhiyun 	.custom_params = sprd_dt_params,
874*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
875*4882a593Smuzhiyun 	.custom_conf_items = sprd_conf_items,
876*4882a593Smuzhiyun #endif
877*4882a593Smuzhiyun 	.owner = THIS_MODULE,
878*4882a593Smuzhiyun };
879*4882a593Smuzhiyun 
sprd_pinctrl_parse_groups(struct device_node * np,struct sprd_pinctrl * sprd_pctl,struct sprd_pin_group * grp)880*4882a593Smuzhiyun static int sprd_pinctrl_parse_groups(struct device_node *np,
881*4882a593Smuzhiyun 				     struct sprd_pinctrl *sprd_pctl,
882*4882a593Smuzhiyun 				     struct sprd_pin_group *grp)
883*4882a593Smuzhiyun {
884*4882a593Smuzhiyun 	struct property *prop;
885*4882a593Smuzhiyun 	const char *pin_name;
886*4882a593Smuzhiyun 	int ret, i = 0;
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun 	ret = of_property_count_strings(np, "pins");
889*4882a593Smuzhiyun 	if (ret < 0)
890*4882a593Smuzhiyun 		return ret;
891*4882a593Smuzhiyun 
892*4882a593Smuzhiyun 	grp->name = np->name;
893*4882a593Smuzhiyun 	grp->npins = ret;
894*4882a593Smuzhiyun 	grp->pins = devm_kcalloc(sprd_pctl->dev,
895*4882a593Smuzhiyun 				 grp->npins, sizeof(unsigned int),
896*4882a593Smuzhiyun 				 GFP_KERNEL);
897*4882a593Smuzhiyun 	if (!grp->pins)
898*4882a593Smuzhiyun 		return -ENOMEM;
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 	of_property_for_each_string(np, "pins", prop, pin_name) {
901*4882a593Smuzhiyun 		ret = sprd_pinctrl_get_id_by_name(sprd_pctl, pin_name);
902*4882a593Smuzhiyun 		if (ret >= 0)
903*4882a593Smuzhiyun 			grp->pins[i++] = ret;
904*4882a593Smuzhiyun 	}
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun 	for (i = 0; i < grp->npins; i++) {
907*4882a593Smuzhiyun 		dev_dbg(sprd_pctl->dev,
908*4882a593Smuzhiyun 			"Group[%s] contains [%d] pins: id = %d\n",
909*4882a593Smuzhiyun 			grp->name, grp->npins, grp->pins[i]);
910*4882a593Smuzhiyun 	}
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	return 0;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun 
sprd_pinctrl_get_groups(struct device_node * np)915*4882a593Smuzhiyun static unsigned int sprd_pinctrl_get_groups(struct device_node *np)
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun 	struct device_node *child;
918*4882a593Smuzhiyun 	unsigned int group_cnt, cnt;
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 	group_cnt = of_get_child_count(np);
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 	for_each_child_of_node(np, child) {
923*4882a593Smuzhiyun 		cnt = of_get_child_count(child);
924*4882a593Smuzhiyun 		if (cnt > 0)
925*4882a593Smuzhiyun 			group_cnt += cnt;
926*4882a593Smuzhiyun 	}
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun 	return group_cnt;
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun 
sprd_pinctrl_parse_dt(struct sprd_pinctrl * sprd_pctl)931*4882a593Smuzhiyun static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
934*4882a593Smuzhiyun 	struct device_node *np = sprd_pctl->dev->of_node;
935*4882a593Smuzhiyun 	struct device_node *child, *sub_child;
936*4882a593Smuzhiyun 	struct sprd_pin_group *grp;
937*4882a593Smuzhiyun 	const char **temp;
938*4882a593Smuzhiyun 	int ret;
939*4882a593Smuzhiyun 
940*4882a593Smuzhiyun 	if (!np)
941*4882a593Smuzhiyun 		return -ENODEV;
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 	info->ngroups = sprd_pinctrl_get_groups(np);
944*4882a593Smuzhiyun 	if (!info->ngroups)
945*4882a593Smuzhiyun 		return 0;
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun 	info->groups = devm_kcalloc(sprd_pctl->dev,
948*4882a593Smuzhiyun 				    info->ngroups,
949*4882a593Smuzhiyun 				    sizeof(struct sprd_pin_group),
950*4882a593Smuzhiyun 				    GFP_KERNEL);
951*4882a593Smuzhiyun 	if (!info->groups)
952*4882a593Smuzhiyun 		return -ENOMEM;
953*4882a593Smuzhiyun 
954*4882a593Smuzhiyun 	info->grp_names = devm_kcalloc(sprd_pctl->dev,
955*4882a593Smuzhiyun 				       info->ngroups, sizeof(char *),
956*4882a593Smuzhiyun 				       GFP_KERNEL);
957*4882a593Smuzhiyun 	if (!info->grp_names)
958*4882a593Smuzhiyun 		return -ENOMEM;
959*4882a593Smuzhiyun 
960*4882a593Smuzhiyun 	temp = info->grp_names;
961*4882a593Smuzhiyun 	grp = info->groups;
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun 	for_each_child_of_node(np, child) {
964*4882a593Smuzhiyun 		ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
965*4882a593Smuzhiyun 		if (ret) {
966*4882a593Smuzhiyun 			of_node_put(child);
967*4882a593Smuzhiyun 			return ret;
968*4882a593Smuzhiyun 		}
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 		*temp++ = grp->name;
971*4882a593Smuzhiyun 		grp++;
972*4882a593Smuzhiyun 
973*4882a593Smuzhiyun 		if (of_get_child_count(child) > 0) {
974*4882a593Smuzhiyun 			for_each_child_of_node(child, sub_child) {
975*4882a593Smuzhiyun 				ret = sprd_pinctrl_parse_groups(sub_child,
976*4882a593Smuzhiyun 								sprd_pctl, grp);
977*4882a593Smuzhiyun 				if (ret) {
978*4882a593Smuzhiyun 					of_node_put(sub_child);
979*4882a593Smuzhiyun 					of_node_put(child);
980*4882a593Smuzhiyun 					return ret;
981*4882a593Smuzhiyun 				}
982*4882a593Smuzhiyun 
983*4882a593Smuzhiyun 				*temp++ = grp->name;
984*4882a593Smuzhiyun 				grp++;
985*4882a593Smuzhiyun 			}
986*4882a593Smuzhiyun 		}
987*4882a593Smuzhiyun 	}
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun 	return 0;
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun 
sprd_pinctrl_add_pins(struct sprd_pinctrl * sprd_pctl,struct sprd_pins_info * sprd_soc_pin_info,int pins_cnt)992*4882a593Smuzhiyun static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
993*4882a593Smuzhiyun 				 struct sprd_pins_info *sprd_soc_pin_info,
994*4882a593Smuzhiyun 				 int pins_cnt)
995*4882a593Smuzhiyun {
996*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
997*4882a593Smuzhiyun 	unsigned int ctrl_pin = 0, com_pin = 0;
998*4882a593Smuzhiyun 	struct sprd_pin *pin;
999*4882a593Smuzhiyun 	int i;
1000*4882a593Smuzhiyun 
1001*4882a593Smuzhiyun 	info->npins = pins_cnt;
1002*4882a593Smuzhiyun 	info->pins = devm_kcalloc(sprd_pctl->dev,
1003*4882a593Smuzhiyun 				  info->npins, sizeof(struct sprd_pin),
1004*4882a593Smuzhiyun 				  GFP_KERNEL);
1005*4882a593Smuzhiyun 	if (!info->pins)
1006*4882a593Smuzhiyun 		return -ENOMEM;
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun 	for (i = 0, pin = info->pins; i < info->npins; i++, pin++) {
1009*4882a593Smuzhiyun 		unsigned int reg;
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 		pin->name = sprd_soc_pin_info[i].name;
1012*4882a593Smuzhiyun 		pin->type = sprd_soc_pin_info[i].type;
1013*4882a593Smuzhiyun 		pin->number = sprd_soc_pin_info[i].num;
1014*4882a593Smuzhiyun 		reg = sprd_soc_pin_info[i].reg;
1015*4882a593Smuzhiyun 		if (pin->type == GLOBAL_CTRL_PIN) {
1016*4882a593Smuzhiyun 			pin->reg = (unsigned long)sprd_pctl->base +
1017*4882a593Smuzhiyun 				PINCTRL_REG_LEN * reg;
1018*4882a593Smuzhiyun 			pin->bit_offset = sprd_soc_pin_info[i].bit_offset;
1019*4882a593Smuzhiyun 			pin->bit_width = sprd_soc_pin_info[i].bit_width;
1020*4882a593Smuzhiyun 			ctrl_pin++;
1021*4882a593Smuzhiyun 		} else if (pin->type == COMMON_PIN) {
1022*4882a593Smuzhiyun 			pin->reg = (unsigned long)sprd_pctl->base +
1023*4882a593Smuzhiyun 				PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
1024*4882a593Smuzhiyun 				(i - ctrl_pin);
1025*4882a593Smuzhiyun 			com_pin++;
1026*4882a593Smuzhiyun 		} else if (pin->type == MISC_PIN) {
1027*4882a593Smuzhiyun 			pin->reg = (unsigned long)sprd_pctl->base +
1028*4882a593Smuzhiyun 				PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
1029*4882a593Smuzhiyun 				(i - ctrl_pin - com_pin);
1030*4882a593Smuzhiyun 		}
1031*4882a593Smuzhiyun 	}
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun 	for (i = 0, pin = info->pins; i < info->npins; pin++, i++) {
1034*4882a593Smuzhiyun 		dev_dbg(sprd_pctl->dev, "pin name[%s-%d], type = %d, "
1035*4882a593Smuzhiyun 			"bit offset = %ld, bit width = %ld, reg = 0x%lx\n",
1036*4882a593Smuzhiyun 			pin->name, pin->number, pin->type,
1037*4882a593Smuzhiyun 			pin->bit_offset, pin->bit_width, pin->reg);
1038*4882a593Smuzhiyun 	}
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun 	return 0;
1041*4882a593Smuzhiyun }
1042*4882a593Smuzhiyun 
sprd_pinctrl_core_probe(struct platform_device * pdev,struct sprd_pins_info * sprd_soc_pin_info,int pins_cnt)1043*4882a593Smuzhiyun int sprd_pinctrl_core_probe(struct platform_device *pdev,
1044*4882a593Smuzhiyun 			    struct sprd_pins_info *sprd_soc_pin_info,
1045*4882a593Smuzhiyun 			    int pins_cnt)
1046*4882a593Smuzhiyun {
1047*4882a593Smuzhiyun 	struct sprd_pinctrl *sprd_pctl;
1048*4882a593Smuzhiyun 	struct sprd_pinctrl_soc_info *pinctrl_info;
1049*4882a593Smuzhiyun 	struct pinctrl_pin_desc *pin_desc;
1050*4882a593Smuzhiyun 	int ret, i;
1051*4882a593Smuzhiyun 
1052*4882a593Smuzhiyun 	sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl),
1053*4882a593Smuzhiyun 				 GFP_KERNEL);
1054*4882a593Smuzhiyun 	if (!sprd_pctl)
1055*4882a593Smuzhiyun 		return -ENOMEM;
1056*4882a593Smuzhiyun 
1057*4882a593Smuzhiyun 	sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0);
1058*4882a593Smuzhiyun 	if (IS_ERR(sprd_pctl->base))
1059*4882a593Smuzhiyun 		return PTR_ERR(sprd_pctl->base);
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	pinctrl_info = devm_kzalloc(&pdev->dev,
1062*4882a593Smuzhiyun 				    sizeof(struct sprd_pinctrl_soc_info),
1063*4882a593Smuzhiyun 				    GFP_KERNEL);
1064*4882a593Smuzhiyun 	if (!pinctrl_info)
1065*4882a593Smuzhiyun 		return -ENOMEM;
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 	sprd_pctl->info = pinctrl_info;
1068*4882a593Smuzhiyun 	sprd_pctl->dev = &pdev->dev;
1069*4882a593Smuzhiyun 	platform_set_drvdata(pdev, sprd_pctl);
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 	ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt);
1072*4882a593Smuzhiyun 	if (ret) {
1073*4882a593Smuzhiyun 		dev_err(&pdev->dev, "fail to add pins information\n");
1074*4882a593Smuzhiyun 		return ret;
1075*4882a593Smuzhiyun 	}
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	ret = sprd_pinctrl_parse_dt(sprd_pctl);
1078*4882a593Smuzhiyun 	if (ret) {
1079*4882a593Smuzhiyun 		dev_err(&pdev->dev, "fail to parse dt properties\n");
1080*4882a593Smuzhiyun 		return ret;
1081*4882a593Smuzhiyun 	}
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	pin_desc = devm_kcalloc(&pdev->dev,
1084*4882a593Smuzhiyun 				pinctrl_info->npins,
1085*4882a593Smuzhiyun 				sizeof(struct pinctrl_pin_desc),
1086*4882a593Smuzhiyun 				GFP_KERNEL);
1087*4882a593Smuzhiyun 	if (!pin_desc)
1088*4882a593Smuzhiyun 		return -ENOMEM;
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun 	for (i = 0; i < pinctrl_info->npins; i++) {
1091*4882a593Smuzhiyun 		pin_desc[i].number = pinctrl_info->pins[i].number;
1092*4882a593Smuzhiyun 		pin_desc[i].name = pinctrl_info->pins[i].name;
1093*4882a593Smuzhiyun 		pin_desc[i].drv_data = pinctrl_info;
1094*4882a593Smuzhiyun 	}
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 	sprd_pinctrl_desc.pins = pin_desc;
1097*4882a593Smuzhiyun 	sprd_pinctrl_desc.name = dev_name(&pdev->dev);
1098*4882a593Smuzhiyun 	sprd_pinctrl_desc.npins = pinctrl_info->npins;
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 	sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc,
1101*4882a593Smuzhiyun 					   &pdev->dev, (void *)sprd_pctl);
1102*4882a593Smuzhiyun 	if (IS_ERR(sprd_pctl->pctl)) {
1103*4882a593Smuzhiyun 		dev_err(&pdev->dev, "could not register pinctrl driver\n");
1104*4882a593Smuzhiyun 		return PTR_ERR(sprd_pctl->pctl);
1105*4882a593Smuzhiyun 	}
1106*4882a593Smuzhiyun 
1107*4882a593Smuzhiyun 	return 0;
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(sprd_pinctrl_core_probe);
1110*4882a593Smuzhiyun 
sprd_pinctrl_remove(struct platform_device * pdev)1111*4882a593Smuzhiyun int sprd_pinctrl_remove(struct platform_device *pdev)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun 	struct sprd_pinctrl *sprd_pctl = platform_get_drvdata(pdev);
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	pinctrl_unregister(sprd_pctl->pctl);
1116*4882a593Smuzhiyun 	return 0;
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(sprd_pinctrl_remove);
1119*4882a593Smuzhiyun 
sprd_pinctrl_shutdown(struct platform_device * pdev)1120*4882a593Smuzhiyun void sprd_pinctrl_shutdown(struct platform_device *pdev)
1121*4882a593Smuzhiyun {
1122*4882a593Smuzhiyun 	struct pinctrl *pinctl;
1123*4882a593Smuzhiyun 	struct pinctrl_state *state;
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	pinctl = devm_pinctrl_get(&pdev->dev);
1126*4882a593Smuzhiyun 	if (IS_ERR(pinctl))
1127*4882a593Smuzhiyun 		return;
1128*4882a593Smuzhiyun 	state = pinctrl_lookup_state(pinctl, "shutdown");
1129*4882a593Smuzhiyun 	if (IS_ERR(state))
1130*4882a593Smuzhiyun 		return;
1131*4882a593Smuzhiyun 	pinctrl_select_state(pinctl, state);
1132*4882a593Smuzhiyun }
1133*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(sprd_pinctrl_shutdown);
1134*4882a593Smuzhiyun 
1135*4882a593Smuzhiyun MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver");
1136*4882a593Smuzhiyun MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
1137*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1138