xref: /OK3568_Linux_fs/kernel/drivers/pinctrl/spear/pinctrl-spear310.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Driver for the ST Microelectronics SPEAr310 pinmux
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2012 ST Microelectronics
5*4882a593Smuzhiyun  * Viresh Kumar <vireshk@kernel.org>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This file is licensed under the terms of the GNU General Public
8*4882a593Smuzhiyun  * License version 2. This program is licensed "as is" without any
9*4882a593Smuzhiyun  * warranty of any kind, whether express or implied.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include "pinctrl-spear3xx.h"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define DRIVER_NAME "spear310-pinmux"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* addresses */
21*4882a593Smuzhiyun #define PMX_CONFIG_REG			0x08
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /* emi_cs_0_to_5_pins */
24*4882a593Smuzhiyun static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
25*4882a593Smuzhiyun static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
26*4882a593Smuzhiyun 	{
27*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
28*4882a593Smuzhiyun 		.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
29*4882a593Smuzhiyun 		.val = 0,
30*4882a593Smuzhiyun 	},
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun static struct spear_modemux emi_cs_0_to_5_modemux[] = {
34*4882a593Smuzhiyun 	{
35*4882a593Smuzhiyun 		.muxregs = emi_cs_0_to_5_muxreg,
36*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
37*4882a593Smuzhiyun 	},
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static struct spear_pingroup emi_cs_0_to_5_pingroup = {
41*4882a593Smuzhiyun 	.name = "emi_cs_0_to_5_grp",
42*4882a593Smuzhiyun 	.pins = emi_cs_0_to_5_pins,
43*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
44*4882a593Smuzhiyun 	.modemuxs = emi_cs_0_to_5_modemux,
45*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
49*4882a593Smuzhiyun static struct spear_function emi_cs_0_to_5_function = {
50*4882a593Smuzhiyun 	.name = "emi",
51*4882a593Smuzhiyun 	.groups = emi_cs_0_to_5_grps,
52*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /* uart1_pins */
56*4882a593Smuzhiyun static const unsigned uart1_pins[] = { 0, 1 };
57*4882a593Smuzhiyun static struct spear_muxreg uart1_muxreg[] = {
58*4882a593Smuzhiyun 	{
59*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
60*4882a593Smuzhiyun 		.mask = PMX_FIRDA_MASK,
61*4882a593Smuzhiyun 		.val = 0,
62*4882a593Smuzhiyun 	},
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static struct spear_modemux uart1_modemux[] = {
66*4882a593Smuzhiyun 	{
67*4882a593Smuzhiyun 		.muxregs = uart1_muxreg,
68*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(uart1_muxreg),
69*4882a593Smuzhiyun 	},
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static struct spear_pingroup uart1_pingroup = {
73*4882a593Smuzhiyun 	.name = "uart1_grp",
74*4882a593Smuzhiyun 	.pins = uart1_pins,
75*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(uart1_pins),
76*4882a593Smuzhiyun 	.modemuxs = uart1_modemux,
77*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(uart1_modemux),
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun static const char *const uart1_grps[] = { "uart1_grp" };
81*4882a593Smuzhiyun static struct spear_function uart1_function = {
82*4882a593Smuzhiyun 	.name = "uart1",
83*4882a593Smuzhiyun 	.groups = uart1_grps,
84*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(uart1_grps),
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* uart2_pins */
88*4882a593Smuzhiyun static const unsigned uart2_pins[] = { 43, 44 };
89*4882a593Smuzhiyun static struct spear_muxreg uart2_muxreg[] = {
90*4882a593Smuzhiyun 	{
91*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
92*4882a593Smuzhiyun 		.mask = PMX_TIMER_0_1_MASK,
93*4882a593Smuzhiyun 		.val = 0,
94*4882a593Smuzhiyun 	},
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static struct spear_modemux uart2_modemux[] = {
98*4882a593Smuzhiyun 	{
99*4882a593Smuzhiyun 		.muxregs = uart2_muxreg,
100*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(uart2_muxreg),
101*4882a593Smuzhiyun 	},
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static struct spear_pingroup uart2_pingroup = {
105*4882a593Smuzhiyun 	.name = "uart2_grp",
106*4882a593Smuzhiyun 	.pins = uart2_pins,
107*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(uart2_pins),
108*4882a593Smuzhiyun 	.modemuxs = uart2_modemux,
109*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(uart2_modemux),
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun static const char *const uart2_grps[] = { "uart2_grp" };
113*4882a593Smuzhiyun static struct spear_function uart2_function = {
114*4882a593Smuzhiyun 	.name = "uart2",
115*4882a593Smuzhiyun 	.groups = uart2_grps,
116*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(uart2_grps),
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun /* uart3_pins */
120*4882a593Smuzhiyun static const unsigned uart3_pins[] = { 37, 38 };
121*4882a593Smuzhiyun static struct spear_muxreg uart3_muxreg[] = {
122*4882a593Smuzhiyun 	{
123*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
124*4882a593Smuzhiyun 		.mask = PMX_UART0_MODEM_MASK,
125*4882a593Smuzhiyun 		.val = 0,
126*4882a593Smuzhiyun 	},
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static struct spear_modemux uart3_modemux[] = {
130*4882a593Smuzhiyun 	{
131*4882a593Smuzhiyun 		.muxregs = uart3_muxreg,
132*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(uart3_muxreg),
133*4882a593Smuzhiyun 	},
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun static struct spear_pingroup uart3_pingroup = {
137*4882a593Smuzhiyun 	.name = "uart3_grp",
138*4882a593Smuzhiyun 	.pins = uart3_pins,
139*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(uart3_pins),
140*4882a593Smuzhiyun 	.modemuxs = uart3_modemux,
141*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(uart3_modemux),
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun static const char *const uart3_grps[] = { "uart3_grp" };
145*4882a593Smuzhiyun static struct spear_function uart3_function = {
146*4882a593Smuzhiyun 	.name = "uart3",
147*4882a593Smuzhiyun 	.groups = uart3_grps,
148*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(uart3_grps),
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun /* uart4_pins */
152*4882a593Smuzhiyun static const unsigned uart4_pins[] = { 39, 40 };
153*4882a593Smuzhiyun static struct spear_muxreg uart4_muxreg[] = {
154*4882a593Smuzhiyun 	{
155*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
156*4882a593Smuzhiyun 		.mask = PMX_UART0_MODEM_MASK,
157*4882a593Smuzhiyun 		.val = 0,
158*4882a593Smuzhiyun 	},
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun static struct spear_modemux uart4_modemux[] = {
162*4882a593Smuzhiyun 	{
163*4882a593Smuzhiyun 		.muxregs = uart4_muxreg,
164*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(uart4_muxreg),
165*4882a593Smuzhiyun 	},
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun static struct spear_pingroup uart4_pingroup = {
169*4882a593Smuzhiyun 	.name = "uart4_grp",
170*4882a593Smuzhiyun 	.pins = uart4_pins,
171*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(uart4_pins),
172*4882a593Smuzhiyun 	.modemuxs = uart4_modemux,
173*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(uart4_modemux),
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun static const char *const uart4_grps[] = { "uart4_grp" };
177*4882a593Smuzhiyun static struct spear_function uart4_function = {
178*4882a593Smuzhiyun 	.name = "uart4",
179*4882a593Smuzhiyun 	.groups = uart4_grps,
180*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(uart4_grps),
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /* uart5_pins */
184*4882a593Smuzhiyun static const unsigned uart5_pins[] = { 41, 42 };
185*4882a593Smuzhiyun static struct spear_muxreg uart5_muxreg[] = {
186*4882a593Smuzhiyun 	{
187*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
188*4882a593Smuzhiyun 		.mask = PMX_UART0_MODEM_MASK,
189*4882a593Smuzhiyun 		.val = 0,
190*4882a593Smuzhiyun 	},
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun static struct spear_modemux uart5_modemux[] = {
194*4882a593Smuzhiyun 	{
195*4882a593Smuzhiyun 		.muxregs = uart5_muxreg,
196*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(uart5_muxreg),
197*4882a593Smuzhiyun 	},
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun static struct spear_pingroup uart5_pingroup = {
201*4882a593Smuzhiyun 	.name = "uart5_grp",
202*4882a593Smuzhiyun 	.pins = uart5_pins,
203*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(uart5_pins),
204*4882a593Smuzhiyun 	.modemuxs = uart5_modemux,
205*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(uart5_modemux),
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static const char *const uart5_grps[] = { "uart5_grp" };
209*4882a593Smuzhiyun static struct spear_function uart5_function = {
210*4882a593Smuzhiyun 	.name = "uart5",
211*4882a593Smuzhiyun 	.groups = uart5_grps,
212*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(uart5_grps),
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun /* fsmc_pins */
216*4882a593Smuzhiyun static const unsigned fsmc_pins[] = { 34, 35, 36 };
217*4882a593Smuzhiyun static struct spear_muxreg fsmc_muxreg[] = {
218*4882a593Smuzhiyun 	{
219*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
220*4882a593Smuzhiyun 		.mask = PMX_SSP_CS_MASK,
221*4882a593Smuzhiyun 		.val = 0,
222*4882a593Smuzhiyun 	},
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun static struct spear_modemux fsmc_modemux[] = {
226*4882a593Smuzhiyun 	{
227*4882a593Smuzhiyun 		.muxregs = fsmc_muxreg,
228*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(fsmc_muxreg),
229*4882a593Smuzhiyun 	},
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun static struct spear_pingroup fsmc_pingroup = {
233*4882a593Smuzhiyun 	.name = "fsmc_grp",
234*4882a593Smuzhiyun 	.pins = fsmc_pins,
235*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(fsmc_pins),
236*4882a593Smuzhiyun 	.modemuxs = fsmc_modemux,
237*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(fsmc_modemux),
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun static const char *const fsmc_grps[] = { "fsmc_grp" };
241*4882a593Smuzhiyun static struct spear_function fsmc_function = {
242*4882a593Smuzhiyun 	.name = "fsmc",
243*4882a593Smuzhiyun 	.groups = fsmc_grps,
244*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(fsmc_grps),
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun /* rs485_0_pins */
248*4882a593Smuzhiyun static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
249*4882a593Smuzhiyun static struct spear_muxreg rs485_0_muxreg[] = {
250*4882a593Smuzhiyun 	{
251*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
252*4882a593Smuzhiyun 		.mask = PMX_MII_MASK,
253*4882a593Smuzhiyun 		.val = 0,
254*4882a593Smuzhiyun 	},
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun static struct spear_modemux rs485_0_modemux[] = {
258*4882a593Smuzhiyun 	{
259*4882a593Smuzhiyun 		.muxregs = rs485_0_muxreg,
260*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
261*4882a593Smuzhiyun 	},
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun static struct spear_pingroup rs485_0_pingroup = {
265*4882a593Smuzhiyun 	.name = "rs485_0_grp",
266*4882a593Smuzhiyun 	.pins = rs485_0_pins,
267*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(rs485_0_pins),
268*4882a593Smuzhiyun 	.modemuxs = rs485_0_modemux,
269*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun static const char *const rs485_0_grps[] = { "rs485_0" };
273*4882a593Smuzhiyun static struct spear_function rs485_0_function = {
274*4882a593Smuzhiyun 	.name = "rs485_0",
275*4882a593Smuzhiyun 	.groups = rs485_0_grps,
276*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(rs485_0_grps),
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun /* rs485_1_pins */
280*4882a593Smuzhiyun static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
281*4882a593Smuzhiyun static struct spear_muxreg rs485_1_muxreg[] = {
282*4882a593Smuzhiyun 	{
283*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
284*4882a593Smuzhiyun 		.mask = PMX_MII_MASK,
285*4882a593Smuzhiyun 		.val = 0,
286*4882a593Smuzhiyun 	},
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun static struct spear_modemux rs485_1_modemux[] = {
290*4882a593Smuzhiyun 	{
291*4882a593Smuzhiyun 		.muxregs = rs485_1_muxreg,
292*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
293*4882a593Smuzhiyun 	},
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun static struct spear_pingroup rs485_1_pingroup = {
297*4882a593Smuzhiyun 	.name = "rs485_1_grp",
298*4882a593Smuzhiyun 	.pins = rs485_1_pins,
299*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(rs485_1_pins),
300*4882a593Smuzhiyun 	.modemuxs = rs485_1_modemux,
301*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
302*4882a593Smuzhiyun };
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun static const char *const rs485_1_grps[] = { "rs485_1" };
305*4882a593Smuzhiyun static struct spear_function rs485_1_function = {
306*4882a593Smuzhiyun 	.name = "rs485_1",
307*4882a593Smuzhiyun 	.groups = rs485_1_grps,
308*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(rs485_1_grps),
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun /* tdm_pins */
312*4882a593Smuzhiyun static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
313*4882a593Smuzhiyun static struct spear_muxreg tdm_muxreg[] = {
314*4882a593Smuzhiyun 	{
315*4882a593Smuzhiyun 		.reg = PMX_CONFIG_REG,
316*4882a593Smuzhiyun 		.mask = PMX_MII_MASK,
317*4882a593Smuzhiyun 		.val = 0,
318*4882a593Smuzhiyun 	},
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun static struct spear_modemux tdm_modemux[] = {
322*4882a593Smuzhiyun 	{
323*4882a593Smuzhiyun 		.muxregs = tdm_muxreg,
324*4882a593Smuzhiyun 		.nmuxregs = ARRAY_SIZE(tdm_muxreg),
325*4882a593Smuzhiyun 	},
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun static struct spear_pingroup tdm_pingroup = {
329*4882a593Smuzhiyun 	.name = "tdm_grp",
330*4882a593Smuzhiyun 	.pins = tdm_pins,
331*4882a593Smuzhiyun 	.npins = ARRAY_SIZE(tdm_pins),
332*4882a593Smuzhiyun 	.modemuxs = tdm_modemux,
333*4882a593Smuzhiyun 	.nmodemuxs = ARRAY_SIZE(tdm_modemux),
334*4882a593Smuzhiyun };
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun static const char *const tdm_grps[] = { "tdm_grp" };
337*4882a593Smuzhiyun static struct spear_function tdm_function = {
338*4882a593Smuzhiyun 	.name = "tdm",
339*4882a593Smuzhiyun 	.groups = tdm_grps,
340*4882a593Smuzhiyun 	.ngroups = ARRAY_SIZE(tdm_grps),
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun /* pingroups */
344*4882a593Smuzhiyun static struct spear_pingroup *spear310_pingroups[] = {
345*4882a593Smuzhiyun 	SPEAR3XX_COMMON_PINGROUPS,
346*4882a593Smuzhiyun 	&emi_cs_0_to_5_pingroup,
347*4882a593Smuzhiyun 	&uart1_pingroup,
348*4882a593Smuzhiyun 	&uart2_pingroup,
349*4882a593Smuzhiyun 	&uart3_pingroup,
350*4882a593Smuzhiyun 	&uart4_pingroup,
351*4882a593Smuzhiyun 	&uart5_pingroup,
352*4882a593Smuzhiyun 	&fsmc_pingroup,
353*4882a593Smuzhiyun 	&rs485_0_pingroup,
354*4882a593Smuzhiyun 	&rs485_1_pingroup,
355*4882a593Smuzhiyun 	&tdm_pingroup,
356*4882a593Smuzhiyun };
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun /* functions */
359*4882a593Smuzhiyun static struct spear_function *spear310_functions[] = {
360*4882a593Smuzhiyun 	SPEAR3XX_COMMON_FUNCTIONS,
361*4882a593Smuzhiyun 	&emi_cs_0_to_5_function,
362*4882a593Smuzhiyun 	&uart1_function,
363*4882a593Smuzhiyun 	&uart2_function,
364*4882a593Smuzhiyun 	&uart3_function,
365*4882a593Smuzhiyun 	&uart4_function,
366*4882a593Smuzhiyun 	&uart5_function,
367*4882a593Smuzhiyun 	&fsmc_function,
368*4882a593Smuzhiyun 	&rs485_0_function,
369*4882a593Smuzhiyun 	&rs485_1_function,
370*4882a593Smuzhiyun 	&tdm_function,
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun static const struct of_device_id spear310_pinctrl_of_match[] = {
374*4882a593Smuzhiyun 	{
375*4882a593Smuzhiyun 		.compatible = "st,spear310-pinmux",
376*4882a593Smuzhiyun 	},
377*4882a593Smuzhiyun 	{},
378*4882a593Smuzhiyun };
379*4882a593Smuzhiyun 
spear310_pinctrl_probe(struct platform_device * pdev)380*4882a593Smuzhiyun static int spear310_pinctrl_probe(struct platform_device *pdev)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	spear3xx_machdata.groups = spear310_pingroups;
383*4882a593Smuzhiyun 	spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
384*4882a593Smuzhiyun 	spear3xx_machdata.functions = spear310_functions;
385*4882a593Smuzhiyun 	spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
388*4882a593Smuzhiyun 	pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
389*4882a593Smuzhiyun 			spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	spear3xx_machdata.modes_supported = false;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	return spear_pinctrl_probe(pdev, &spear3xx_machdata);
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun static struct platform_driver spear310_pinctrl_driver = {
397*4882a593Smuzhiyun 	.driver = {
398*4882a593Smuzhiyun 		.name = DRIVER_NAME,
399*4882a593Smuzhiyun 		.of_match_table = spear310_pinctrl_of_match,
400*4882a593Smuzhiyun 	},
401*4882a593Smuzhiyun 	.probe = spear310_pinctrl_probe,
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun 
spear310_pinctrl_init(void)404*4882a593Smuzhiyun static int __init spear310_pinctrl_init(void)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun 	return platform_driver_register(&spear310_pinctrl_driver);
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun arch_initcall(spear310_pinctrl_init);
409