1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * pinmux driver shared headfile for CSR SiRFsoc 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __PINMUX_SIRF_H__ 9*4882a593Smuzhiyun #define __PINMUX_SIRF_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define SIRFSOC_NUM_PADS 622 12*4882a593Smuzhiyun #define SIRFSOC_RSC_USB_UART_SHARE 0 13*4882a593Smuzhiyun #define SIRFSOC_RSC_PIN_MUX 0x4 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) 16*4882a593Smuzhiyun #define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90) 17*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4) 18*4882a593Smuzhiyun #define SIRFSOC_GPIO_DSP_EN0 (0x80) 19*4882a593Smuzhiyun #define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1 22*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2 23*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4 24*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8 25*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10 26*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20 27*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40 28*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80 29*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_PULL_MASK 0x100 30*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200 31*4882a593Smuzhiyun #define SIRFSOC_GPIO_CTL_DSP_INT 0x400 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define SIRFSOC_GPIO_NO_OF_BANKS 5 34*4882a593Smuzhiyun #define SIRFSOC_GPIO_BANK_SIZE 32 35*4882a593Smuzhiyun #define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index)) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /** 38*4882a593Smuzhiyun * @dev: a pointer back to containing device 39*4882a593Smuzhiyun * @virtbase: the offset to the controller in virtual memory 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun struct sirfsoc_pmx { 42*4882a593Smuzhiyun struct device *dev; 43*4882a593Smuzhiyun struct pinctrl_dev *pmx; 44*4882a593Smuzhiyun void __iomem *gpio_virtbase; 45*4882a593Smuzhiyun void __iomem *rsc_virtbase; 46*4882a593Smuzhiyun u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE]; 47*4882a593Smuzhiyun u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS]; 48*4882a593Smuzhiyun u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS]; 49*4882a593Smuzhiyun u32 dspen_regs; 50*4882a593Smuzhiyun u32 rsc_regs[3]; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* SIRFSOC_GPIO_PAD_EN set */ 54*4882a593Smuzhiyun struct sirfsoc_muxmask { 55*4882a593Smuzhiyun unsigned long group; 56*4882a593Smuzhiyun unsigned long mask; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct sirfsoc_padmux { 60*4882a593Smuzhiyun unsigned long muxmask_counts; 61*4882a593Smuzhiyun const struct sirfsoc_muxmask *muxmask; 62*4882a593Smuzhiyun /* RSC_PIN_MUX set */ 63*4882a593Smuzhiyun unsigned long ctrlreg; 64*4882a593Smuzhiyun unsigned long funcmask; 65*4882a593Smuzhiyun unsigned long funcval; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /** 69*4882a593Smuzhiyun * struct sirfsoc_pin_group - describes a SiRFprimaII pin group 70*4882a593Smuzhiyun * @name: the name of this specific pin group 71*4882a593Smuzhiyun * @pins: an array of discrete physical pins used in this group, taken 72*4882a593Smuzhiyun * from the driver-local pin enumeration space 73*4882a593Smuzhiyun * @num_pins: the number of pins in this group array, i.e. the number of 74*4882a593Smuzhiyun * elements in .pins so we can iterate over that array 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun struct sirfsoc_pin_group { 77*4882a593Smuzhiyun const char *name; 78*4882a593Smuzhiyun const unsigned int *pins; 79*4882a593Smuzhiyun const unsigned num_pins; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define SIRFSOC_PIN_GROUP(n, p) \ 83*4882a593Smuzhiyun { \ 84*4882a593Smuzhiyun .name = n, \ 85*4882a593Smuzhiyun .pins = p, \ 86*4882a593Smuzhiyun .num_pins = ARRAY_SIZE(p), \ 87*4882a593Smuzhiyun } 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct sirfsoc_pmx_func { 90*4882a593Smuzhiyun const char *name; 91*4882a593Smuzhiyun const char * const *groups; 92*4882a593Smuzhiyun const unsigned num_groups; 93*4882a593Smuzhiyun const struct sirfsoc_padmux *padmux; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define SIRFSOC_PMX_FUNCTION(n, g, m) \ 97*4882a593Smuzhiyun { \ 98*4882a593Smuzhiyun .name = n, \ 99*4882a593Smuzhiyun .groups = g, \ 100*4882a593Smuzhiyun .num_groups = ARRAY_SIZE(g), \ 101*4882a593Smuzhiyun .padmux = &m, \ 102*4882a593Smuzhiyun } 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct sirfsoc_pinctrl_data { 105*4882a593Smuzhiyun struct pinctrl_pin_desc *pads; 106*4882a593Smuzhiyun int pads_cnt; 107*4882a593Smuzhiyun struct sirfsoc_pin_group *grps; 108*4882a593Smuzhiyun int grps_cnt; 109*4882a593Smuzhiyun struct sirfsoc_pmx_func *funcs; 110*4882a593Smuzhiyun int funcs_cnt; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun extern struct sirfsoc_pinctrl_data prima2_pinctrl_data; 114*4882a593Smuzhiyun extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif 117