1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * SuperH Pin Function Controller support. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Renesas Solutions Corp. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __SH_PFC_CORE_H__ 8*4882a593Smuzhiyun #define __SH_PFC_CORE_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "sh_pfc.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct sh_pfc_pin_range { 15*4882a593Smuzhiyun u16 start; 16*4882a593Smuzhiyun u16 end; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun int sh_pfc_register_gpiochip(struct sh_pfc *pfc); 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun int sh_pfc_register_pinctrl(struct sh_pfc *pfc); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width); 24*4882a593Smuzhiyun void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 25*4882a593Smuzhiyun u32 data); 26*4882a593Smuzhiyun u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg); 27*4882a593Smuzhiyun void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); 30*4882a593Smuzhiyun int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun const struct pinmux_bias_reg * 33*4882a593Smuzhiyun sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, 34*4882a593Smuzhiyun unsigned int *bit); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __SH_PFC_CORE_H__ */ 37